JP5165967B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5165967B2 JP5165967B2 JP2007215550A JP2007215550A JP5165967B2 JP 5165967 B2 JP5165967 B2 JP 5165967B2 JP 2007215550 A JP2007215550 A JP 2007215550A JP 2007215550 A JP2007215550 A JP 2007215550A JP 5165967 B2 JP5165967 B2 JP 5165967B2
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- metal wiring
- mos transistor
- type mos
- electrically connected
- esd protection
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- 239000004065 semiconductor Substances 0.000 title claims description 17
- 239000002184 metal Substances 0.000 claims description 70
- 239000003870 refractory metal Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
102 第2のソース領域
103 第2のソース領域
201 ゲート電極
301 第1のドレイン領域
302 第2のドレイン領域
601 ビアホール
701 グランド電位供給ライン
711 第2のメタル配線
801 外部接続端子
811 第1のメタル配線
901 第1のメタル配線
Claims (6)
- 外部接続端子と電気的に接続された複数のドレイン領域とグランド電位供給ラインと電気的に接続された複数のソース領域とが交互に配置され、隣り合う前記ドレイン領域と前記ソース領域との間にゲート電極が配置された、複数のトランジスタが一体化したESD保護用のN型MOSトランジスタを備える半導体装置において、
前記複数のソース領域にそれぞれ配置され、接続された第1のメタル配線は、前記第1のメタル配線よりも一層上の第2のメタル配線と、前記複数のソース領域の上で、前記第1のメタル配線の上にそれぞれ配置されたビアホールによって電気的に接続され、
前記第2のメタル配線は前記グランド電位供給ラインから前記ESD保護用のN型MOSトランジスタのチャネル幅方向と垂直な方向に配線され、
前記第1のメタル配線の上にそれぞれ配置された前記ビアホールの数は、前記ビアホールの下に位置する前記ソース領域が前記グランド電位供給ラインから遠くなるほど、多くなっていることを特徴とする半導体装置。 - 前記第2のメタル配線は、前記グランド電位供給ラインから遠くなるほど、前記N型MOSトランジスタのチャネル幅方向に太く形成されていることを特徴とする請求項1記載の半導体装置。
- 外部接続端子と電気的に接続された複数のドレイン領域とグランド電位供給ラインと電気的に接続された複数のソース領域とが交互に配置され、隣り合う前記ドレイン領域と前記ソース領域との間にゲート電極が配置された、複数のトランジスタが一体化したESD保護用のN型MOSトランジスタを備える半導体装置において、
前記複数のドレイン領域にそれぞれ配置され、接続された第1のメタル配線は、前記第1のメタル配線よりも一層上の第2のメタル配線と、前記複数のドレイン領域の上で、前記第1のメタル配線の上にそれぞれ配置されたビアホールによって電気的に接続され、
前記第2のメタル配線は前記外部接続端子から前記ESD保護用のN型MOSトランジスタのチャネル幅方向と垂直な方向に配線され、
前記第1のメタル配線の上にそれぞれ設けられた前記ビアホールの数は、前記ビアホールの下に位置する前記ドレイン領域が前記外部接続端子から遠くなるほど、多くなっていることを特徴とする半導体装置。 - 前記第2のメタル配線は、前記外部接続端子から遠くなるほど、前記N型MOSトランジスタのチャネル幅方向に太く形成されていることを特徴とする請求項3記載の半導体装置。
- 外部接続端子と電気的に接続された複数のドレイン領域とグランド電位供給ラインと電気的に接続された複数のソース領域とが交互に配置され、隣り合う前記ドレイン領域と前記ソース領域との間にゲート電極が配置された、複数のトランジスタが一体化したESD保護用のN型MOSトランジスタを備える半導体装置において、
前記複数のソース領域にそれぞれ配置され、接続された第1のメタル配線は、前記第1のメタル配線よりも一層上の第2のメタル配線と、前記複数のソース領域の上で、前記第1のメタル配線の上にそれぞれ配置されたビアホールによって電気的に接続され、
前記第2のメタル配線は前記グランド電位供給ラインから前記ESD保護用のN型MOSトランジスタのチャネル幅方向と垂直な方向に配線され、
前記第1のメタル配線の上にそれぞれ配置された前記ビアホールの数は、前記ビアホールの下に位置する前記ソース領域と前記グランド電位供給ラインとの間の抵抗が前記複数のソース領域のそれぞれにおいて等しくなるように、設定されていることを特徴とする半導体装置。 - 外部接続端子と電気的に接続された複数のドレイン領域とグランド電位供給ラインと電気的に接続された複数のソース領域とが交互に配置され、隣り合う前記ドレイン領域と前記ソース領域との間にゲート電極が配置された、複数のトランジスタが一体化したESD保護用のN型MOSトランジスタを備える半導体装置において、
前記複数のドレイン領域にそれぞれ配置され、接続された第1のメタル配線は、前記第1のメタル配線よりも一層上の第2のメタル配線と、前記複数のドレイン領域の上で、前記第1のメタル配線の上にそれぞれ配置されたビアホールによって電気的に接続され、
前記第2のメタル配線は前記外部接続端子から前記ESD保護用のN型MOSトランジスタのチャネル幅方向と垂直な方向に配線され、
前記第1のメタル配線の上にそれぞれ配置された前記ビアホールの数は、前記ビアホールの下に位置する前記ドレイン領域と前記外部接続端子との間の抵抗が前記複数のドレイン領域のそれぞれにおいて等しくなるように、設定されていることを特徴とする半導体装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007215550A JP5165967B2 (ja) | 2007-08-22 | 2007-08-22 | 半導体装置 |
US12/191,693 US7750409B2 (en) | 2007-08-22 | 2008-08-14 | Semiconductor device |
TW97131421A TWI467739B (zh) | 2007-08-22 | 2008-08-18 | 半導體裝置 |
CN2008101611651A CN101373766B (zh) | 2007-08-22 | 2008-08-22 | 半导体器件 |
KR1020080082596A KR101475952B1 (ko) | 2007-08-22 | 2008-08-22 | 반도체 디바이스 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007215550A JP5165967B2 (ja) | 2007-08-22 | 2007-08-22 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009049259A JP2009049259A (ja) | 2009-03-05 |
JP5165967B2 true JP5165967B2 (ja) | 2013-03-21 |
Family
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Application Number | Title | Priority Date | Filing Date |
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JP2007215550A Active JP5165967B2 (ja) | 2007-08-22 | 2007-08-22 | 半導体装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7750409B2 (ja) |
JP (1) | JP5165967B2 (ja) |
KR (1) | KR101475952B1 (ja) |
CN (1) | CN101373766B (ja) |
TW (1) | TWI467739B (ja) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7483001B2 (en) * | 2001-11-21 | 2009-01-27 | Seiko Epson Corporation | Active matrix substrate, electro-optical device, and electronic device |
KR100996174B1 (ko) * | 2008-12-15 | 2010-11-24 | 주식회사 하이닉스반도체 | 멀티 핑거 트랜지스터를 구비한 정전기 방전 회로 |
JP5603089B2 (ja) * | 2009-02-23 | 2014-10-08 | セイコーインスツル株式会社 | 半導体装置 |
JP2011071329A (ja) * | 2009-09-25 | 2011-04-07 | Seiko Instruments Inc | 半導体装置 |
JP5546191B2 (ja) * | 2009-09-25 | 2014-07-09 | セイコーインスツル株式会社 | 半導体装置 |
JP5529607B2 (ja) * | 2010-03-29 | 2014-06-25 | セイコーインスツル株式会社 | 半導体装置 |
JP5701684B2 (ja) * | 2011-05-23 | 2015-04-15 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 半導体装置 |
KR101668885B1 (ko) * | 2011-07-01 | 2016-10-25 | 매그나칩 반도체 유한회사 | Esd 보호 소자 |
JP2013110269A (ja) * | 2011-11-21 | 2013-06-06 | Samsung Electro-Mechanics Co Ltd | Cmos集積回路及び増幅回路 |
JP6099985B2 (ja) * | 2013-01-18 | 2017-03-22 | エスアイアイ・セミコンダクタ株式会社 | 半導体装置 |
CN105097926A (zh) * | 2014-05-22 | 2015-11-25 | 上海北京大学微电子研究院 | 一种新型的射频晶体管版图结构 |
CN106200160A (zh) * | 2016-07-08 | 2016-12-07 | 京东方科技集团股份有限公司 | 阵列基板、显示面板及显示装置 |
KR20220104423A (ko) | 2021-01-18 | 2022-07-26 | 성기봉 | 페달엔진자전거(실용모델) |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE68922767T2 (de) * | 1988-03-18 | 1995-09-28 | Fujitsu Ltd | Verbindungsstruktur zum Verbinden von Leitern in einem elektronischen Apparat. |
JPH0834246B2 (ja) * | 1988-03-18 | 1996-03-29 | 富士通株式会社 | 配線パターン接続構造 |
JPH0745829A (ja) | 1993-07-28 | 1995-02-14 | Ricoh Co Ltd | 半導体集積回路装置 |
KR0164496B1 (ko) * | 1995-12-02 | 1998-12-15 | 김광호 | 정전기보호소자 |
KR100203054B1 (ko) * | 1995-12-02 | 1999-06-15 | 윤종용 | 개선된 정전기 방전 능력을 갖는 집적 회로 |
JP2005019452A (ja) * | 2003-06-23 | 2005-01-20 | Toshiba Corp | 半導体装置 |
JP4170210B2 (ja) * | 2003-12-19 | 2008-10-22 | Necエレクトロニクス株式会社 | 半導体装置 |
US7511345B2 (en) * | 2005-06-21 | 2009-03-31 | Sarnoff Corporation | Bulk resistance control technique |
CN100561738C (zh) * | 2006-06-12 | 2009-11-18 | 中芯国际集成电路制造(上海)有限公司 | 利用多晶硅区的i/o esd保护的系统和方法 |
-
2007
- 2007-08-22 JP JP2007215550A patent/JP5165967B2/ja active Active
-
2008
- 2008-08-14 US US12/191,693 patent/US7750409B2/en not_active Expired - Fee Related
- 2008-08-18 TW TW97131421A patent/TWI467739B/zh not_active IP Right Cessation
- 2008-08-22 CN CN2008101611651A patent/CN101373766B/zh active Active
- 2008-08-22 KR KR1020080082596A patent/KR101475952B1/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
KR20090020532A (ko) | 2009-02-26 |
CN101373766B (zh) | 2012-08-15 |
JP2009049259A (ja) | 2009-03-05 |
US20090050968A1 (en) | 2009-02-26 |
TW200929523A (en) | 2009-07-01 |
KR101475952B1 (ko) | 2014-12-23 |
US7750409B2 (en) | 2010-07-06 |
CN101373766A (zh) | 2009-02-25 |
TWI467739B (zh) | 2015-01-01 |
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