TWI575698B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TWI575698B
TWI575698B TW102148939A TW102148939A TWI575698B TW I575698 B TWI575698 B TW I575698B TW 102148939 A TW102148939 A TW 102148939A TW 102148939 A TW102148939 A TW 102148939A TW I575698 B TWI575698 B TW I575698B
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wiring
electrically connected
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semiconductor device
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TW201444050A (zh
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島崎洸一
廣瀬嘉胤
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精工半導體有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
    • H01L27/0277—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path involving a parasitic bipolar transistor triggered by the local electrical biasing of the layer acting as base of said parasitic bipolar transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

半導體裝置
本發明係關於具備ESD(靜電放電)保護電路用之NMOS電晶體的半導體裝置。
首先，針對以往之半導體裝置予以說明。圖2為表示以往之半導體裝置的俯視圖。
保護內部電路不受ESD破壞的ESD保護電路通常使用NMOS電晶體。該NMOS電晶體之圖案例如圖2所示般地佈局。
NMOS電晶體具備被交互配置之複數的源極5及複數的汲極4、源極5和汲極4之間的複數且偶數之通道、被設置在複數之通道之上方之複數的閘極3、與複數的源極5之中最遠端的源極5鄰接而被設置的背閘極1a及被埋入其他的源極5的背閘極1b，及被配置成包圍NMOS電晶體之背閘極1c(例如參照專利文獻1)。
[先前技術文獻] [專利文獻]
[專利文獻1]日本特開2008-193019號公報(圖3)
在此，在專利文獻1所揭示之技術中，構想以1個圖案佈局從複數的源極5之中最遠端的源極5朝背閘極1a及背閘極1c的各配線。如此一來，在該源極中，因配線之面積變寬，故配線之寄生電阻之值變小。因ESD所導致之突波電流流入ESD保護電路用之NMOS電晶體之時，因容易集中於配線之寄生電阻之值小的上述源極1，故容易集中於具有寬面積之配線的源極，容易產生因局部發熱所導致的破壞。即是，半導體裝置之ESD耐量容易變低。
本發明係鑒於上述課題創作出，提供ESD耐量高的半導體裝置。
本發明為了解決上述課題，提供一種半導體裝置，屬於具備ESD保護電路用之NMOS電晶體之半導體裝置，其特徵為具備：上述NMOS電晶體，其具備被交互配置之複數的源極及複數的汲極、在上述源極和上述汲極之間的複數且偶數的通道，被設置在複數的上述通道上之複數的閘極，及被配置在複數的上述源極中最遠端之上述源極附近的背閘極；接地電壓配線，其係被電性連接於外部連接 用之接地電壓墊；及輸入電壓配線，其係被電性連接於外部連接用之輸入電壓墊；複數的源極配線分別由相同形狀之金屬膜所構成，將複數的上述源極分別電性連接於上述接地電壓配線，複數的汲極配線分別由相同形狀之金屬膜所構成，將複數的上述汲極分別電性連接於上述輸入電壓配線，複數的閘極配線分別由金屬膜所構成，將複數的上述閘極分別電性連接於上述接地電壓配線，背閘極配線係由金屬膜所構成，從上述源極之上方的上述源極配線分離，將上述背閘極電性連接於上述接地電壓配線。
在本發明中，所有的源極配線之圖案被佈局成相同。如此一來，在NMOS電晶體中之突波電流容易在各源極配線均勻地流動。即是，突波電流難以集中。依此，因難以產生因局部發熱所導致的破壞，ESD耐量變高。
10‧‧‧NMOS電晶體
11‧‧‧閘極
12‧‧‧源極
13‧‧‧汲極
14‧‧‧背閘極
19‧‧‧接觸件
21‧‧‧閘極配線
22‧‧‧源極配線
22a‧‧‧接地電壓配線
23‧‧‧汲極配線
23a‧‧‧輸入電壓配線
24‧‧‧背閘極配線
圖1為表示半導體裝置的俯視圖。
圖2為表示以往之半導體裝置之俯視圖。
以下，針對本發明之實施型態，參考圖面而予以說明。
首先，針對半導體裝置之構成予以說明。圖1為表示 半導體裝置的俯視圖。
半導體裝置具備ESD保護電路用之NMOS電晶體10、接地電壓配線22a及輸入電壓配線23a。
NMOS電晶體10具備被交互配置之複數的源極12及複數的汲極13、源極12和汲極13之間的複數且偶數之通道、被設置在複數的通道上之複數的閘極11，及被配置在複數的源極12之中最遠端的源極12之附近的背閘極14。在此，NMOS電晶體10之通道長方向之最遠端的擴散區域為源極12。
接地電壓配線22a係被電性連接於外部連接用的接地電壓墊。輸入電壓配線23a係被電性連接於外部連接用的輸入電壓墊。複數的源極配線22分別由相同形狀之金屬膜所構成，經接觸件19，將複數的源極12分別電性連接於接地電壓配線22a。複數的汲極配線23分別由相同形狀之金屬膜所構成，經接觸件19，將複數的汲極12分別電性連接於輸入電壓配線23a。複數的閘極配線21分別由相同形狀之金屬膜所構成，經接觸件19，將複數的閘極11分別電性連接於接地電壓配線22a。背閘極配線24係由金屬膜所構成，經接觸件19，將背閘極14電性連接於接地電壓配線22a。再者，背閘極配線24係從源極12之上方的源極配線22分離。
在此，在NMOS電晶體10中，閘極11係在半導體基板上以多晶矽所構成。源極12及汲極13為被設置在P型之半導體基板之表面的N型之擴散區域。背閘極14為被 設置在P型之半導體基板之表面的P型之擴散區域。閘極配線21等之所有配線係在半導體基板上，以鋁或銅等之所構成。
接著，針對朝向外部連接用之輸入電壓墊的輸入電壓為一般之時，保護內部電路不受ESD(靜電放電)破壞之ESD保護電路用之NMOS電晶體10的動作，予以說明。
源極12和閘極11和背閘極14之電壓為接地電壓，汲極13之電壓為輸入電壓。依此，在一般時，NMOS電晶體10斷開，不對被施加至汲極13的輸入電壓造成影響。
接著，針對在外部連接用之輸入電壓墊流動因ESD所導致之突波電流之時的NMOS電晶體10之ESD保護動作予以說明。
因ESD所導致之突波電流從輸入電壓墊流入接地電壓墊。此時，NMOS電晶體10之寄生二極體藉由停頓動作，使該突波電流流向相反方向。如此一來，輸入電壓墊被電性連接於半導體裝置之內部電路，來自輸入電壓墊之突波電流不會流至內部電路。依此，內部電路被保護而不受突波電流破壞。
此時，朝向複數的源極12中之最遠端的源極12及背閘極14的各配線不會以1個圖案來佈局，使該些各配線分別兩個圖案來佈局。即是，所有的源極配線22之圖案被佈局成相同。如此一來，在NMOS電晶體10之突波電流容易在各源極配線22均勻地流動，突波電流難以集 中。依此，因難以產生因局部發熱所導致的破壞，半導體裝置之ESD耐量變高。
並且，各閘極11彼即使以多晶矽連接亦可。
再者，各閘極11即使非接地電壓配線22a而係分別連接於各源極配線22亦可。
再者，即使在各閘極11中，於閘極11和接地電壓配線22a之間存在電阻成分亦可。
再者，源極12和汲極13和背閘極14即使非P型之半導體基板而設置在P型阱之表面亦可。
10‧‧‧NMOS電晶體
11‧‧‧閘極
12‧‧‧源極
13‧‧‧汲極
14‧‧‧背閘極
19‧‧‧接觸件
21‧‧‧閘極配線
22‧‧‧源極配線
22a‧‧‧接地電壓配線
23‧‧‧汲極配線
23a‧‧‧輸入電壓配線
24‧‧‧背閘極配線

Claims (2)

  1. 一種半導體裝置，屬於具備ESD保護電路用之NMOS電晶體的半導體裝置，其特徵為具有：上述NMOS電晶體，其具備被交互配置之複數的源極及複數的汲極、被形成在上述源極和上述汲極之間的複數且偶數的通道，被設置在上述複數且偶數的通道上之複數的閘極，及被配置在上述複數的源極中最遠端之上述複數的源極附近的背閘極；接地電壓配線，其係被電性連接於外部連接用之接地電壓墊；輸入電壓配線，其係被電性連接於外部連接用之輸入電壓墊；複數的源極配線，其係以相同形狀之金屬膜而分別被構成，將上述複數的源極分別電性連接於上述接地電壓配線；複數的汲極配線，其係以相同形狀之金屬膜而分別被構成，將上述複數的汲極分別電性連接於上述輸入電壓配線；複數的閘極配線，其係以金屬膜而分別被構成，將上述複數的閘極分別電性連接於上述接地電壓配線；及背閘極配線，其係以金屬膜被構成，且從上述複數的源極配線分離，將上述背閘極電性連接於上述接地電壓配線。
  2. 如申請專利範圍第1項所記載之半導體裝置，其中 上述複數的閘極配線分別由相同形狀之金屬膜所構成。
TW102148939A 2013-01-18 2013-12-30 半導體裝置 TWI575698B (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090278207A1 (en) * 2008-05-07 2009-11-12 David Ross Greenberg Electromigration-Complaint High Performance FET Layout
US20120235210A1 (en) * 2011-03-18 2012-09-20 Fujitsu Semiconductor Limited Semiconductor device, manufacturing method and transistor circuit
US20120326235A1 (en) * 2011-06-22 2012-12-27 Semiconductor Components Industries, Llc Semiconductor device

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61216477A (ja) * 1985-03-22 1986-09-26 Nec Corp 半導体装置
JP3237110B2 (ja) * 1998-03-24 2001-12-10 日本電気株式会社 半導体装置
US6310379B1 (en) * 1999-06-03 2001-10-30 Texas Instruments Incorporated NMOS triggered NMOS ESD protection circuit using low voltage NMOS transistors
JP4620282B2 (ja) * 2001-04-24 2011-01-26 ルネサスエレクトロニクス株式会社 半導体装置
JP2007096211A (ja) * 2005-09-30 2007-04-12 Ricoh Co Ltd 半導体装置
JP5586819B2 (ja) * 2006-04-06 2014-09-10 ピーエスフォー ルクスコ エスエイアールエル 半導体装置
US7847904B2 (en) * 2006-06-02 2010-12-07 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device and electronic appliance
JP2008193019A (ja) 2007-02-08 2008-08-21 Matsushita Electric Ind Co Ltd 半導体集積回路装置
TWI456900B (zh) * 2011-11-17 2014-10-11 Global Unichip Corp 訊號延遲電路和訊號延遲方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090278207A1 (en) * 2008-05-07 2009-11-12 David Ross Greenberg Electromigration-Complaint High Performance FET Layout
US20120235210A1 (en) * 2011-03-18 2012-09-20 Fujitsu Semiconductor Limited Semiconductor device, manufacturing method and transistor circuit
US20120326235A1 (en) * 2011-06-22 2012-12-27 Semiconductor Components Industries, Llc Semiconductor device

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CN104919577A (zh) 2015-09-16
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EP2947681A4 (en) 2016-08-17
KR20150109360A (ko) 2015-10-01
WO2014112293A1 (ja) 2014-07-24
CN104919577B (zh) 2017-11-21
TW201444050A (zh) 2014-11-16
JP2014138146A (ja) 2014-07-28
US20150364464A1 (en) 2015-12-17
US9397088B2 (en) 2016-07-19
EP2947681A1 (en) 2015-11-25

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