CN104919577A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN104919577A
CN104919577A CN201380070544.9A CN201380070544A CN104919577A CN 104919577 A CN104919577 A CN 104919577A CN 201380070544 A CN201380070544 A CN 201380070544A CN 104919577 A CN104919577 A CN 104919577A
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electrically connected
metal film
semiconductor device
backgate
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CN104919577B (zh
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岛崎洸一
广濑嘉胤
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Ablic Inc
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Seiko Instruments Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
    • H01L27/0277—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path involving a parasitic bipolar transistor triggered by the local electrical biasing of the layer acting as base of said parasitic bipolar transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular

Abstract

为了提供ESD耐受能力高的半导体装置，多个源布线(22)分别由相同形状的金属膜构成，使多个源(12)分别与接地电压布线(22a)电连接，多个漏布线(23)分别由相同形状的金属膜构成，使多个漏(12)分别与输入电压布线(23a)电连接，多个栅布线(21)分别由相同形状的金属膜构成，使多个栅(11)分别与接地电压布线(22a)电连接。而且，背栅布线(24)由金属膜构成，使背栅(14)与接地电压布线(22a)电连接，背栅布线(24)从源(12)上的源布线(22)分离。

Description

半导体装置
技术领域
本发明涉及具备ESD(静电放电)保护电路用的NMOS晶体管的半导体装置。
背景技术
首先，对现有的半导体装置进行说明。图2是示出现有的半导体装置的俯视图。
在保护内部电路不受ESD的影响的ESD保护电路中，通常使用NMOS晶体管。该NMOS晶体管的样式(pattern)例如如图2所示那样布置。
NMOS晶体管具备：交替配置的多个源5和多个漏4；源5与漏4之间的多个且为偶数个的沟道(channel)；设于多个沟道之上的多个栅3；以及与多个源5中最端部的源5相邻配置的背栅1a、嵌入其他的源5中的背栅1b和包围NMOS晶体管而配置的背栅1c(例如，参照专利文献1)。
现有技术文献
专利文献
专利文献1：日本特开2008-193019号公报(图3)
发明内容
发明要解决的课题
这里，在专利文献1中公开的技术中，认为从多个源5中最端部的源5通向背栅1a以及背栅1c的各布线是以1种样式来布置的。因此，在该源中，由于布线的面积变大，布线的寄生电阻值变小。在基于ESD的浪涌电流流过ESD保护电路用的NMOS晶体管的情况下，由于容易在布线的寄生电阻值小的上述源1处集中，因此容易在具有较大面积的布线的源集中，容易产生由局部发热造成的破坏。即，半导体装置的ESD耐受能力容易变低。
本发明是鉴于上述课题而完成的，提供一种ESD耐受能力高的半导体装置。
用于解决课题的手段
本发明为了解决上述课题，提供一种半导体装置，其具备ESD保护电路用的NMOS晶体管，该半导体装置的特征在于，该半导体装置具备：上述NMOS晶体管，其具备交替配置的多个源和多个漏、在上述源与上述漏之间的多个且为偶数个的沟道、设于多个上述沟道之上的多个栅、以及配置于多个上述源中最端部的上述源的附近的背栅；接地电压布线，其与外部连接用的接地电压焊盘电连接；输入电压布线，其与外部连接用的输入电压焊盘电连接，多个源布线分别由相同形状的金属膜构成，使多个上述源分别与上述接地电压布线电连接，多个漏布线分别由相同形状的金属膜构成，使多个上述漏分别与上述输入电压布线电连接，多个栅布线分别由金属膜构成，使多个上述栅分别与上述接地电压布线电连接，背栅布线由金属膜构成，且从上述源上的上述源布线分离，使上述背栅与上述接地电压布线电连接。
发明效果
在本发明中，所有源布线是以相同样式来布置的。因此，NMOS晶体管中的浪涌电流在各源布线中容易均匀地流过。即，浪涌电流不容易集中。因而，不容易产生由局部发热造成的破坏，ESD耐受能力提高。
附图说明
图1是示出半导体装置的俯视图。
图2是示出现有的半导体装置的俯视图。
具体实施方式
以下，参照附图对本发明的实施方式进行说明。
首先，对半导体装置的结构进行说明。图1是示出半导体装置的俯视图。
半导体装置具备：ESD保护电路用的NMOS晶体管10、接地电压布线22a、以及输入电压布线23a。
NMOS晶体管10具备：交替配置的多个源12和多个漏13、源12与漏13之间的多个且为偶数个的沟道、设于多个沟道之上的多个栅11、以及配置于多个源12中最端部的源12附近的背栅14。这里，NMOS晶体管10的沟道长度方向的最端部的扩散区域是源12。
接地电压布线22a与外部连接用的接地电压焊盘电连接。输入电压布线23a与外部连接用的输入电压焊盘电连接。多个源布线22分别由相同形状的金属膜构成，经由接点19将多个源12分别电连接于接地电压布线22a。多个漏布线23分别由相同形状的金属膜构成，经由接点19将多个漏12分别电连接于输入电压布线23a。多个栅布线21分别由相同形状的金属膜构成，经由接点19将多个栅11分别电连接于接地电压布线22a。背栅布线24由金属膜构成，经由接点19将背栅14电连接于接地电压布线22a。此外，背栅布线24从源12上的源布线22分离。
这里，在NMOS晶体管10中，栅11在半导体基板上由多晶硅构成。源12以及漏13是设于P型的半导体基板的表面的N型的扩散区域。背栅14是设于P型的半导体基板的表面的P型的扩散区域。栅布线21等全部布线在半导体基板上由铝或者铜构成。
接下来，对向外部连接用的输入电压焊盘输入的输入电压是通常电压的情况下的、保护内部电路不受ESD(静电放电)的影响的ESD保护电路用的NMOS晶体管10的动作进行说明。
源12以及栅11以及背栅14的电压是接地电压，漏13的电压是输入电压。因而，通常时，NMOS晶体管10关闭，不会对漏13的输入电压带来影响。
接下来，对基于ESD的浪涌电流流过外部连接用的输入电压焊盘的情况下的NMOS晶体管10的ESD保护动作进行说明。
基于ESD的浪涌电流从输入电压焊盘流向接地电压焊盘。此时，NMOS晶体管10的寄生二极管通过击穿动作而使该浪涌电流朝相反方向流动。因此，输入电压焊盘与半导体装置的内部电路电连接，但是来自输入电压焊盘的浪涌电流不会在内部电路中流动。因而，保护了内部电路不受浪涌电流影响。
此时，通向多个源12中最端部的源12以及背栅14的各布线不是以1种样式来布置的，这些各布线是以不同的2种样式来布置的。即，所有源布线22是以相同样式来布置的。因此，NMOS晶体管10中的浪涌电流在各源布线22中容易均匀地流过，浪涌电流不容易集中。因而，不容易产生由局部发热造成的破坏，半导体装置的ESD耐受能力提高。
另外，各栅11彼此也可以通过多晶硅来连接。
此外，各栅11也可以分别与各源布线22连接，而不是与接地电压布线22a连接。
此外，在各栅11中，栅11与接地电压布线22a之间也可以存在电阻成分。
此外，源12、漏13以及背栅14也可以设于P型的阱的表面，而非设于P型的半导体基板。
标号说明
10：NMOS晶体管；11：栅；12：源；13：漏；14：背栅；19：接点；21：栅布线；22：源布线；22a：接地电压布线；23：漏布线；23a：输入电压布线；24：背栅布线。

Claims (2)

1.一种半导体装置，其具备ESD保护电路用的NMOS晶体管，其中，该半导体装置具有：
所述NMOS晶体管，其具备：交替配置的多个源和多个漏、形成于所述源与所述漏之间的多个且为偶数个的沟道、设于所述多个且为偶数个的沟道之上的多个栅、以及配置于所述多个源中最端部的所述多个源的附近的背栅；
接地电压布线，其与外部连接用的接地电压焊盘电连接；
输入电压布线，其与外部连接用的输入电压焊盘电连接；
多个源布线，其分别由相同形状的金属膜构成，使所述多个源分别与所述接地电压布线电连接；
多个漏布线，其分别由相同形状的金属膜构成，使所述多个漏分别与所述输入电压布线电连接；
多个栅布线，其分别由金属膜构成，使所述多个栅分别与所述接地电压布线电连接；以及
背栅布线，其由金属膜构成，且从所述多个源布线分离，使所述背栅与所述接地电压布线电连接。
2.根据权利要求1所述的半导体装置，其特征在于，
所述多个栅布线分别由相同形状的金属膜构成。
CN201380070544.9A 2013-01-18 2013-12-20 半导体装置 Expired - Fee Related CN104919577B (zh)

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JP2013-007153 2013-01-18
JP2013007153A JP6099986B2 (ja) 2013-01-18 2013-01-18 半導体装置
PCT/JP2013/084288 WO2014112293A1 (ja) 2013-01-18 2013-12-20 半導体装置

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JPS61216477A (ja) * 1985-03-22 1986-09-26 Nec Corp 半導体装置
CN1230023A (zh) * 1998-03-24 1999-09-29 日本电气株式会社 带有保护电路的半导体器件
US20070235809A1 (en) * 2006-04-06 2007-10-11 Elpida Memory, Inc. Semiconductor device
CN102842576A (zh) * 2011-06-22 2012-12-26 半导体元件工业有限责任公司 半导体装置

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KR102082643B1 (ko) 2020-02-28
WO2014112293A1 (ja) 2014-07-24
JP6099986B2 (ja) 2017-03-22
CN104919577B (zh) 2017-11-21
US20150364464A1 (en) 2015-12-17
EP2947681A1 (en) 2015-11-25
TWI575698B (zh) 2017-03-21
JP2014138146A (ja) 2014-07-28
KR20150109360A (ko) 2015-10-01
TW201444050A (zh) 2014-11-16
US9397088B2 (en) 2016-07-19
EP2947681A4 (en) 2016-08-17

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