CN104937701B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN104937701B
CN104937701B CN201380070741.0A CN201380070741A CN104937701B CN 104937701 B CN104937701 B CN 104937701B CN 201380070741 A CN201380070741 A CN 201380070741A CN 104937701 B CN104937701 B CN 104937701B
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岛崎洸
岛崎洸一
广濑嘉胤
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Ablic Inc
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    • H—ELECTRICITY
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    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
    • H01L27/0277—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path involving a parasitic bipolar transistor triggered by the local electrical biasing of the layer acting as base of said parasitic bipolar transistor
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/42312—Gate electrodes for field effect devices
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    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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Abstract

为了提供ESD耐受能力高的半导体装置，形成了如下的半导体装置(IC)：接地电压布线(22a)通过自身的布线方向的一端与接自外部连接用的接地电压焊盘的布线(22b)电连接，输入电压布线(23a)通过自身的布线方向的一端与接自外部连接用的输入电压焊盘的布线(23b)电连接，接地电压布线(22a)的一端和输入电压布线(23a)的一端以NMOS晶体管(10)的中心为中心而大致对置。

Description

半导体装置
技术领域
本发明涉及具有ESD(静电放电)保护电路用的NMOS晶体管的半导体装置。
背景技术
首先，对以往的半导体装置进行说明。图2是示出以往的半导体装置的俯视图。
在保护内部电路不受ESD影响的ESD保护电路中，通常使用NMOS晶体管。该NMOS晶体管的样式(pattern)例如如图2所示那样布置。
NMOS晶体管90具有交替配置的多个源和多个漏、形成在各个源与漏之间的多个且为偶数个的沟道、以及设置在各个沟道上的栅98。栅98是多指型的栅，由一个多晶硅构成，各源分别与源布线99连接，各漏分别与漏布线97连接。该漏布线97被延长而与焊盘80连接(例如参照专利文献1)。
现有技术文献
专利文献
专利文献1：日本特开2005-294740号公报(图1)
发明内容
发明所要解决的课题
这里，在由专利文献1公开的技术中，在图2中，由于源布线99被从图的下方连接，因此NMOS晶体管90的面对图中下方的沟道的源布线99的寄生电阻的值比面对图中上方的沟道的源布线99的寄生电阻的值低。即，与各沟道相关的源布线99的寄生电阻的值不同。
因此，在各沟道中，难以均匀地流动基于ESD的浪涌电流。换个角度来看，浪涌电流容易集中于特定的沟道。这里，浪涌电流容易集中于图中下方的沟道。因此，在ESD保护电路用的NMOS晶体管90中，容易产生局部发热所引起的损坏，从而导致ESD耐受能力降低。
本发明是鉴于上述课题而完成，提供一种ESD耐受能力高的半导体装置。
用于解决课题的手段
本发明为了解决上述课题，提供一种半导体装置，该半导体装置具有ESD保护电路用的NMOS晶体管，该半导体装置的特征在于，具有：所述NMOS晶体管，其具有交替配置的多个源和多个漏、所述源与所述漏之间的多个且为偶数个的沟道、以及设置在多个所述沟道上的多个栅；接地电压布线，其通过自身的布线方向的一端与接自外部连接用的接地电压焊盘的布线电连接；输入电压布线，其通过自身的布线方向的一端与接自外部连接用的输入电压焊盘的布线电连接；多个源布线，它们分别将所述接地电压布线和多个所述源电连接；多个漏布线，它们分别将所述输入电压布线和多个所述漏电连接；以及多个栅布线，它们分别将所述接地电压布线和多个所述栅电连接，所述接地电压布线的一端和所述输入电压布线的一端以所述NMOS晶体管的中心为中心而大致对置。
发明的效果
本发明中，在NMOS晶体管的各沟道中，虽然与各沟道相关的源布线和漏布线的寄生电阻的值不同，但源布线的寄生电阻和漏布线的寄生电阻的合计电阻值大致相等。这样，在各沟道中容易均匀地流过浪涌电流。即，浪涌电流难以集中于特定的沟道。因此，在ESD保护电路用的NMOS晶体管中，不易产生因局部发热所引起的破坏，ESD耐受能力提高。
附图说明
图1是半导体装置的俯视图。
图2是示出以往的半导体装置的俯视图。
具体实施方式
以下，参照附图来说明本发明的实施方式。
首先，对半导体装置的结构进行说明。图1是示出半导体装置的俯视图。
半导体装置具有ESD保护电路用的NMOS晶体管10、接地电压布线22a以及输入电压布线23a。NMOS晶体管10具备：交替配置的多个源12和多个漏13；源12与漏13之间的多个且为偶数个的沟道；设置在多个沟道上的多个栅11；以及被配置成包围源12和漏13的背栅14。这里，NMOS晶体管10的沟道长度方向的最端部的扩散区域是源12。
这里，接地电压布线22a大致形成为长方形，并且通过自身的布线方向的一端与接自外部连接用的接地电压焊盘的布线22b电连接。即，在图1中，接自外部连接用的接地电压焊盘的布线22b从左侧连接于接地电压布线22a，所连接的一端沿图的上下方向延伸。同样，输入电压布线23a大致形成为长方形，并且通过自身的布线方向的另一端与接自外部连接用的输入电压焊盘的布线23b电连接。即，在图1中，接自外部连接用的输入电压焊盘的布线23b从右侧连接于输入电压布线23a，所连接的另一端沿图的上下方向延伸。接地电压布线22a的一端和输入电压布线23a的另一端以NMOS晶体管10的中心为中心而大致对置。即，成为接近点对称的位置的配置。但此时，接地电压布线22a的一端与输入电压布线23a的另一端相对于图内的通过NMOS晶体管10的中心的水平线不能处于上下对称的位置。此外，接自外部连接用的接地电压焊盘的布线22b和接自外部连接用的输入电压焊盘的布线23b通常被配置为均与NMOS晶体管10的沟道长度方向平行。
多个源布线22分别将接地电压布线22a和经由接触区19连接的多个源12电连接。多个漏布线23分别将输入电压布线23a和经由接触区19连接的多个漏13电连接。多个栅布线21分别将接地电压布线22a和经由接触区19连接的多个栅11电连接。背栅布线24将接地电压布线22a和经由接触区19连接的背栅14电连接。
这里，栅11在半导体衬底上由多晶硅构成。源12和漏13是设置于P型的半导体衬底的表面的N型的扩散区域。背栅14是设置于P型的半导体衬底的表面的P型的扩散区域。源布线22等所有的布线在半导体衬底上由铝或铜等的金属膜构成。
此外，多个源布线22分别由相同形状的金属膜形成。多个漏布线23分别由相同形状的金属膜形成。多个栅布线21分别由相同形状的金属膜形成。
接着，对向外部连接用的输入电压焊盘输入的输入电压是通常电压的情况下的、保护内部电路不受ESD(静电放电)影响的ESD保护电路用的NMOS晶体管10的动作进行说明。
源12、栅11以及背栅14的电压是接地电压，漏13的电压是输入电压。因此，在通常时，NMOS晶体管10截止，不会对施加于漏13的输入电压产生影响。
接着，对基于ESD的浪涌电流流过外部连接用的输入电压焊盘的情况下的、NMOS晶体管10的ESD保护动作进行说明。
基于ESD的浪涌电流从输入电压焊盘流向接地电压焊盘。此时，NMOS晶体管10的寄生二极管通过击穿动作使该浪涌电流朝反方向流动。这样，虽然输入电压焊盘与半导体装置的内部电路电连接，但来自输入电压焊盘的浪涌电流不会流向内部电路。因此，保护了内部电路不受浪涌电流影响。
此时，在NMOS晶体管10中，在接近接自接地电压焊盘的布线22b的源12中，至接地电压焊盘为止的寄生电阻的值减小，在远离接自接地电压焊盘的布线22b的源12中，至接地电压焊盘为止的寄生电阻的值增大。同样，在接近接自输入电压焊盘的布线23b的漏13中，至输入电压焊盘为止的寄生电阻的值减小，在远离接自输入电压焊盘的布线23b的漏13中，至输入电压焊盘为止的寄生电阻的值增大。即，在NMOS晶体管10的各沟道中，与各沟道相关的源布线22和漏布线23的寄生电阻的值不同，但源布线22的寄生电阻和漏布线23的寄生电阻的合计电阻的值大致相等。这样，在各沟道中容易均匀地流过浪涌电流。即，浪涌电流不易集中于特定的沟道。因此，在ESD保护电路用的NMOS晶体管10中，不易产生因局部发热所引起的破坏，ESD耐受能力提高。
因此，如果接地电压布线22a的一端和输入电压布线23a的另一端相对于图内的通过NMOS晶体管10的中心的水平线处于上下对称的位置，则无法得到这样的效果，并且在接近中心的沟道与远离中心的沟道之间会产生寄生电阻的差，从而难以进行均匀的动作。
另外，各栅11彼此可以通过多晶硅连接。
此外，各栅11可以不与接地电压布线22a而是分别与各源布线22连接。
此外，在各栅11中，在栅11与接地电压布线22a之间可以存在电阻成分。
此外，源12、漏13和背栅14可以不设置于P型的半导体衬底的表面而是设置于P型的阱的表面。
标号说明
10：NMOS晶体管；
11：栅；
12：源；
13：漏；
14：背栅；
19：接触区；
21：栅布线；
22：源布线；
22a：接地电压布线；
22b：接自接地电压焊盘的布线；
23：漏布线；
23a：输入电压布线；
23b：接自输入电压焊盘的布线；
24：背栅布线。

Claims (1)

1.一种半导体装置，其特征在于，所述半导体装置具有：
半导体衬底；
NMOS晶体管，其具备设置于所述半导体衬底的表面上的交替配置的多个源和多个漏、形成于所述多个源与所述多个漏之间的偶数个的沟道、配置在所述偶数个的沟道之上的多个栅、以及被配置成包围具有所述多个源和所述多个漏的区域的背栅；
接地电压布线，其通过多个源布线与所述多个源电连接；
输入电压布线，其通过多个漏布线与所述多个漏电连接；
多个栅布线，它们跨越所述背栅，分别将被所述背栅包围的区域外的所述接地电压布线和被所述背栅包围的区域内的所有的所述多个栅电连接；
接自外部连接用的接地电压焊盘的布线，其在所述接地电压布线的一端处电连接；以及
接自外部连接用的输入电压焊盘的布线，其在所述输入电压布线的另一端处电连接，
所述多个源布线跨越所述背栅，分别将被所述背栅包围的区域外的所述接地电压布线和被所述背栅包围的区域内的所有的所述多个源电连接，
所述多个漏布线跨越所述背栅，分别将被所述背栅包围的区域外的所述输入电压布线和被所述背栅包围的区域内的所有的所述多个漏电连接，
多个所述栅布线分别由相同形状的金属膜形成，
所述多个源布线分别由相同形状的金属膜形成，
所述多个漏布线分别由相同形状的金属膜形成，
所述接地电压布线的一端和所述输入电压布线的另一端以所述NMOS晶体管的中心为中心对置，
所述一端处的接自所述外部连接用的接地电压焊盘的布线和所述另一端处的接自所述外部连接用的输入电压焊盘的布线都被配置成与所述NMOS晶体管的沟道长度方向平行。
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