CN108873508B - 阵列基板的制造方法 - Google Patents
阵列基板的制造方法 Download PDFInfo
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- CN108873508B CN108873508B CN201811056603.8A CN201811056603A CN108873508B CN 108873508 B CN108873508 B CN 108873508B CN 201811056603 A CN201811056603 A CN 201811056603A CN 108873508 B CN108873508 B CN 108873508B
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- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
一种阵列基板的制造方法包括以下步骤。形成多条扫描线于基底上,基底具有像素区以及扇出区。形成多条数据线。形成多个晶体管,多个晶体管各自与对应的扫描线以及对应的数据线电性连接。形成多个共同电极。形成多个像素电极,多个像素电极各自与对应的晶体管电性连接。按序形成多条第一扇出线、多条第二扇出线以及多条第三扇出线于扇出区内。多条第三扇出线包括透明导电层以及辅助导电层。辅助导电层位于透明导电层上且与透明导电层接触。第三扇出线与多个共同电极是通过相同的掩模形成。
Description
技术领域
本发明涉及一种阵列基板的制造方法,特别涉及一种显示面板的阵列基板的制造方法。
背景技术
近年来,显示面板的设计朝向减少阵列基板的周边区面积发展,故周边区中的部分扇出线必须改为由不同导电层彼此堆叠的形式,以适应周边区的缩减。然而,形成更多的导电层须增加使用的掩模数,而导致制造成本的增加。
发明内容
本发明的至少一实施例提供一种阵列基板的制造方法,其使用的掩模数减少,因此可降低制造阵列基板的成本。
本发明的至少一实施例的阵列基板的制造方法包括以下步骤。形成多条扫描线于基底上,基底具有像素区以及扇出区。形成多条数据线。形成多个晶体管,多个晶体管各自与对应的扫描线以及对应的数据线电性连接。形成多个共同电极。形成多个像素电极,多个像素电极各自与对应的晶体管电性连接。按序形成多条第一扇出线、多条第二扇出线以及多条第三扇出线于扇出区内。多条第三扇出线包括透明导电层以及辅助导电层。辅助导电层位于透明导电层上且与透明导电层接触。第三扇出线与多个共同电极是通过相同的掩模形成。
本发明的至少一实施例的阵列基板的制造方法包括以下步骤。形成第一金属层于基底上,基底包括像素区及扇出区,且第一金属层包括多个栅极与多条扫描线位于像素区以及多条第一扇出线位于扇出区。形成栅极绝缘层于第一金属层上。形成第二金属层于栅极绝缘层上,第二金属层包括多个源极、多个漏极与多条数据线位于像素区以及多条第二扇出线位于扇出区。形成第一绝缘层于第二金属层上。通过掩模形成第一导电层以及第三金属层于第一绝缘层上,第一导电层包括多个透明导电层位于扇出区以及多个共同电极位于像素区,第三金属层包括多个辅助导电层位于扇出区,且多个辅助导电层分别位于多个透明导电层上以构成多条第三扇出线于扇出区。
基于上述,本发明的至少一实施例的阵列基板的制造方法通过使用同一掩模于扇出区中形成第一导电层以及第三金属层,因此可减少掩模的使用,借此可降低制造阵列基板的成本。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合说明书附图作详细说明如下。
附图说明
图1A至图1O为本发明一实施例的阵列基板的制造方法的剖面示意图。
图2A、图3A至图4A为本发明一实施例的阵列基板的制造方法的像素区的俯视图。
图2B、图3B至图4B为本发明一实施例的阵列基板的制造方法的扇出区的俯视图。
图5为本发明一实施例的阵列基板的俯视图。
图6A为图5中剖线C-C’的剖面示意图。
图6B为图5中剖线D-D’的剖面示意图。
图6C为图5中剖线E-E’的剖面示意图。
附图标记说明:
100:基底
100a:像素区
100b:扇出区
110:第一金属层
120:栅极绝缘层
130:第二金属层
140:第一绝缘层
150:第一导电层
150a:第一导电材料层
152:透明导电层
154:共同电极
160:第三金属层
160a:第三金属材料层
160b:剩余的第三金属材料层
162:辅助导电层
170:第二绝缘层
180:第二导电层
182:桥接电极
184:像素电极
184S:狭缝
186:连接电极
200:光刻胶层
200a:光刻胶材料层
202a:第一区域
204a、204b:第二区域
300、310、320、330、340、350:掩模
300a:第一区
300b:第二区
A-A’、B-B’、C-C’、D-D’、E-E’:剖线
D:漏极
DL:数据线
F1:第一扇出线
F11、F21、F31:延伸部
F2:第二扇出线
F3:第三扇出线
G:栅极
H11、H12、H2、H3、H41、H42、H51、H52、H61、H62:接触窗
L11、L21、L31:延伸方向
P1:第一接垫
P2:第二接垫
P3:第三接垫
PL:平坦层
S:源极
SE:半导体层
SL:扫描线
T:主动元件
TP:触控信号线
具体实施方式
以下将参照本实施例的附图以更全面地阐述本发明。然而,本发明亦可以各种不同的形式体现,而不应限于本文中所述的实施例。附图中的层与区域的厚度会为了清楚起见而放大。相同或相似的参考号码表示相同或相似的元件,以下段落将不再一一赘述。另外,实施例中所提到的方向用语,例如:上、下、左、右、前或后等,仅是参考附加附图的方向。因此,使用的方向用语是用来说明并非用来限制本发明。
图1A至图1O为本发明一实施例的阵列基板的制造方法的剖面示意图,图2A、图3A至图4A为本发明一实施例的阵列基板的制造方法的像素区的俯视图,图2B、图3B至图4B为本发明一实施例的阵列基板的制造方法的扇出区的俯视图。图5为本发明一实施例的阵列基板的俯视图。图1A为图2A中剖线A-A’及图2B中剖线B-B’的剖面示意图,图1D为图3A中剖线A-A’及图3B中剖线B-B’的剖面示意图,图1L为图4A中剖线A-A’及图4B中剖线B-B’的剖面示意图,图1O为图5中剖线A-A’及剖线B-B’的剖面示意图。图6A为图5中剖线C-C’的剖面示意图,图6B为图5中剖线D-D’的剖面示意图,图6C为图5中剖线E-E’的剖面示意图。
请同时参照图1A、图2A以及图2B,形成第一金属层110于基底100上。基底100可为柔性基板,例如聚合物基板或塑胶基板,但本发明并不限于此。在其他实施方式中,基底100也可以是刚性基板,例如玻璃基板、石英基板或硅基板。基底100具有像素区100a以及位于像素区100a外的扇出区100b。在一些实施例中,基底100可选择性地包括矩形像素区100a以及连接于像素区100a下方的颈状扇出区100b。然而,本发明不限于此,在其他实施例中,基底100的外型可依实际需求做不同设计。
第一金属层110的形成方法例如是利用物理气相沉积法或金属化学气相沉积法后再进行光刻蚀刻工艺而形成。举例来说,可先利用物理气相沉积法或金属化学气相沉积法于基底100上全面性地形成第一金属材料层(未示出)。接着,于第一金属材料层上形成光刻胶材料层(未示出)。请参考图1A,利用掩模300对光刻胶材料层(未示出)进行光刻工艺,以形成图案化光刻胶层(未示出)。之后,以图案化光刻胶层为掩模,对第一金属材料层进行蚀刻工艺,以形成第一金属层110。在本实施方式中,第一金属层110是利用掩模300以第一道光刻蚀刻工艺形成。
第一金属层110可包括多条扫描线SL、多个栅极G、多条第一扇出线F1、多个第一接垫P1、多个第二接垫P2以及多个第三接垫P3,为方便说明,在此仅显示两条扫描线SL、两个第一接垫P1、两个第二接垫P2以及两个第三接垫P3,但本发明不以此为限。在本实施例中,可同时形成多条扫描线SL、多个栅极G、多条第一扇出线F1、多个第一接垫P1、多个第二接垫P2以及多个第三接垫P3。多条扫描线SL以及多个栅极G位于像素区100a,多条第一扇出线F1、第一接垫P1、多个第二接垫P2以及多个第三接垫P3位于扇出区100b。各个栅极G与对应的扫描线SL电性连接。各个第一接垫P与对应的第一扇出线F1连接,而多个第二接垫P2以及多个第三接垫P3则会分别与后续形成的扇出线电性连接。各个第一扇出线F1具有第一延伸部F11沿延伸方向L11延伸,延伸方向L11例如不平行于各扫描线SL的延伸方向。
接下来,请参考图1B,形成栅极绝缘层120于第一金属层110上。栅极绝缘层120可覆盖扫描线SL、栅极G、第一扇出线F1、第一接垫P1、第二接垫P2以及第三接垫P3。栅极绝缘层120的形成方法例如是利用物理气相沉积法或化学气相沉积法而形成。在本实施例中,栅极绝缘层120的材料可为无机材料(例如:氧化硅、氮化硅、氮氧化硅、或上述至少二种材料的堆叠层)、有机材料(例如:聚酰亚胺是树脂、环氧是树脂或亚克力是树脂)或上述的组合,但本发明不以此为限。栅极绝缘层120可为单层结构,但本发明并不限于此。在其他实施例中,栅极绝缘层120也可为多层结构。
请继续参照图1C,在形成栅极绝缘层120后,形成多个半导体层SE于栅极绝缘层120上。多个半导体层SE的形成方法例如是利用光刻蚀刻工艺而形成。举例来说,可先利用物理气相沉积法或金属化学气相沉积法于栅极绝缘层120上全面性地形成半导体材料层(未示出)。接着,于半导体材料层上形成光刻胶材料层(未示出)。利用掩模310对光刻胶材料层(未示出)进行光刻工艺,以形成图案化光刻胶层(未示出)。之后,以图案化光刻胶层为掩模,对半导体材料层进行蚀刻工艺,以形成多个半导体层SE。在本实施方式中,多个半导体层SE是利用掩模310以第二道光刻蚀刻工艺形成。
在本实施例中,多个半导体层SE的材料可为非晶硅,但本发明不以此为限。多个半导体层SE的材料亦可为多晶硅、微晶硅、单晶硅、纳米晶硅或其它具有不同晶格排列的半导体材料或金属氧化物半导体材料。多个半导体层SE例如与多个栅极G相对应地设置。
请同时参照图1D、图3A以及图3B,形成第二金属层130于栅极绝缘层120上。第二金属层130的形成方法例如是利用物理气相沉积法或金属化学气相沉积法后再进行光刻蚀刻工艺而形成。举例来说,可先利用物理气相沉积法或金属化学气相沉积法于基底100上全面性地形成第二金属材料层(未示出)以覆盖栅极绝缘层120以及半导体层SE。接着,于第二金属材料层上形成光刻胶材料层(未示出)。利用掩模320对光刻胶材料层(未示出)进行光刻工艺,以形成图案化光刻胶层(未示出)。之后,以图案化光刻胶层为掩模,对第二金属材料层进行蚀刻工艺,以形成第二金属层130。在本实施方式中,第二金属层130可利用掩模320以第三道光刻蚀刻工艺而形成。
第二金属层130包括多条数据线DL、多条触控信号线TP、多个源极S、多个漏极D以及多条第二扇出线F2。换句话说,可同时形成多条数据线DL、多条触控信号线TP、多个源极S、多个漏极D以及多条第二扇出线F2。多条数据线DL、多条触控信号线TP、多个源极S以及多个漏极D位于像素区100a,且多条第二扇出线F2位于扇出区100b。在本实施例中,栅极G、半导体层SE、源极S以及漏极D可构成主动元件T。在本实施例中,主动元件T为所属领域中技术人员所周知的任一种底部栅极型薄膜晶体管。然而,本实施例虽然是以底部栅极型薄膜晶体管为例,但本发明不限于此。在其他实施例中,主动元件T也可以是顶部栅极型薄膜晶体管或是其它合适类型的薄膜晶体管。源极S与对应的数据线SL电性连接。部分数据线DL分别与对应的第二扇出线F2连接,触控信号线TP与对应的第一扇出线F1电性连接。各个第二扇出线F2具有第二延伸部F21沿延伸方向L21延伸,延伸方向L21例如不平行于各扫描线SL以及各数据线DL的延伸方向。在本实施例中,第二延伸部F21完全重叠于第一延伸部F11上,但本发明不以此为限。在其他实施例中,第二延伸部F21可仅部分重叠于第一延伸部F11上。
请参照图1E,形成第一绝缘层140于第二金属层130上。第一绝缘层140可覆盖第二金属层130。第一绝缘层140的形成方法例如是利用物理气相沉积法或化学气相沉积法而形成。在本实施例中,第一绝缘层140的材料可为无机材料(例如:氧化硅、氮化硅、氮氧化硅、或上述至少二种材料的堆叠层)、有机材料(例如:聚酰亚胺是树脂、环氧是树脂或亚克力是树脂)或上述的组合,但本发明不以此为限。第一绝缘层140可为单层结构,但本发明并不限于此。在其他实施例中,第一绝缘层140也可为多层结构。
请参照图1F,按序形成第一导电材料层150a、第三金属材料层160a以及光刻胶材料层200a于第一绝缘层140上。此外,可选择性地形成平坦层PL于第一导电材料层150a以及第一绝缘层140之间,换句话说,第一导电材料层150a以及第一绝缘层140之间可不具有平坦层PL。平坦层PL的形成方法例如是利用物理气相沉积法或化学气相沉积法形成。在本实施例中,平坦层PL的材料可为无机材料(例如:氧化硅、氮化硅、氮氧化硅、或上述至少二种材料的堆叠层)、有机材料(例如:聚酰亚胺是树脂、环氧是树脂或亚克力是树脂)或上述的组合,但本发明不以此为限。平坦层PL可为单层结构,但本发明并不限于此。在其他实施例中,平坦层PL也可为多层结构。第一导电材料层150a的形成方法例如是利用溅镀法而形成,但本发明不以此为限。第一导电材料层150a的材料可为金属氧化物导电材料(例如:铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物)、其它合适的透明导电材料、或者是上述至少二者的堆叠层。在本实施例中,第一导电材料层150a举例为透明导电材料层。第三金属材料层160a的形成方法例如是利用物理气相沉积法或金属化学气相沉积法形成,但本发明不以此为限。在本实施例中,第三金属材料层160a举例为辅助导电材料层。在本实施例中,光刻胶材料层200a为正型光刻胶,但本发明不以此为限。在其他实施例中,光刻胶材料层200a可为负型光刻胶。
请同时参照图1F及图1G,使用掩模330图案化光刻胶材料层200a,以形成光刻胶层200。在本实施例中,掩模330为半调掩模(half-tone mask),掩模330具有多个第一区330a对应像素区100a及多个第二区330b对应扇出区100b,第一区330a的透光率举例是高于第二区330b的透光率。光刻胶层200包括多个第一区域202a对应像素区100a以及多个第二区域204a对应扇出区100b。第二区域204a的厚度大于第一区域202a的厚度,各个第一区域202a的厚度例如为各个第二区域204a的厚度的10%~50%。
请同时参照图1G及图1H,使用光刻胶层200图案化第三金属材料层160a以于扇出区100b中形成多个辅助导电层162以及于像素区100a中形成剩余的第三金属材料层160b。图案化第三金属材料层160a的方法例如是进行湿蚀刻工艺,且使用的蚀刻液例如为铝酸,但本发明不以此为限。
请同时参照图1H及图1I,使用光刻胶层200图案化第一导电材料层150a以形成多个透明导电层152于扇出区100b以及多个共同电极154于像素区100a。图案化第一导电材料层150a的方法例如是进行湿蚀刻工艺,且使用的蚀刻液例如为草酸,但本发明不以此为限。各个透明导电层152可分别与对应的辅助导电层162形成堆叠结构且彼此重叠。
请同时参照图1I及图1J,移除第一区域202a以实质上暴露出剩余的第三金属材料层160b。移除第一区域202a的方法例如是进行灰化工艺,但本发明不以此为限。在通过灰化工艺移除第一区域202a时也移除各个第二区域204a的一部分,而形成剩余的第二区域204b位于辅助导电层162上。剩余的第二区域204b的厚度例如是第二区域204a的厚度的20%~50%。
请同时参照图1J及图1K,移除位于像素区100a的剩余的第三金属材料层160b。移除位于像素区100a的剩余的第三金属材料层160b的方法例如是进行湿蚀刻工艺,且使用的蚀刻液例如为铝酸,但本发明不以此为限。在移除剩余的第三金属材料层160b之后,于像素区100a内暴露出共同电极154的顶表面。
请参照图1L、图4A以及图4B,移除剩余的第二区域204b。移除剩余的第二区域204b的方法例如是进行灰化工艺,但本发明不以此为限。移除剩余的第二区域204b之后,形成第一导电层150以及第三金属层160于第一绝缘层140上。第一导电层150例如由透明导电层152与共同电极154所构成,为透明导电层。第三金属层160例如包括多个辅助导电层162且位于第一导电层150上。从另一个方向来看,多个共同电极154位于像素区100a,且多个透明导电层152以及多个辅助导电层162位于扇出区100b。
由透明导电层152以及辅助导电层162组成的堆叠结构可构成多条第三扇出线F3。请参考图4B,各个第三扇出线F3具有第三延伸部F31沿延伸方向L31延伸,延伸方向L31例如不平行于各扫描线SL以及各数据线DL的延伸方向。在本实施例中,第三延伸部F31可完全重叠于第一延伸部F11以及第二延伸部F21上,但本发明不以此为限。在其他实施例中,第一延伸部F11、第二延伸部F21与第三延伸部F31中的至少两者是交错堆叠,举例来说,于基底100的法线方向上彼此相邻近且按序排列的第一延伸部F11、第二延伸部F21与第三延伸部F31中,第二延伸部F21的至少一部分是不重叠于第一延伸部F11及第三延伸部F31。此外,共同电极154例如可通过接触窗H11与触控信号线TP电性连接。
由此可知,在本实施方式中,第一导电层150以及第三金属层160通过利用同一个掩模330而同时形成。
基于上述,可通过使用半调掩模(掩模330)而同时形成第一导电层150以及第三金属层160,与现有的工艺相比可减少一道掩模的使用,借此可降低阵列基板的制造成本。
请参照图1M,形成第二绝缘层170于第一导电层150以及第三金属层160上。第二绝缘层170可同时覆盖第一导电层150以及第三金属层160。第二绝缘层170的形成方法例如是利用物理气相沉积法或化学气相沉积法而形成。在本实施例中,第二绝缘层170的材料可为无机材料(例如:氧化硅、氮化硅、氮氧化硅、或上述至少二种材料的堆叠层)、有机材料(例如:聚酰亚胺是树脂、环氧是树脂或亚克力是树脂)或上述的组合,但本发明不以此为限。第二绝缘层170可为单层结构,但本发明并不限于此。在其他实施例中,第二绝缘层170也可为多层结构。
请参照图1N,于第一绝缘层140、平坦层PL、第二绝缘层170中形成接触窗H12,以暴露出部分的漏极D。接触窗H12的形成方法例如是利用掩模340进行光刻蚀刻工艺而形成。首先,于第二绝缘层170上形成光刻胶材料层(未示出)。利用掩模340对光刻胶材料层(未示出)进行光刻工艺,以形成图案化光刻胶层(未示出)。之后,以图案化光刻胶层为掩模,对第一绝缘层140、平坦层PL以及第二绝缘层170进行蚀刻工艺,以形成接触窗H12。由此可知,在本实施方式中,接触窗H12是利用掩模340以第五道光刻蚀刻工艺形成。
请同时参照图1O、图5、图6A、图6B以及图6C,形成第二导电层180于第二绝缘层170上。第二导电层180的形成方法例如是利用物理气相沉积法或金属化学气相沉积法后再进行光刻蚀刻工艺而形成。举例来说,可先利用物理气相沉积法或金属化学气相沉积法于基底100上全面性地形成第二导电材料层(未示出)。接着,于第二导电材料层上形成光刻胶材料层(未示出)。利用掩模350对光刻胶材料层(未示出)进行光刻工艺,以形成图案化光刻胶层(未示出)。之后,以图案化光刻胶层为掩模,对第二导电材料层进行蚀刻工艺,以形成第二导电层180。由此可知,在本实施方式中,第二导电层180是利用掩模350以第六道光刻蚀刻工艺形成。
第二导电层180例如包括多个桥接电极182、多个像素电极184、多个连接电极186。多个像素电极184位于像素区100a,且多个桥接电极182位于扇出区100b。多个像素电极184通过接触窗H12与漏极D电性连接。在本实施例中,各个像素电极184具有多条狭缝184S与对应的共用电极154重叠。在本实施例中,多条狭缝184S例如呈矩形状,但本发明不限于此。
请继续参照图5,多个接触窗H2分别暴露出触控信号线TP以及第一扇出线F1且通过对应的连接电极186以将其电性连接,多个接触窗H3分别暴露部分的数据线DL以及第三扇出线F3且通过对应的连接电极186以将其电性连接,另一部分的数据线DL举例是直接连接对应的第二扇出线F2。
请同时参照图5以及图6A,在形成第二绝缘层170之后以及形成第二导电层180之前,于栅极绝缘层120、第一绝缘层140、平坦层PL及第二绝缘层170形成接触窗H41以暴露出部分的第一金属层110,亦即暴露出部分的第一接垫P1,且于第一绝缘层140、平坦层PL及第二绝缘层170形成接触窗H42以暴露出部分的第二金属层130,接触窗H41、H42的形成方法例如是利用光刻蚀刻工艺而形成,然本发明不局限于此。在其他实施例中,于形成第二金属层130前,可于栅极绝缘层120形成接触窗以暴露出部分的第一金属层110,于形成第二绝缘层170之后以及形成第二导电层180之前,再于第一绝缘层140、平坦层PL及第二绝缘层170形成接触窗与栅极绝缘层120的接触窗贯通以暴露出部分的第一金属层110,亦即暴露出部分的第一接垫P1。第一接垫P1上方的第二金属层130通过桥接电极182、接触窗H41、H42与第一接垫P1电性连接。
请同时参照图5以及图6B,在形成第二绝缘层170之后以及形成第二导电层180之前,于栅极绝缘层120、第一绝缘层140、平坦层PL及第二绝缘层170形成接触窗H51以暴露出部分的第一金属层110,亦即暴露出部分的第二接垫P2,且于第一绝缘层140、平坦层PL及第二绝缘层170形成接触窗H52以暴露出部分的第二金属层130,接触窗H51、H52的形成方法例如是利用光刻蚀刻工艺而形成,然本发明不局限于此。在其他实施例中,于形成第二金属层130前,可于栅极绝缘层120形成接触窗以暴露出部分的第一金属层110,于形成第二绝缘层170之后以及形成第二导电层180之前,再于第一绝缘层140、平坦层PL及第二绝缘层170形成接触窗与栅极绝缘层120的接触窗贯通以暴露出部分的第一金属层110,亦即暴露出部分的第二接垫P2。第二扇出线F2通过桥接电极182、接触窗H51、H52与第二接垫P2电性连接。
请同时参照图5以及图6C,在形成第二绝缘层170之后以及形成第二导电层180之前,于栅极绝缘层120、第一绝缘层140、平坦层PL及第二绝缘层170形成接触窗H61以暴露出部分的第一金属层110,亦即暴露出部分的第三接垫P3,且于第二绝缘层170形成接触窗H62以暴露出部分的第三扇出线F3,亦即暴露出部分的辅助导电层162,接触窗H61、H62的形成方法例如是利用光刻蚀刻工艺而形成,然本发明不局限于此。在其他实施例中,于形成第二金属层130前,可于栅极绝缘层120形成接触窗以暴露出部分的第一金属层110,于形成第二绝缘层170之后以及形成第二导电层180之前,再于第一绝缘层140、平坦层PL及第二绝缘层170形成接触窗与栅极绝缘层120的接触窗贯通以暴露出部分的第一金属层110,亦即暴露出部分的第三接垫P3。第三扇出线F3通过桥接电极182、接触窗H61、H62与第三接垫P3电性连接。
综上所述,本发明的至少一实施例的阵列基板的制造方法通过使用同一掩模于扇出区中形成第一导电层以及第三金属层,因此由第一导电层以及第三金属层组成的第三扇出线可与第一扇出线以及第二扇出线一起构成三层堆叠的金属层(即,由第一延伸部、第二延伸部以及第三延伸部组成的堆叠结构),除了可使扇出区的面积缩减而间接使像素区的面积提升外,也可减少掩模的使用,借此可降低阵列基板的制造成本。
虽然本发明已以实施例公开如上,然其并非用以限定本发明,任何所属技术领域中技术人员,在不脱离本发明的构思和范围内,当可作些许的变动与润饰,故本发明的保护范围当视权利要求所界定者为准。
Claims (13)
1.一种阵列基板的制造方法,包括:
形成多条扫描线于一基底上,该基底具有一像素区以及一扇出区;
形成多条数据线;
形成多个晶体管,其中所述晶体管各自与对应的扫描线以及对应的数据线电性连接;
形成多个共同电极;
形成多个像素电极,其中所述像素电极各自与对应的晶体管电性连接;
形成多条第一扇出线于该扇出区内;
形成多条第二扇出线于该扇出区内;以及
形成多条第三扇出线于该扇出区内,其中各该第三扇出线包括:
一透明导电层;以及
一辅助导电层,位于该透明导电层上且与该透明导电层接触;
其中所述第三扇出线与所述共同电极是通过相同的掩模形成,
其中形成所述第三扇出线与所述共同电极的步骤包括:
按序形成一透明导电材料层、一辅助导电材料层以及一光刻胶材料层;
使用一掩模图案化该光刻胶材料层,以形成一光刻胶层,其中该光刻胶层包含:
多个第一区域位于该像素区内;以及
多个第二区域位于该扇出区内,各该第二区域的厚度小于各该第一区域的厚度;
使用该光刻胶层图案化该辅助导电材料层以形成所述辅助导电层于该扇出区以及一剩余辅助导电材料层于该像素区,其中各该辅助导电层的一部分是同时重叠于对应的该第一扇出线以及对应的该第二扇出线;
使用该光刻胶层图案化该透明导电材料层以形成该透明导电层于该扇出区以及所述共同电极于该像素区;
移除该第一区域;
移除该剩余辅助导电材料层;以及
移除该第二区域。
2.如权利要求1所述的阵列基板的制造方法,其中各该晶体管包括一栅极、一半导体层、一源极以及一漏极,其中所述栅极、所述扫描线以及所述第一扇出线是由相同金属层所形成。
3.如权利要求2所述的阵列基板的制造方法,其中所述源极、所述漏极、所述数据线以及所述第二扇出线是由相同金属层所形成。
4.如权利要求3所述的阵列基板的制造方法,还包括形成多条触控信号线分别电性连接于对应的共同电极,其中所述触控信号线、所述源极、所述漏极、所述数据线以及所述第二扇出线是由相同金属层所形成。
5.如权利要求1所述的阵列基板的制造方法,其中所述共同电极以及该透明导电层是由相同层导电层所形成。
6.如权利要求1所述的阵列基板的制造方法,还包括形成多个第一接垫、多个第二接垫以及多个第三接垫于该扇出区中,其中所述第一接垫各自与对应的第一扇出线电性连接,所述第二接垫各自与对应的第二扇出线电性连接,且所述第三接垫各自与对应的第三扇出线电性连接。
7.如权利要求1所述的阵列基板的制造方法,其中各该第一扇出线至第三扇出线具有一延伸部,各该延伸部的延伸方向不平行于各该数据线的延伸方向,对于邻近且按序排列的该第一扇出线、该第二扇出线以及该第三扇出线,所述延伸部的一部分是完全重叠。
8.如权利要求1所述的阵列基板的制造方法,其中各该第一扇出线至第三扇出线具有一延伸部,各该延伸部的延伸方向不平行于各该数据线的延伸方向,对于邻近且按序排列的该第一扇出线、该第二扇出线以及该第三扇出线,所述延伸部是交错重叠。
9.一种阵列基板的制造方法,包括:
形成一第一金属层于一基底上,该基底包括一像素区及一扇出区,该第一金属层包括多个栅极与多条扫描线位于该像素区以及多条第一扇出线位于该扇出区;
形成一栅极绝缘层于该第一金属层上;
形成一第二金属层于该栅极绝缘层上,该第二金属层包括多个源极、多个漏极与多条数据线位于该像素区以及多条第二扇出线位于该扇出区;
形成一第一绝缘层于该第二金属层上;以及
通过一掩模形成一第一导电层以及一第三金属层于该第一绝缘层上,其中该第一导电层包括多个透明导电层位于该扇出区以及多个共同电极位于该像素区,该第三金属层包括多个辅助导电层位于该扇出区,所述辅助导电层分别位于所述透明导电层上以构成多条第三扇出线于该扇出区,
其中形成该第一导电层以及该第三金属层的步骤包括:
按序形成一透明导电材料层、一辅助导电材料层以及一光刻胶材料层于该第一绝缘层上;
使用一掩模图案化该光刻胶材料层,以形成一光刻胶层,其中该光刻胶层包含:
多个第一区域位于该像素区内;以及
多个第二区域位于该扇出区内,各该第二区域的厚度大于各该第一区域的厚度;
使用该光刻胶层图案化该辅助导电材料层以形成所述辅助导电层于该扇出区以及一剩余辅助导电材料层于该像素区,其中各该辅助导电层的一部分是同时重叠于对应的该第一扇出线以及对应的该第二扇出线;
使用该光刻胶层图案化该透明导电材料层以形成该透明导电层于该扇出区以及所述共同电极于该像素区;
移除该第一区域;
移除该剩余辅助导电材料层;以及
移除该第二区域。
10.如权利要求9所述的阵列基板的制造方法,其中于形成该第一导电层以及该第三金属层的步骤后,还包括:
形成一第二绝缘层于该第一导电层以及该第三金属层上;以及
形成一第二导电层于该第二绝缘层上,其中该第二导电层包括:
多个像素电极位于该像素区且分别电性连接于所述漏极;以及
多个桥接电极位于该扇出区。
11.如权利要求9所述的阵列基板的制造方法,其中于形成该第二金属层于该栅极绝缘层上的步骤前,还包括形成多个半导体层位于该栅极绝缘层上且分别与所述栅极相对设置,该方法还包括形成多个第一接垫、多个第二接垫以及多个第三接垫于该扇出区中,其中所述第一接垫各自与对应的第一扇出线电性连接,所述第二接垫各自与对应的第二扇出线电性连接,且所述第三接垫各自与对应的第三扇出线电性连接。
12.如权利要求11所述的阵列基板的制造方法,其中各该第一扇出线至第三扇出线具有一延伸部,各该延伸部的延伸方向不平行于各该数据线的延伸方向,对于邻近且按序排列的该第一扇出线、该第二扇出线以及该第三扇出线,所述延伸部是完全重叠。
13.如权利要求11所述的阵列基板的制造方法,其中各该第一扇出线至第三扇出线具有一延伸部,各该延伸部的延伸方向不平行于各该数据线的延伸方向,对于邻近且按序排列的该第一扇出线、该第二扇出线以及该第三扇出线,所述延伸部是交错重叠。
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TWI729328B (zh) * | 2018-12-04 | 2021-06-01 | 友達光電股份有限公司 | 陣列基板及其製造方法 |
TWI697141B (zh) * | 2018-12-11 | 2020-06-21 | 友達光電股份有限公司 | 元件基板 |
KR20200113065A (ko) * | 2019-03-20 | 2020-10-06 | 삼성디스플레이 주식회사 | 표시 장치 |
CN109976056B (zh) * | 2019-04-08 | 2023-04-14 | 京东方科技集团股份有限公司 | 阵列基板、其制作方法、显示面板及显示装置 |
JP7367006B2 (ja) * | 2019-04-12 | 2023-10-23 | ラピスセミコンダクタ株式会社 | 表示ドライバ及び表示装置 |
CN110600520A (zh) * | 2019-09-19 | 2019-12-20 | 昆山工研院新型平板显示技术中心有限公司 | 一种显示面板及显示装置 |
TWI709126B (zh) * | 2019-11-15 | 2020-11-01 | 友達光電股份有限公司 | 顯示裝置 |
CN113363281A (zh) * | 2020-03-05 | 2021-09-07 | 群创光电股份有限公司 | 显示装置 |
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