201024874201024874
1 W36^M"A 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種液晶顯示模組，且特別是有關於 一種液晶顯示模組之畫素陣列基板及其修補方法。 【先前技術】 科技發展日新月異’平面顯示器已被廣泛地被運用於 筆記型電腦、數位相機、數位攝錄影機、個人數位助理及 行動電話上。以薄膜電晶體液晶顯示器而言，驅動晶片與 晝素陣列基板的接合技術以玻璃黏晶技術(Chip on glass， COG)為未來主要趨勢。玻璃黏晶技術乃是將驅動晶片直接 架置於玻璃基板上’可以提高包裝密度及減輕重量使得面 板更為輕薄、減少使用材料、降低生產成本並且提高面板 解析度。 請參照第1圖’其繪示依照採用玻璃黏晶技術之傳統 平面顯示器之畫素陣列基板的俯視示意圖（導線或線路之 數量僅為示意，非真正代表實物的線路條數）。電路板1〇 接收或產生顯示晝面所需的資料訊號以及電源之後，透過 軟性電路板20傳遞至畫素陣列基板3〇。 畫素陣列基板30分為顯示區40以及非顯示區（顯示 區40以外的區域）。在非顯示區内，資料驅動晶片34以及 掃瞄驅動晶片36透過金屬、高分子樹脂或導電性黏著物 直接地連接於玻璃基板上，也就是所謂的坡璃黏晶技術 (COG)。另一方面，複數條平行的掃瞄線42及複數條平行 201024874 的資料線44交錯形成於顯示區40中，二相鄰資料線44 與二相鄰掃瞄線42係定義出一畫素。 在控制訊號及電源傳遞至畫素陣列基板30之後，位 於基板上非顯不區的走線32將訊號以及電源分送至多個 貝料驅動晶片34以及掃瞄驅動晶片36。原始的控制訊號 透過各晶片内邏輯電路運算之後產生晝素資料，晝素資料 經由扇出導線(fan_out)38分別傳遞至晝素陣列中的資料線 44或掃瞄線42，藉此導通或關斷各晝素、並且給予各畫 • 素資料訊號。 一般來說’在平面顯示器安裝驅動晶片及軟性電路板 之别’會先以測試探針卡(pr〇becard)對畫素陣列基板3〇 進行全接觸式測試(full c〇ntacttest)，檢驗現階段半成品的 電性品質’通常探針卡的探針要與扇形導線38的前端接 觸。由於扇出導線38前端於後續階段是直接與驅動晶片 的接腳相連，其間距很小只有2〇〜3〇//m，目前的探針卡 不足支援如COG基板這一類積集度如此高的待測導線。 ❹因此，需要將扇出導線38拉線到基板其他部分，並另外 形成間距較寬的測試墊，才能夠進行探針卡全接觸式測 試。然而，資料驅動晶片34與走線32橫亙在扇出導線38 與基板10邊緣之間，由扇出導線38拉線出來勢必要跨過 走線32並且穿插於資料驅動晶片34各接腳連接走線32 的接腳墊（圖未繪示）之間，其製程不僅複雜還容易衍生出 走線與測試線短路等問題。 基於上述理由，業界目前的解決方法就是由資料線末 7 2010248741 W36^M"A IX. Description of the Invention: [Technical Field] The present invention relates to a liquid crystal display module, and more particularly to a pixel array substrate of a liquid crystal display module and a repairing method thereof. [Prior Art] The development of technology is changing rapidly. Flat-panel displays have been widely used in notebook computers, digital cameras, digital video cameras, personal digital assistants, and mobile phones. In the case of a thin film transistor liquid crystal display, the bonding technique of driving a wafer to a halogen matrix substrate is a major trend in the future with chip on glass (COG). The glass-bonding technology is to directly mount the driver wafer on the glass substrate, which can increase the packing density and reduce the weight, make the panel thinner, reduce the use of materials, reduce the production cost and improve the panel resolution. Referring to FIG. 1 , a schematic plan view of a pixel array substrate according to a conventional flat panel display using a glass die bonding technique is shown (the number of wires or lines is merely an illustration, and the number of lines that do not really represent a physical object). The circuit board 1 接收 receives or generates the data signal and the power required to display the surface, and then transmits it to the pixel array substrate 3 through the flexible circuit board 20. The pixel array substrate 30 is divided into a display area 40 and a non-display area (area other than the display area 40). In the non-display area, the data driving chip 34 and the scanning driving chip 36 are directly connected to the glass substrate through a metal, a polymer resin or a conductive adhesive, which is called a so-called COG. On the other hand, a plurality of parallel scan lines 42 and a plurality of parallel data lines 44 of 201024874 are alternately formed in the display area 40, and two adjacent data lines 44 and two adjacent scan lines 42 define a pixel. After the control signal and power are transferred to the pixel array substrate 30, the traces 32 on the non-display area on the substrate distribute the signals and power to the plurality of feed drive wafers 34 and the scan drive wafers 36. The original control signal is generated by the logic circuit in each chip to generate the halogen data, and the halogen data is respectively transmitted to the data line 44 or the scan line 42 in the pixel array via the fan-out wire (fan_out) 38, thereby turning on or off. Break each element and give each picture information. Generally speaking, 'installing the driver chip and the flexible circuit board in the flat panel display' will first perform full contact test (full c〇ntacttest) on the pixel array substrate 3 with the test probe card (pr〇becard). The electrical quality of the stage semi-finished product 'typically the probe of the probe card is in contact with the front end of the sector wire 38. Since the front end of the fan-out wire 38 is directly connected to the pin of the driving chip at a subsequent stage, the pitch is as small as 2 〇 3 〇 / / m, and the current probe card is insufficient to support such a high degree of accumulation as the COG substrate. The wire to be tested. Therefore, it is necessary to pull the fan-out wire 38 to other parts of the substrate and additionally form a test pad having a wide pitch to enable the probe card full-contact test. However, the data driving chip 34 and the trace 32 are traversed between the fan-out wire 38 and the edge of the substrate 10. The wire is pulled out by the fan-out wire 38. It is necessary to cross the wire 32 and be inserted through the pins of the data driving chip 34. Between the pads 32 of the line 32 (not shown), the process is not only complicated but also easy to derive problems such as short circuit between the trace and the test line. For the above reasons, the current solution in the industry is from the end of the data line 7 201024874
1W3625PA 端44b拉測試線48出來，並在鄰近區域形成間距較寬的 測試墊50 ’進行接觸測試。測試墊50設置於切割線D之 外’一旦玻璃基板切割出單一基板之後，測試墊50會被 切除且不會出現在晝素陣列基板上。測試探針卡之每一探 針會與每一個測試墊50電性接觸，測試信號經由測試墊 50與測試線48 ’從資料線末端44b輸入晝素陣列，之後， 偵測畫素是否可以根據測試信號導通或關斷，便可以檢測 出畫素陣列是否有缺陷。然而，只有位於測試塾5〇到資 料線前端44a之間的資料線缺陷會被檢測出來，如果資料 線前端44a到資料驅動晶片34之間的扇出導線％因為製 程不良或者其他因素發生斷路等缺陷，便無法藉由上述測 試方式檢測出來，這一類COG的產品基板也就無法在安 裝驅動晶片測試前的晝素陣列製程完成階段時就有效地 將扇出導線38的缺陷檢測出來，倘若發生製程中這一類 扇出導線的缺陷，則須等到安裝驅動晶片進行測試後才能 發現，其將造成較大的損失或較高的重工(re_w〇rk)成本。 【發明内容】 本發明係有關於一種液晶顯示模組之晝素陣列基板 及其修補方法，其連接驅動晶片與畫素陣列的扇出導線係 由二層金屬層所構成，可以大幅度地降低導線產生缺陷的 機率。 根據本發明之第一方面，提出一種畫素陣列基板包括 基板、複數個畫素以及扇出導線。基板有顯示區以及晶片 待置區。複數個畫素係以矩陣方式排列於顯示區内。扇出 導線（fanout)，連接晶片待置區與顯示區，用以電性連接 驅動晶片以及晝素。扇出導線包括第一金屬層、絕緣層以 及第二金屬層。第一金屬層係形成於基板上，絕緣層係形 成於第一金屬層上，第二金屬層係形成於絕緣層上。 根據本發明之第二方面，提出一種液晶顯示模組，包 括第一基板、驅動晶片、複數個晝素、第二基板以及液晶 層。第一基板具有顯不區以及晶片待置區，驅動晶片係以 φ 玻璃黏晶製程設置於晶片待置區，複數個晝素，以矩陣方 式排列於顯示區内，扇出導線(fan out)連接晶片待置區與 顯示區，用以電性連接驅動晶片及些畫素，扇出導線包括 第一金屬層、絕緣層以及第二金屬層。第一金屬層係形成 於基板上，絕緣層係形成於第一金屬層上，第二金屬層係 形成於絕緣層上。第二基板係與第一基板平行設置，液晶 層係密封於第一基板以及第二基板之間。 根據本發明之第三方面，提出一種晝素陣列基板的修 ® 補方法包括（a)提供畫素陣列基板，具有顯示區以及晶片待 置區，晝素陣列基板包括扇出導線(fan out)，連接晶片待 置區與顯示區，扇出導線包括第一金屬層、絕緣層以及第 二金屬層，第一金屬層係形成於基板上，絕緣層係形成於 第一金屬層上，第二金屬層，係形成於絕緣層上，並重疊 於第一金屬層之上，其中第一金屬層與第二金屬層其中至 少一者具有斷裂處；以及（b)施加雷射光束於斷裂處以外位 置，用以熔接第一金屬層以及第二金屬層。 9 201024874The 1W3625PA terminal 44b pulls the test line 48 out and forms a wide spaced test pad 50' in the adjacent area for contact testing. The test pad 50 is disposed outside the cutting line D. Once the glass substrate is cut out of the single substrate, the test pad 50 is cut off and does not appear on the pixel array substrate. Each probe of the test probe card is electrically contacted with each test pad 50, and the test signal is input to the pixel array from the data line end 44b via the test pad 50 and the test line 48'. Thereafter, whether the pixel is detected can be based on When the test signal is turned on or off, it can detect whether the pixel array is defective. However, only the data line defects located between the test 塾5〇 and the data line front end 44a will be detected if the fan-out wire between the data line front end 44a and the data drive chip 34 is broken due to poor process or other factors. Defects cannot be detected by the above test method. The product substrate of this type of COG cannot effectively detect the defects of the fan-out wire 38 when the phase of the halogen array process is completed before the test of the driver wafer is mounted. The defects of this type of fan-out wire in the process must be discovered after the driver chip is mounted for testing, which will result in a large loss or a high rework cost. SUMMARY OF THE INVENTION The present invention relates to a liquid crystal display module, a pixel array substrate, and a repairing method thereof. The fan-out wire connecting the driving chip and the pixel array is composed of two metal layers, which can be greatly reduced. The probability of a wire producing a defect. According to a first aspect of the present invention, a pixel array substrate is provided comprising a substrate, a plurality of pixels, and a fan-out wire. The substrate has a display area and a wafer waiting area. A plurality of pixels are arranged in a matrix in the display area. A fanout is connected to the wafer holding area and the display area for electrically connecting the driving chip and the halogen. The fan-out wire includes a first metal layer, an insulating layer, and a second metal layer. The first metal layer is formed on the substrate, the insulating layer is formed on the first metal layer, and the second metal layer is formed on the insulating layer. According to a second aspect of the present invention, a liquid crystal display module is provided, comprising a first substrate, a driving wafer, a plurality of halogens, a second substrate, and a liquid crystal layer. The first substrate has a display area and a wafer waiting area, and the driving chip is disposed in the wafer waiting area by a φ glass bonding process, and the plurality of pixels are arranged in a matrix manner in the display area, and the fan out The wafer holding area and the display area are connected to electrically connect the driving chip and the pixels, and the fan-out wire comprises a first metal layer, an insulating layer and a second metal layer. The first metal layer is formed on the substrate, the insulating layer is formed on the first metal layer, and the second metal layer is formed on the insulating layer. The second substrate is disposed in parallel with the first substrate, and the liquid crystal layer is sealed between the first substrate and the second substrate. According to a third aspect of the present invention, a method for repairing a halogen matrix substrate includes: (a) providing a pixel array substrate having a display area and a wafer waiting area, the halogen array substrate including a fan out wire And connecting the wafer holding area and the display area, the fan-out wire comprises a first metal layer, an insulating layer and a second metal layer, the first metal layer is formed on the substrate, the insulating layer is formed on the first metal layer, and the second a metal layer formed on the insulating layer and overlying the first metal layer, wherein at least one of the first metal layer and the second metal layer has a break; and (b) applying a laser beam outside the break a location for fusing the first metal layer and the second metal layer. 9 201024874
I W3625FA 為讓本發明之上述内容能更明顯易懂，下文特舉一較 佳實施例，並配合所附圖式，作詳細說明如下： 【實施方式】 本發明之發明目的在提供一種應用於液晶顯示模組 之畫素陣列基板’其用以連接驅動晶片與畫素陣列的扇出 導線係由二層金屬層所形成，可以大幅度地降低扇出導線 產生缺陷的機率。以下係舉出一較佳實施例並配合圖示做 詳細說明，然此些文字及圖示僅為本發明之發明精神下的 ❹ 一種實施方式，並不會對本發明之欲保護範圍進行限縮。 請參照第2圖，其繪示依照本發明一較佳實施例的一 種液晶顯不模組的側視不意圖。本較佳實施例之顯示模組 100包括第一基板102、第二基板104以及液晶層106。第 一基板102與第二基板104平行設置，液晶層1〇6填充並 密封於第一基板102與第二基板104之間。第一基板1〇2 例如是晝素陣列基板，具有顯示區A以及晶片待置區C。 驅動晶片108係以玻璃黏晶製程（Chip On Glass, COG)設 ❹ 置在晶片待置區C内，複數個畫素110以矩陣方式排列於 顯示區A内（如第3圖所示）。 第3圖繪示依照第2圖之第一基板的俯視示意圖。在 顯示區A之外，第一基板102上更包括複數個驅動晶片 108以及複數條走線134。驅動晶片108、10Sa與108b係 設置於晶片待置區C(請參照第2圖），走線134介於晶片 待置區C與基板102邊緣之間，分別連接驅動晶片108、 10 201024874 χ ττ my λ. Λ λ 108a與108b至軟性電路板130，用以將電源及資料訊號 經由軟性電路板130分送至多個驅動晶片1〇8、108a與 108b 中。 在顯示區A内，第一基板102上之晝素陣列係由複 數條平行的掃瞄線、複數條平行的資料線以及薄膜電晶體 所組成。第一掃瞄線l〇la以及第二掃描線101b相互平行 設置於顯示區A，第一資料線l〇3a以及第二資料線103b 也相互平行設置於顯示區A，第一資料線i〇3a以及第二資 ❹ 料線103b與第一掃瞄線101a以及第二掃瞄線101b垂直 交錯地定義出一畫素11〇。複數個薄膜電晶體U1係分別 形成於複數個畫素11〇中，薄膜電晶體m與第一掃瞄線 101a以及第一資料線1〇3a電性連接，以接收由驅動晶片 傳出的資料訊號。 扇出導線(fan 〇ut)120連接晶片待置區C(第2圖）與顯 示區A ’用以電性連接驅動晶片ι〇8及晝素11()。扇出導 線120包括第一金屬層122、絕緣層124以及第二金屬層 〇 126 ;第一金屬層122係形成於第一基板1〇2上，絕緣層 124係形成於第一金屬層ι22上，第二金屬層ι26係形成 於絕緣層124上。扇出導線12〇係由二層金屬層所形成， 必須在二層金屬層都發生斷路的情況下才會造成導線斷 路’可以大幅度地降低產生缺陷的機率，此即為一保險機 制。因此本實施例特別適用於無法檢測到扇出導線是否產 生缺陷的末端檢測法’即便檢測本實施例之畫素陣列基板 時是由資料線末端拉出測試墊，但由於扇出導線發生缺陷 11 201024874 ， 的機率變得很低，使得在安裝驅動晶片108進行測試以前 的階段無法檢測出扇出導線缺陷之問題不再造成重大損 失。再者，在扇出導線寬度不變的情況下，其線路變為二 倍寬，阻抗可以降為原來的二分之一。 第4A圖繪示依照本發明之較佳實施例之畫素陣列基 板的部分俯視示意圖，第4B圖繪示第4A圖中沿4B-4B’ 線所示之剖面圖。扇出導線120之第二金屬層126較佳的 是隔著絕緣層124重疊於扇出導線120之第一金屬層122 之上。第二金屬層126與第一金屬層122可以是部分地疊 參 合，也可以是完全地重合。看似二條分開的佈線，實際上 都是電連接同一個驅動晶片的腳位以及同一列的畫素。請 參照第2圖，絕緣層124具有接觸孔（如第2圖之127，位 於另一接觸孔128的正下方，目前被第二金屬層126填 滿，以及如第2圖之129)，使得第二金屬層126透過接觸 孔127及129連接第一金屬層122。驅動晶片108之腳位 再透過另一接觸孔128與第二金屬層126電性連接。因 此，看似二條分開的佈線，實際上都是電連接同一個驅動 ❹ 晶片的腳位以及同一列的晝素，以提供扇出導線120 —個 兩層通路的結構。 扇出導線120的第一金屬層與第二金屬層也可以不 重疊。第5A圖繪示依照本發明另一較佳實施例之晝素陣 列基板的部分俯視示意圖，第5B圖繪示第5A圖中沿 5B-5B’線所示之剖面圖。扇出導線120a之第二金屬層126a 係鄰近扇出導線120a之第一金屬層122a。雖然二者並不 12 201024874 重疊，第一金屬層122a與第二金屬層126a係可以在各自 的兩末端透過類似接觸孔127與129的接觸孔設計連接同 一個驅動晶片的腳位以及同一列的晝素。 請同時參照第2及3圖，薄膜電晶體111包括閘極 112、閘極絕緣層114、通道層116、源極/汲極118a/118b。 閘極112係形成於第一基板102上，閘極絕緣層114係形 成於閘極112上，通道層116係形成於閘極絕緣層114上， 源極/汲極118a/l 18b係相互絕緣地形成於通道層116以及 0 閘極絕緣層114上。較佳的是，扇出導線120係連接至第 一資料線l〇3a，用以傳遞一信號至薄膜電晶體ill。 扇出導線的製程較佳地可以與畫素陣列的製程整合 在一起。較佳的是’閘極112與第一金屬層122係由同一 道光罩以微影蝕刻製程（圖案化製程）所形成，閛極112之 組成係與第一金屬層122之組成相同。較佳的是，源極/ 沒極118a/ll8b與第二金屬層126係由同一道圖案化製程 所形成，源極/汲極118a/118b之組成係與第二金屬層126 ❹ 之組成相同。 扇出導線之第一金屬層與第二金屬層較佳的是部分 重疊’當導線發生斷路的時候可以根據下列方式進行修 補。首先’提供上述之第一基板，扇出導線(fan 〇ut)之第 二金屬層126係重疊於第一金屬層122之上，其中第一金 屬層122與第二金屬層126經檢測後其中至少一者具有一 斷裂處。當檢視出斷裂位置後，施加雷射光束（圖未繪示） 於斷裂處與接觸孔127之間以及與接觸孔129之間的扇出 13 201024874I W3625FA In order to make the above content of the present invention more comprehensible, a preferred embodiment will be described below in detail with reference to the accompanying drawings, in which: FIG. The pixel array substrate of the liquid crystal display module has a fan-out wire for connecting the driving chip and the pixel array, and is formed by two metal layers, which can greatly reduce the probability of the fan-out wire generating defects. The following is a detailed description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. . Please refer to FIG. 2, which illustrates a side view of a liquid crystal display module according to a preferred embodiment of the present invention. The display module 100 of the preferred embodiment includes a first substrate 102, a second substrate 104, and a liquid crystal layer 106. The first substrate 102 is disposed in parallel with the second substrate 104, and the liquid crystal layer 1 is filled and sealed between the first substrate 102 and the second substrate 104. The first substrate 1〇2 is, for example, a halogen array substrate having a display area A and a wafer waiting area C. The driving wafer 108 is disposed in the wafer waiting area C by a chip on glass (COG), and a plurality of pixels 110 are arranged in a matrix in the display area A (as shown in FIG. 3). FIG. 3 is a schematic plan view of the first substrate according to FIG. 2 . In addition to the display area A, the first substrate 102 further includes a plurality of driving chips 108 and a plurality of wiring lines 134. The driving wafers 108, 10Sa and 108b are disposed in the wafer holding area C (refer to FIG. 2), and the wiring 134 is interposed between the wafer holding area C and the edge of the substrate 102, and is respectively connected to the driving wafer 108, 10 201024874 χ ττ My λ. λ λ 108a and 108b to the flexible circuit board 130 for distributing power and data signals to the plurality of driving chips 1 〇 8, 108a and 108b via the flexible circuit board 130. In the display area A, the pixel array on the first substrate 102 is composed of a plurality of parallel scanning lines, a plurality of parallel data lines, and a thin film transistor. The first scan line 10a and the second scan line 101b are disposed in parallel with each other in the display area A. The first data line 103a and the second data line 103b are also disposed in parallel with each other in the display area A, and the first data line i〇 The 3a and the second asset line 103b define a pixel 11 垂直 vertically interlaced with the first scan line 101a and the second scan line 101b. A plurality of thin film transistors U1 are respectively formed in a plurality of pixels 11 , and the thin film transistor m is electrically connected to the first scan line 101 a and the first data line 1 〇 3 a to receive the data transmitted from the driving chip. Signal. A fan-out wire 120 connects the wafer holding area C (Fig. 2) and the display area A' to electrically connect the driving chip 〇8 and the halogen 11 (). The fan-out wire 120 includes a first metal layer 122, an insulating layer 124, and a second metal layer 126; the first metal layer 122 is formed on the first substrate 1〇2, and the insulating layer 124 is formed on the first metal layer ι22. The second metal layer ι26 is formed on the insulating layer 124. The fan-out wire 12 is formed by two metal layers, and the wire breakage must be caused in the case where the two metal layers are broken, which can greatly reduce the probability of occurrence of defects, which is an insurance mechanism. Therefore, the present embodiment is particularly suitable for the end detection method in which it is impossible to detect whether or not the fan-out wire is defective. Even when the pixel array substrate of the present embodiment is detected, the test pad is pulled out from the end of the data line, but the defect occurs due to the fan-out wire. The probability of 201024874, becomes very low, so that the problem of failing to detect fan-out wire defects before the installation of the driver wafer 108 for testing no longer causes significant losses. Furthermore, in the case where the width of the fan-out wire is constant, the line becomes twice as wide and the impedance can be reduced to one-half. 4A is a partial top plan view of a pixel array substrate in accordance with a preferred embodiment of the present invention, and FIG. 4B is a cross-sectional view taken along line 4B-4B' of FIG. 4A. The second metal layer 126 of the fan-out wire 120 is preferably overlying the first metal layer 122 of the fan-out wire 120 via the insulating layer 124. The second metal layer 126 and the first metal layer 122 may be partially overlapped or may be completely coincident. It seems that the two separate wires are actually connected to the pins of the same drive chip and the pixels in the same column. Referring to FIG. 2, the insulating layer 124 has contact holes (such as 127 of FIG. 2, directly under the other contact hole 128, which is currently filled by the second metal layer 126, and 129 as shown in FIG. 2). The second metal layer 126 is connected to the first metal layer 122 through the contact holes 127 and 129. The pin of the driving chip 108 is electrically connected to the second metal layer 126 through another contact hole 128. Therefore, it appears that the two separate wirings are actually electrically connected to the same driving ❹ wafer pin and the same column of pixels to provide a structure of the fan-out wire 120 as a two-layer path. The first metal layer and the second metal layer of the fan-out wire 120 may not overlap. 5A is a partial top plan view of a pixel array substrate according to another preferred embodiment of the present invention, and FIG. 5B is a cross-sectional view taken along line 5B-5B' of FIG. 5A. The second metal layer 126a of the fan-out wire 120a is adjacent to the first metal layer 122a of the fan-out wire 120a. Although the two do not overlap 12 201024874, the first metal layer 122a and the second metal layer 126a may be designed to connect the pins of the same driving chip and the same column through the contact holes of the contact holes 127 and 129 at the respective ends thereof. Russell. Referring also to Figures 2 and 3, the thin film transistor 111 includes a gate 112, a gate insulating layer 114, a channel layer 116, and source/drain electrodes 118a/118b. The gate 112 is formed on the first substrate 102, the gate insulating layer 114 is formed on the gate 112, the channel layer 116 is formed on the gate insulating layer 114, and the source/drain electrodes 118a/l 18b are insulated from each other. The ground is formed on the channel layer 116 and the 0 gate insulating layer 114. Preferably, the fan-out wire 120 is connected to the first data line 103a for transmitting a signal to the thin film transistor ill. The process of fanning out the wires is preferably integrated with the process of the pixel array. Preferably, the gate 112 and the first metal layer 122 are formed by a photolithography process (patterning process) by the same mask, and the drain 112 has the same composition as the first metal layer 122. Preferably, the source/drain electrodes 118a/ll8b and the second metal layer 126 are formed by the same patterning process, and the source/drain electrodes 118a/118b have the same composition as the second metal layer 126 . The first metal layer of the fan-out wire and the second metal layer preferably overlap partially. When the wire is broken, it can be repaired in the following manner. Firstly, the first metal substrate 126 of the first substrate is provided, and the second metal layer 126 of the fan-out wire is overlaid on the first metal layer 122, wherein the first metal layer 122 and the second metal layer 126 are detected. At least one has a break. After the fracture position is inspected, a laser beam (not shown) is applied between the fracture and the contact hole 127 and between the contact hole 129. 13 201024874
lV/3t2^A 導線上較靠近斷裂處的一位置（即：總共有兩個位置點 用以溶接重疊的第-金屬層以及第：金屬層以提供跨層 接觸通路。藉此一修補動作，即使在安裝驅動晶片測試而 進一步發現扇出導線缺陷或者在任何時段發現扇出導 缺陷後，仍可恢復提供-在斷線處前後方 複 低阻抗扇緣㈣構。 雙層佈線的 本發明上述實施例所揭露之液晶顯示模組之 補方法，其扇出導線係由二層不同的金屬層 φ 二大幅度地降低限抗。因此，本實 =2 否產生缺陷的末端_法，即心 測試墊’其產品檢測結果也可以信賴。再者 t金屬層重疊，更可以利用雷射修補提供-低=導ΐ 良率的扇出導線。 k ^ Θ JL拍所述’雖然本發明已啸佳實施_露如上，然 ^非用以限定本發明。本發明所屬技術領域中且 知識者’在;F脫離本發明之精神和朗内當可作各 潤飾。因此’本發明之保護職當視 利範圍所界定者為準。 Ύ月导 【圖式簡單說明】 ρ第1圖緣示依照採用玻璃點晶技術之傳統平 器之畫素陣列基板的俯視示意圖。 *、 第2圖繪示依照本發明—較佳實施例的 種液晶顯 14 201024874 1 yy γύ 示模組的側視示意圖。 第3圖繪示依照第2圖之第一基板的俯視示意圖。 第4A圖繪示依照本發明之較佳實施例之晝素陣列基 板的部分俯視示意圖，第4B圖繪示第4A圖中沿4B-4B’ 線所示之剖面圖。 第5A圖繪示依照本發明另一較佳實施例之晝素陣列 基板的部分俯視示意圖，第5B圖繪示第5A圖中沿5B-5B’ 線所示之剖面圖。 【主要元件符號說明】 10 ： 電路板 20 ： 軟性電路板 30 ： 晝素陣列基板 32 ： 走線 34 ： 資料驅動晶片 36 ： 掃猫驅動晶片 38 ： 扇出導線 40 ： 顯不區 42 ： 掃胳線 44 ： 資料線 44a :資料線前端 44b :資料線末端 50 ： 測試墊 100 :顯示模組 15 201024874 . 101a、101b :掃瞄線 102 :第一基板 103a、103b :資料線 104 :第二基板 106 :液晶層 108、108a、108b :驅動晶片 110 :畫素 111 :薄膜電晶體lV/3t2^A A position on the wire that is closer to the fracture (ie, there are two positions in total to dissolve the overlapping first-metal layer and the third: metal layer to provide a cross-layer contact path. Even after the driver wafer test is installed and the fan-out wire defect is further found or the fan-out defect is found at any time, the supply can be resumed - the front and rear complex low-impedance fan edge (four) structure at the break line. In the method for complementing the liquid crystal display module disclosed in the embodiment, the fan-out wire is greatly reduced in resistance by two different metal layers φ 2 . Therefore, the actual = 2 no defect end method, that is, the heart The test pad's product test results can also be trusted. In addition, the t metal layer overlaps, and the laser can be used to provide the fan-out wire with a low-conductance yield. k ^ Θ JL shoots the 'Although the invention has been whistling The present invention is not limited to the scope of the present invention, and is intended to be used in the technical scope of the present invention. Scope The definition is subject to the standard. Ύ月导 [Simple diagram description] ρ The first figure shows a schematic view of a pixel array substrate according to a conventional flat panel using glass dot-crystal technology. *, Figure 2 shows according to the present invention - A schematic view of a first embodiment of a liquid crystal display 14 201024874 1 yy γ 模组 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 FIG. 4B is a cross-sectional view taken along line 4B-4B' of FIG. 4A. FIG. 5A is a cross-sectional view of the pixel array according to another preferred embodiment of the present invention. A partial plan view of the substrate, and FIG. 5B is a cross-sectional view taken along line 5B-5B' in FIG. 5A. [Description of main components] 10: Circuit board 20: Flexible circuit board 30: Alizarin array substrate 32: Trace 34: Data Drive Chip 36: Sweeper Drive Chip 38: Fanout Wire 40: Display Area 42: Sweep Line 44: Data Line 44a: Data Line Front End 44b: Data Line End 50: Test Pad 100: Display Mode Group 15 . 101a, 101b: scan line 102: first substrate 103a, 103b: data line 104: second substrate 106: liquid crystal layer 108, 108a, 108b: drive wafer 110: pixel 111: thin film transistor
112:閘極 G 114 :閘極絕緣層 116 :通道層 118a/118b :源極/汲極 120 :扇出導線 122、122a :第一金屬層 124、124a :絕緣層 126、 126a :第二金屬層 127、 128、129 :接觸孔 ⑩ 130 :軟性電路板 134 :走線 A .顯不區 C :晶片待置區 16112: gate G 114: gate insulating layer 116: channel layer 118a/118b: source/drain 120: fan-out wires 122, 122a: first metal layer 124, 124a: insulating layer 126, 126a: second metal Layers 127, 128, 129: contact hole 10 130: flexible circuit board 134: trace A. display area C: wafer holding area 16