TWI699586B - Array substrate and manufacturing method thereof - Google Patents

Abstract

An array substrate includes a substrate, a first data line, a first fanout line, a second data line, a driving module, a second fanout line, and a conductive line. The substrate includes a display region and a non-display region on a side of the non-display region. The non-display region has an edge. The first data line is disposed on the display region. The first fanout line is disposed on the non-display region and connected to the first data line. The first fanout line includes an end substantially level with the edge of the non-display region. The second data line is disposed on the display region. The driving module is disposed on the non-display region. The second fanout line is disposed on the non-display region and connected to the second data line and the driving module. The first fanout line is closer to the edge of the non-display region than the second fanout line is. The conductive line is disposed on the non-display region and connected to the first fanout line and the second fanout line.

Description

Array substrate and manufacturing method thereof

This disclosure relates to an array substrate and a manufacturing method thereof.

The display panel has been widely used in different fields. The display panel includes a driving circuit such as a driving chip arranged in the signal circuit area. The signal circuit area can be at least partly a fan-out area and/or IC bonding. The signal circuit area can have multiple signal circuits to form clusters, and the signal circuits can be in specific shapes in each cluster Distribution, for example, multiple signal lines in the cluster extend toward the contact/pad while converging to form a trapezoidal or fan-like (so called fan-out area) line cluster. In order to adapt to the use of various display panels, the size of the display panel can be readjusted by designing different size masks or cutting methods. However, the cost of designing the photomask is high. If a cutting method is used, the signal lines in the fan-out area and/or the chip bonding area may be disconnected, resulting in abnormal display signals.

An embodiment of the present disclosure provides an array substrate and a manufacturing method thereof, so as to avoid the problem of poor display quality at the cut portion of the array substrate.

An array substrate of an embodiment of the present invention includes a substrate, a first data line, a first fan-out wiring, a second data line, a driving circuit, a second fan-out wiring, and a conductive line. The substrate has a display area and a non-display area on one side of the display area. The non-display area has an edge. The first data line is arranged in the display area. The first fan-out wiring is arranged in the non-display area and connected to the first data line, and the first fan-out wiring has an end substantially flush with the edge of the non-display area. The second data line is arranged in the display area. The driving circuit is arranged in the non-display area. The second fan-out wiring is arranged in the non-display area and connected to the second data line and the driving circuit. The first fan-out wiring is closer to the edge of the non-display area than the second fan-out wiring. The conductive wires are arranged in the non-display area and connected to the first fan-out wiring and the second fan-out wiring.

An array substrate according to an embodiment of the present invention includes a substrate, a first fan-out wiring, a first data line, a second fan-out wiring, a second data line, and a conductive line. The substrate has a display area and a non-display area on one side of the display area, and the non-display area has an edge. The first fan-out wiring is arranged in the non-display area and has an end substantially flush with the edge of the non-display area. The first data line is arranged in the display area and connected with the first fan-out wiring. The second fan-out wiring is arranged in the non-display area. The second data line is arranged in the display area and connected with the second fan-out wiring. The conductive wire is arranged in the non-display area and is electrically connected to the first fan-out wiring and the second fan-out wiring through the first contact hole and the second contact hole, respectively. The first fan-out wiring and the second fan-out wiring are electrically connected through conductive wires.

The manufacturing method of an array substrate according to an embodiment of the present invention includes the following steps. An array mother board is provided. The array mother board includes a substrate, a patterned conductive layer and a driving circuit arranged on the substrate. The patterned conductive layer includes a first fan-out wiring, a first data line, a second fan-out wiring, a second data line, and a conductive line. First data The line and the second data line are electrically connected to the driving circuit through the first fan-out line and the second fan-out line, respectively, the conductive line is electrically connected to the first data line and the second data line, and the conductive line is respectively connected to the first data line and The second data line intersects. The array mother board is cut so that the first fan-out wiring has one end substantially in line with the edge of the substrate.

The manufacturing method of an array substrate according to an embodiment of the present invention includes the following steps. Provide an array motherboard. The array motherboard includes a substrate. The substrate has a display area and a non-display area on one side of the display area. The array motherboard includes a first data line, a second data line and a scan line in the display area and a non-display area. The first fan-out wiring, the second fan-out wiring and the driving circuit of the zone. The first data line and the second data line are electrically connected to the driving circuit through the first fan-out wiring and the second fan-out wiring, respectively, and the scan line intersects the first data line and the second data line respectively. The array mother board is cut so that the first fan-out wiring has one end substantially in line with the edge of the substrate. The conductive wires are arranged between the first fan-out wiring and the second fan-out wiring, so that the conductive wires are electrically connected to the first fan-out wiring and the second fan-out wiring through the first contact hole and the second contact hole, respectively.

Based on the foregoing, in the manufacturing method of the array substrate of one embodiment of the present invention, the first fan-out wiring and the second fan-out wiring are connected by arranging conductive wires, so that the first fan-out wiring can receive the source from the source through the conductive wires. The display data signal of the driver module is transmitted to the corresponding pixel unit to avoid the problem of poor display quality at the cutting portion of the array substrate. In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

10‧‧‧Display Motherboard

100‧‧‧Array Motherboard

100a, 100b‧‧‧array substrate

102‧‧‧Opposite substrate

104‧‧‧Display medium layer

106‧‧‧Substrate

108‧‧‧Conductive wire

110‧‧‧Gate drive module

112a‧‧‧First source driver module

112b‧‧‧Second source driver module

112c‧‧‧Third source driver module

114‧‧‧First side

116‧‧‧Second side

118‧‧‧Third side

120‧‧‧Fourth side

122‧‧‧The first conductive material

124‧‧‧Second conductive material

126‧‧‧Bridge connection

200‧‧‧Array Motherboard

300‧‧‧Array Motherboard

300a‧‧‧Array substrate

AA‧‧‧display area

Section A-A’‧‧‧

Section B-B’‧‧‧

C1‧‧‧Centerline

CUT1‧‧‧First disconnect

CUT2‧‧‧Second disconnect

D‧‧‧Dip pole

D1‧‧‧First direction

D2‧‧‧Second direction

DL‧‧‧Data line

DL1‧‧‧First data line

DL2‧‧‧Second data line

DL3‧‧‧Third data line

FL‧‧‧Fan Out

FL1‧‧‧First fan out wiring

FL1a‧‧‧Disconnect part

FL2‧‧‧Second fan out wiring

FL2a‧‧‧The first group

FL2b‧‧‧The second group

FL3‧‧‧The third fan-out wiring

FL4‧‧‧The fourth fan out wiring

G‧‧‧Gate

IL1‧‧‧First insulating layer

IL2‧‧‧Second insulation layer

IL3‧‧‧Third insulating layer

L1‧‧‧First cutting line

L2‧‧‧Second cutting line

NA‧‧‧Non-display area

S‧‧‧Source

S1, S2‧‧‧Distance

SL‧‧‧Scan line

TH1‧‧‧First contact hole

TH2‧‧‧Second contact hole

TH3‧‧‧The third contact hole

TH4‧‧‧The fourth contact hole

P‧‧‧Pixel unit

P1‧‧‧The first pixel unit

P2‧‧‧Second pixel unit

P3‧‧‧The third pixel unit

P4‧‧‧Fourth pixel unit

PE1‧‧‧The first pixel electrode

PE2‧‧‧Second pixel electrode

R1, R2‧‧‧area

T1‧‧‧The first active component

T2‧‧‧Second active component

W1‧‧‧Welding point

W2‧‧‧Welding point

W3‧‧‧Welding point

W4‧‧‧Welding point

Read the following detailed description and match the corresponding diagram to understand this Multiple aspects of disclosure. It should be noted that many of the features in the drawing are not drawn in actual proportions according to the standard practice in the industry. In fact, the size of the feature can be increased or decreased arbitrarily to facilitate the clarity of the discussion.

FIG. 1 is a cross-sectional view of a display motherboard according to an embodiment of the disclosure; FIG. 2 is a schematic top view of an array motherboard according to an embodiment of the disclosure; FIG. 3 is a schematic top view of an array substrate Figure 4 shows a schematic top view of an array motherboard according to another embodiment of the present invention; Figure 5 shows a schematic top view of an array motherboard according to another embodiment of the present disclosure; Figure 6 illustrates a top view of an array motherboard according to another embodiment of the present disclosure A schematic top view of an array mother board of another embodiment; FIG. 7 is a schematic top view of an array substrate according to another embodiment of the present disclosure; FIG. 8 is a schematic diagram along the section line A-A' of FIG. 7 A schematic cross-sectional view; and Figure 9 shows a schematic cross-sectional view along the line B-B' of Figure 7.

The following will clearly illustrate the spirit of the present disclosure with drawings and detailed descriptions. Any person with ordinary knowledge in the relevant technical field who understands the embodiments of the present disclosure can change and modify the techniques taught in the present disclosure. Depart from the spirit and scope of this disclosure. For example, the statement that "the first feature is formed on or on the second feature" will include the first feature and the second feature in the embodiment Have direct contact; and also include the first feature and the second feature as indirect contact, with additional features formed between the first feature and the second feature. In addition, the present disclosure will reuse component numbers and/or words in multiple examples. The purpose of repetition is to simplify and clarify, and it does not determine the relationship between multiple embodiments and/or the discussed settings.

In addition, relative terms such as "below", "below", "below", "above" or "above" or similar terms are used in this article to facilitate the description of what is shown in the diagram The relationship of one element or feature to another element or feature. In addition to describing the position of the device in the diagram, the relative position vocabulary includes the different positions of the device under use or operation. When the device is additionally set (rotated by 90 degrees or other facing orientation), the relative terms of the orientation used in this article can also be explained accordingly.

FIG. 1 is a cross-sectional view of a display motherboard 10 according to an embodiment of the disclosure. Please refer to FIG. 1, the display motherboard 10 includes an array motherboard 100, an opposite substrate 102 and a display medium layer 104. The display medium layer 104 is disposed between the array mother board 100 and the opposite substrate 102, and the display medium layer 104 may include a non-self-luminous display medium layer or a self-luminous display medium layer. In this embodiment, a liquid crystal display panel made of liquid crystal material in the non-self-luminous display medium layer 104 is taken as an example for description, but is not limited thereto. The opposite substrate 102 may include a color filter substrate, but is not limited thereto.

FIG. 2 is a schematic top view of an array motherboard 100 according to an embodiment of the disclosure. The array mother board 100 includes a substrate 106, a fan-out wiring FL, a conductive line 108, a data line DL, a scan line SL, a pixel unit P, and a gate driving module 110. The array mother board 100 also includes first source electrodes located on the upper and lower sides of the substrate 106 The driving module 112a, the second source driving module 112b, and the third source driving module 112c, but the invention is not limited thereto. For the convenience of description, Figure 2 shows the first direction D1 and the second direction D2, and the first direction D1 is different from the second direction D2. For example, the first direction D1 and the second direction D2 are respectively those of Figure 2 The longitudinal direction and the lateral direction are orthogonal to each other. The first source driving module 112a, the second source driving module 112b, and the third source driving module 112c are substantially spaced along the second direction D2. The data line DL is electrically connected to the first, second, and third source driving modules 112a, 112b, and 112c through the fan-out wiring FL. The conductive wire 108 connects at least two adjacent fan-out wires FL. For example, at least one fan-out trace FL with one end connected to the first source driver module 112a is connected to at least one adjacent fan-out trace FL with one end connected to the second source driver module 112b through the conductive wire 108. In detail, The end closest to the second source driver module 112b is connected to the fan-out trace FL of the first source driver module 112a through the conductive line 108, and the end closest to the first source driver module 112a is connected to the second source driver module. Fanout routing of group 112b. At least one fan-out trace FL connected to the second source driver module 112b is connected to at least one adjacent fan-out trace FL connected to the third source driver module 112c through the conductive line 108, in detail, is closest to the third source One end of the driver module 112c is connected to the fan-out trace FL of the second source driver module 112b through the conductive line 108, and the end closest to the second source driver module 112b is connected to the fan-out trace of the third source driver module 112c FL. In one embodiment, the conductive wire 108 extends along the second direction D2. In other words, the conductive line 108 is substantially parallel to the second direction D2 and intersects the fan-out trace FL. In other embodiments, the present invention may have more than four source driving modules.

The substrate 106 has a display area AA and a non-display area surrounding the display area AA Show area NA. The data line DL, the scan line SL and the pixel unit P are arranged on the display area AA. The fan-out wiring FL, the conductive line 108, the gate driving module 110 and the first, second and third source driving modules 112a, 112b, 112c are arranged on the non-display area NA. In one embodiment, the data lines DL extend along the first direction D1 and are arranged along the second direction D2, the scan lines SL extend along the second direction D2 and are arranged along the first direction D1, and the scan lines SL intersect the data lines DL. The materials of the scan lines SL, the data lines DL, and the conductive lines 108 can be metal materials or other conductive materials. For example: alloys, metal nitrides, metal oxides, metal oxynitrides, or other suitable materials), or stacked layers of metal materials and other conductive materials. The material of the substrate 106 can be glass, quartz, organic polymer, or opaque/reflective material (for example: conductive material, metal, wafer, ceramic, or other applicable materials), or other applicable materials .

The pixel unit P is electrically connected to the first, second, and third source driving modules 112a, 112b, 112c through the data line DL, and is electrically connected to the gate driving module 110 through the scan line SL. The first, second, and third source driving modules 112a, 112b, and 112c are used for transmitting display data signals to the pixel unit P, and the gate driving module 110 is used for transmitting gate driving signals to the pixel unit P. The gate driver module 110 may be a gate driver on array (GOA) circuit directly formed on the substrate 106. In some embodiments, the common voltage is provided to the substrate 102, and the pixel unit P can control the display medium layer 104 to display the corresponding display data according to the common voltage and the voltage value corresponding to the display data signal.

In this embodiment, the display motherboard 10 is cut along the first cutting line L1 and the second cutting line L2 to obtain a display panel with a desired size. For simplicity, only the cutting array motherboard is shown here. 100 represents the cutting display mother board 10. in Therefore, cutting the array mother board 100 can obtain the array substrate 100a having a desired size. In this embodiment, the first cutting line L1 is located on the right side of the center line C1 of the array motherboard 100 along the first direction D1. The first cutting line L1 is substantially parallel to the first direction D1, and the second cutting line L2 is substantially parallel to the second direction D2. The first cutting line L1 and the second cutting line L2 pass through the display area AA. Specifically, the first cutting line L1 passes through the fan-out line FL. The cutting method is, for example, using a cutter wheel, a diamond knife or a laser. In this embodiment, since the cutting method is used to obtain the display panel of the desired size, the position of the first cutting line L1 and the second cutting line L2 can be moved to obtain the desired size. The display panel does not need to design a new mask pattern. In this way, the advantages of flexible display panel size and cost saving can be achieved at the same time. In other embodiments, the cutting of the display mother board 10 can be performed in a state where the display medium layer 104 is not disposed between the array mother board 100 and the counter substrate 102, and the display medium layer 104 can be disposed on both after cutting. between. The array substrate 100a according to an embodiment of the present invention can be applied to a twisted nematic (TN) display panel or a vertical alignment (VA) display panel. And it is suitable for the display panel of normally black mode (normally black) or normally white mode (normally white).

FIG. 3 shows a schematic top view of the array substrate 100a. At this time, the non-display area NA is adjacent to the first side 114 and the second side 116 of the display area AA. In detail, the gate drive module 110 is located on the non-display area NA adjacent to the first side 114 of the display area AA, and the second and third source drive modules 112b and 112c are located on the second side 116 adjacent to the display area AA. In the non-display area NA, the second source driving module 112b is closer to the first cutting line L1 than the third source driving module 112c (see Figure 2). In other words, the second source driving module 112b is The third source driver module 112c It is closer to the fourth side 120 of the non-display area NA. In one embodiment, the first side 114 is substantially parallel to the first direction D1, and the second side 116 is substantially parallel to the second direction D2. The display area AA also has a third side 118, the non-display area NA has a fourth side 120, and the third side 118 of the display area AA is connected to the fourth side 120 of the non-display area NA. Specifically, the third side of the display area AA One end of the side 118 is connected to one end of the fourth side 120 of the non-display area NA. In one embodiment, the third side 118 of the display area AA and the fourth side 120 of the non-display area NA extend along the first direction D1. In other words, the third side 118 of the display area AA may be substantially parallel to the non-display area NA The fourth side 120.

The fan-out wiring FL passed by the first cutting line L1 is defined as the first fan-out wiring FL1, one end of which is connected to the second source driver module 112b and connected to the first fan-out wiring FL1 through the conductive wire 108 Defined as the second fan-out wiring FL2, one end is connected to the second source driver module 112b and does not touch the conductive line 108 connected to the first fan-out wiring FL1, the fan-out wiring FL is defined as the third fan-out wiring FL3, one end The fan-out wiring FL connected to the third source driving module 112c is defined as the fourth fan-out wiring FL4. The third fan-out wiring FL3 is located between the fourth fan-out wiring FL4 and the first fan-out wiring FL1. In other words, the first fan-out wiring FL1 has a disconnected portion FL1a, and the second fan-out wiring FL2 maintains one end connected to the source driving module (for example, the second source driving module 112b) and the other end to the data line DL . Since the first cutting line L1 passes through the first fan-out wiring FL1, the first fan-out wiring FL1 has an end substantially flush with the edge of the non-display area NA (for example, the fourth side 120 of the non-display area NA). In other words, the first fan-out wiring FL1 has an end substantially flush with the edge of the substrate 106. In this embodiment, the first fan-out wiring FL1 is closer to the edge of the non-display area NA than the second fan-out wiring FL2. change In other words, the first fan-out wiring FL1 is closer to the fourth side 120 of the non-display area NA than the second fan-out wiring FL2.

The pixel units P electrically connected to the first fan-out wiring FL1, the second fan-out wiring FL2, the third fan-out wiring FL3, and the fourth fan-out wiring FL4, respectively, are defined as the first pixel unit P1 and the second pixel Unit P2, third pixel unit P3, and fourth pixel unit P4. The first pixel unit P1 is closer to the edge of the display area AA (for example, the third side 118 of the display area AA) than the second pixel unit P2. Since the first fan-out wiring FL1 is cut off and the connection between the first source driving module 112a (see Figure 2), the data line DL connected to the first fan-out wiring FL1 cannot pass from the first source driving module The display data signal of the group 112a is given to the first pixel unit P1.

The display data signal from the second source driving module 112b is sequentially transmitted to the second pixel unit P2 via the second fan-out wiring FL2 and the data line DL. Since the first fan-out wiring FL1 is connected to the second fan-out wiring FL2 through the conductive wire 108, the display data signal from the second source driving module 112b can sequentially go through the second fan-out wiring FL2, the conductive wire 108, The first fan-out wiring FL1 and the data line DL are transferred to the first pixel unit P1, so that the first pixel unit P1 can display the same picture as the second pixel unit P2. Therefore, even if the data line DL connected to the first fan-out wiring FL1 cannot transmit the display data signal from the first source driving module 112a to the first pixel unit P1, the data line DL can transmit the display data signal from the second source driving module. The display data signal of the group 112b is given to the first pixel unit P1. For example, by making the second pixel unit P2 display the dark state, the effect of making the first pixel unit P1 also display the dark state (because the first pixel unit P1 and the second pixel unit P2 pass through the conductive wire 108 electrical connection) to avoid the edge of the display panel along the first cutting line L1 (see Figure 2) (for example, near the third side of the display area AA) Area of 118) shows the problem of reduced quality. In other words, the second source driving module 112b is made to transfer the black screen display data signal to the first pixel unit P1 through the second fan-out wiring FL2, the conductive line 108, and the data line DL in sequence, and then through the second fan-out in sequence. The line FL2 and the data line DL are transferred to the second pixel unit P2, so that the first pixel unit P1 and the second pixel unit P2 display the dark state at the same time, effectively avoiding the problem of the quality of the display panel cutout. .

The first pixel unit P1 and the second pixel unit P2 are closer to the edge of the substrate 106 than the third pixel unit P3 and the fourth pixel unit P4. In other words, the first pixel unit P1 and the second pixel unit P2 are The third pixel unit P3 and the fourth pixel unit P4 are closer to the third side 118 of the display area AA. In one embodiment, the minimum distance S1 between the first pixel unit P1 and the substrate 106 is between about 25 microns and about 200 microns, and the minimum distance S2 between the second pixel unit P2 and the substrate 106 is about 50. Between micrometers and about 400 micrometers. Therefore, the normal display area of the display area AA is substantially not affected by the cutting of the display motherboard 10.

In one embodiment, a part of the conductive wire 108 is located between the third fan-out wiring FL3 and the fourth fan-out wiring FL4, so that the third fan-out wiring FL3 is connected to the fourth fan-out wiring FL4. By cutting this part of the conductive line 108 along the first disconnection line CUT1, the third fan-out wiring FL3 and the fourth fan-out wiring FL4 connected by the conductive line 108 are disconnected, so that the same line (for example: Each third pixel unit P3 and each fourth pixel unit P4 controlled by the data line DL display their respective display screens as the display screen of the display panel. Specifically, in one embodiment, the fan-out trace FL (for example: the first fan-out trace FL1, the second fan-out trace FL2, the third fan-out trace FL3, and the fourth fan-out trace FL4), the data line DL, The scan line SL and the conductive line 108 are composed of the same patterned conductive layer. change In other words, there is no need for an additional process to form the conductive line 108 to connect the first fan-out wiring FL1 and the second fan-out wiring FL2, and by disconnecting the third fan-out wiring FL3 and the fourth fan-out wiring FL3 connected by the conductive wiring 108 The fan-out wiring FL4 can achieve the effect of the normal display of the display panel. In this way, the size of the display panel can be flexible and the advantages of saving cost and time can be achieved at the same time.

FIG. 4 is a schematic top view of an array substrate 100b according to another embodiment of the invention. In an embodiment, the second fan-out wiring FL2 connected by the conductive line 108 may be disconnected along the second disconnection line CUT2, so that the second pixel unit P2 partially displays the dark state and partially displays the normal state. Desired display screen. Specifically, by disconnecting the second fan-out wiring FL2 connected by the conductive wire 108, the second fan-out wiring FL2 has a first group FL2a and a second group FL2b, and the second fan-out wiring FL2 of the first group FL2a The conductive line 108 is still connected to the first fan-out trace FL1, and the conductive line 108 between the second fan-out trace FL2 of the second group FL2b and the second fan-out trace FL2 of the first group FL2a is cut off. Make the second pixel unit P2 electrically connected to the second fan-out wiring FL2 of the first group FL2a display a dark state, and make the second pixel unit P2 electrically connected to the second fan-out wiring FL2 of the second group FL2b display normal Picture. In this way, the second fan-out trace FL2 of the first group FL2a and the second group FL2b of the second group FL2b can be flexibly selected according to the desired area range of the dark state or the desired normal display area. The number of fan-out wiring FL2 achieves the advantage of flexible display area of the display panel. The conductive wires 108 shown in FIGS. 2 to 4 are each connected to two adjacent fan-out traces FL, but the present invention is not limited to this. The conductive wires 108 can each connect three or more adjacent fans according to actual needs. Leave the line FL. It should be understood that the first disconnection line CUT1 and the second disconnection line CUT2 are not physical lines, but represent a state where the conductive line 108 is cut off.

FIG. 5 is a schematic top view of an array motherboard 200 according to another embodiment of the disclosure. The difference between Figure 5 and Figure 2 lies in the position of the first cutting line L1. Specifically, in this embodiment, the first cutting line L1 is located on the left side of the center line C1 of the display motherboard 10 along the first direction D1. . Since the conductive wire 108 is also connected to the second fan-out wiring FL2 and the third fan-out wiring FL3, even if the display motherboard 10 is cut along the first cutting line L1, the above-mentioned method can still be used to avoid cutting of the display panel The display quality is reduced, and a display panel with a desired display area is obtained. In this way, the display motherboard 10 is cut along the first cutting line L1 without separating the left and right sides of the display motherboard 10. This improves the cutting simplicity and cutting efficiency of the display motherboard 10. The detailed description is as described in Figs. 2 to 4, and the discussion is not repeated here for brevity.

The embodiments in FIG. 1 to FIG. 5 show that the conductive line 108 and the fan-out wiring FL are formed by the same patterned conductive layer. In other embodiments, the conductive line 108 and the fan-out wiring FL may be formed of different patterned conductive layers, which will be described in more detail below.

FIGS. 6-9 show that the conductive line 108 and the fan-out wiring FL are formed of different patterned conductive layers. FIG. 6 is a schematic top view of an array motherboard 300 according to another embodiment of the disclosure. The difference between the embodiment shown in Fig. 6 and the embodiment shown in Figs. 1 to 5 is that the first cutting line L1 and the second cutting line L2 of the embodiment shown in Fig. 5 only cut the array As for the motherboard 300, the counter substrate 102 and the liquid crystal layer are assembled after cutting the array motherboard 300, and the array motherboard 300 of this embodiment does not have conductive wires 108. The array mother board 300 is cut along the first cutting line L1 and the second cutting line L2 to obtain an array substrate 300a having a desired size (see FIG. 7). The method of cutting the array motherboard 300 can be similar to that shown in Figure 2. The cutting method mentioned above will not be repeated here.

FIG. 7 is a schematic top view of the array substrate 300a. At this time, the non-display area NA is adjacent to the first side 114 and the second side 116 of the display area AA. In detail, the gate drive module 110 is located on the non-display area NA adjacent to the first side 114 of the display area AA, and the second and third source drive modules 112b and 112c are located on the second side 116 adjacent to the display area AA. On the non-display area NA.

The fan-out wiring FL passed by the first cutting line L1 is defined as the first fan-out wiring FL1. In other words, the first fan-out wiring FL1 has a disconnection portion FL1a. Since the first cutting line L1 passes through the first fan-out wiring FL1, the first fan-out wiring FL1 has an end substantially flush with the edge of the non-display area NA (for example, the fourth side 120 of the non-display area NA). In other words, the first fan-out wiring FL1 has an end substantially flush with the edge of the substrate 106. The pixel unit P connected to the first fan-out wiring FL1 is defined as the first pixel unit P1, and the data line DL connected to the first fan-out wiring FL1 and the first pixel unit P1 is defined as the first data line DL1. The minimum distance S1 between the first pixel unit P1 and the substrate 106 is between about 25 microns and about 200 microns. Since the connection between the first fan-out wiring FL1 and the first source driving module 112a is cut off, the display data signal from the first source driving module 112a cannot pass through the first fan-out wiring FL1 and the first data line DL1 Passed to the first pixel unit P1, so that the first pixel unit P1 cannot present the desired display screen.

In one embodiment, the conductive line 108 is disposed in the non-display area NA adjacent to the second side 116 of the display area AA, so that the first fan-out wiring FL1 is connected to at least one adjacent fan-out wiring FL. The fan-out wiring FL that is not passed by the first cutting line L1 and is connected to the first fan-out wiring FL1 through the conductive line 108 is defined as the second fan-out wiring FL2, and the remaining fan-out wiring FL is defined as the third fan-out wiring FL3. First The second fan-out wiring FL2 is located between the third fan-out wiring FL3 and the first fan-out wiring FL1. In other words, the conductive wire 108 is disposed between the first fan-out wiring FL1 and the second fan-out wiring FL2. The first fan-out wiring FL1 and the second fan-out wiring FL2 are electrically connected through the conductive wire 108. In this embodiment, the first fan-out wiring FL1 is closer to the edge of the non-display area NA (for example, the fourth side 120 of the non-display area NA) than the second fan-out wiring FL2. The second fan-out wiring FL2 and the third fan-out wiring FL3 maintain one end connected to the source driving module (for example, the second source driving module 112b, the third source driving module 112c) and the other end to the data line DL connection. The pixel units P electrically connected to the second fan-out wiring FL2 and the third fan-out wiring FL3 respectively are defined as the second pixel unit P2 and the third pixel unit P3. The minimum distance S2 between the second pixel unit P2 and the substrate 106 is between about 50 microns and about 400 microns. The first pixel unit P1 is closer to the edge of the display area AA (for example, the third side 118 of the display area AA) than the second pixel unit P2. The data lines DL respectively connected to the second fan-out wiring FL2 and the third fan-out wiring FL3 are defined as the second data line DL2 and the third data line DL3. In this way, the display data signal from the second source driving module 112b is sequentially transferred to the second pixel unit P2 via the second fan-out wiring FL2 and the second data line DL2. Since the first fan-out wiring FL1 is connected to the second fan-out wiring FL2 through the conductive wire 108, the display data signal from the second source driving module 112b can sequentially go through the second fan-out wiring FL2, the conductive wire 108, The first fan-out wiring FL1 and the first data line DL1 are transferred to the first pixel unit P1. After the array substrate 300a, the counter substrate 102 and the display medium layer 104 are assembled into a display panel, the first pixel unit P1 can display the same picture as the second pixel unit P2. For example, by making the first pixel unit P1 and the second pixel unit P2 appear in a dark state, the problem of poor display quality at the cut portion of the display panel is avoided.

The area R1 and the area R2 are respectively enlarged schematic views of the first pixel unit P1 and the second pixel unit P2. The first pixel unit P1 includes a first active device T1 and a first pixel electrode PE1, and the first pixel electrode PE1 is electrically connected to the first active device T1. The first active device T1 includes a gate G, a channel layer (not shown), a source S and a drain D. The gate electrode G, the drain electrode D, and the source electrode S are, for example, metal materials. In this embodiment, the first active device T1 is electrically connected to the corresponding scan line SL and the corresponding data line DL. Specifically, the gate electrode G is electrically connected to the scan line SL. The source electrode S is electrically connected to the data line DL, and the drain electrode D is electrically connected to the pixel electrode. The first active device T1 may be a bottom gate type thin film transistor or a top gate type thin film transistor, but the invention is not limited thereto. The second pixel unit P2 includes a second active element T2 and a second pixel electrode PE2. The second pixel electrode PE2 is electrically connected to the second active element T2. The structure of the second pixel unit P2 is similar to the first pixel. Unit P1, so it will not be repeated here.

Fig. 8 is a schematic cross-sectional view taken along the line A-A' of Fig. 7. Figure 9 is a schematic cross-sectional view taken along the line B-B' of Figure 7; Please refer to FIGS. 7-9 at the same time. In this embodiment, the data line DL and the drain electrode D are formed by the same patterned conductive layer. The array mother board 300 (or the array substrate 300a) has a first insulating layer IL1, a second insulating layer IL2, and a third insulating layer IL3 on the substrate 106. In this embodiment, the first insulating layer IL1 may be a gate insulating layer and located on the gate G (not shown in FIGS. 8 and 9), and the second insulating layer IL2 is located on the channel layer (not shown) and the source Pole S (not shown in Figures 8 and 9), drain D, data line DL (for example: first data line DL1 and second data line DL2) and fan-out wiring FL (for example: first fan-out wiring FL1 , Between the second fan-out wiring FL2 and the third fan-out wiring FL3). The third insulating layer IL3 is located on the drain D and the data line DL.

In this embodiment, the conductive line 108 and the fan-out wiring FL are formed by patterned conductive layers of different layers. In one embodiment, the connection between the conductive wire 108 and the first fan-out wiring FL1 and the second fan-out wiring FL2 is to set the conductive wire 108 first, and then weld the first fan-out wiring FL1 and the conductive wire 108 to interlace And the intersection of the second fan-out trace FL2 and the conductive line 108 to form a fusion point of the first fan-out trace FL1 and the conductive line 108 and a fusion point of the second fan-out trace FL2 and the conductive line 108. In other embodiments, the conductive wire 108 may be electrically connected to the first fan-out trace FL1 through the first conductive material 122 located in the first contact hole TH1, and the conductive wire 108 may be electrically connected to the first fan-out trace FL1 located in the second contact hole TH2. The conductive material 124 is electrically connected to the second fan-out wiring FL2. In an embodiment, the second insulating layer IL2 is located on the first conductive material 122 and the second conductive material 124. In one embodiment, the first conductive material 122 and the second conductive material 124 can be formed of the same patterned conductive layer as the pixel electrodes (for example, the first pixel electrode PE1 and the second pixel electrode PE2). One more process is used to form the first conductive material 122 and the second conductive material 124 to achieve the advantages of saving cost and time. In one embodiment, the material of the first conductive material 122, the material of the second conductive material 124, and the material of the pixel electrode are the same. For example, the materials of the first conductive material 122 and the second conductive material 124 may be metal materials or other conductive materials. For example: alloys, metal nitrides, metal oxides, metal oxynitrides, or other suitable materials), or stacked layers of metal materials and other conductive materials. For example, the material of the first conductive material 122 and the second conductive material 124 may be indium tin oxide or indium zinc oxide.

In one embodiment, a part of the scan line SL located between the third data line DL3 and the second data line DL2 is cut, so that the scan line SL has separate The section facing the second data line DL2 and the section facing the third data line DL3. In this way, the first pixel unit P1 and the second pixel unit P2 do not receive the gate driving signal from the gate driving module 110. In one embodiment, the scan line SL located between the third data line DL3 and the second data line DL2 is cut along the third cutting line L3. In other words, the third cutting line L3 passes through the third data line DL3 and the second data line DL3. Each scan line SL between the data lines DL2 makes the pixel unit P (for example, the first pixel unit P1 and the second pixel unit P2) located on the right side of the third cutting line L3 and the gate driving module 110 The connection therebetween is broken, and the third cutting line L3 passes through the display area AA and is substantially parallel to the first direction D1. The cutting method is laser cutting, for example.

In one embodiment, a bridge line 126 is provided between the data line DL located on the right side of the third cutting line L3 and the pixel electrode of the corresponding pixel unit P. For example, the bridge line 126 is provided on the first data line DL1 Between the first pixel electrode PE1 and between the second data line DL2 and the second pixel electrode PE2, so that the first data line DL1 is electrically connected to the first pixel electrode PE1 through the bridge wire 126, and the second The data line DL2 is electrically connected to the second pixel electrode PE2 through the bridge line 126. In this way, the display data signal from the second source driving module 112b can be sequentially transmitted to the second pixel electrode PE2 through the second fan-out wiring FL2, the second data line DL2, and the bridge line 126, so that the second picture The pixel cell P2 presents the desired display screen, and the display data signal from the second source driving module 112b can also sequentially pass through the second fan-out wiring FL2, the conductive line 108, the first fan-out wiring FL1, and the first fan-out wiring FL1. The data line DL1 and the bridge line 126 are transferred to the first pixel electrode PE1, so that the first pixel unit P1 presents the desired display screen, and since the first fan-out wiring FL1 and the second fan-out wiring FL2 are electrically connected through the conductive line 108 Sexual connection (as mentioned before), so As a result, the first pixel unit P1 and the second pixel unit P2 can present the same desired display screen only through the second source driver module 112b without going through the gate driving module 110, so that the operation The process is simplified. For example, the first pixel unit P1 and the second pixel unit P2 are rendered in a dark state, so as to avoid the problem of poor display quality at the cut portion of the display panel.

The bridge line 126 is located in the display area AA of the substrate 106 and on the second insulating layer IL2. In one embodiment, the bridge line 126 can be electrically connected to the first data line DL1 and the second data line DL2 through the third contact hole TH3 and electrically connected to the drain D through the fourth contact hole TH4. For example, the third contact hole TH3 and the fourth contact hole TH4 can be formed at the same time. In this way, the advantage of saving process time can be achieved. However, the present invention is not limited to this. In other embodiments, the third contact hole TH3 and the fourth contact hole TH4 can also be formed at different times. In other embodiments, the intersection of the bridge line 126 and the first data line DL1 and the intersection of the bridge line 126 and the first pixel electrode PE1 can be welded to form the welding point of the bridge line 126 and the first data line DL1 The welding point W2 of W1 and the bridge line 126 and the first pixel electrode PE1, and the intersection of the bridge line 126 and the second data line DL2 and the intersection of the bridge line 126 and the second pixel electrode PE2 to form a bridge The welding point W3 of the line 126 and the second data line DL2 and the welding point W4 of the bridge line 126 and the second pixel electrode PE2.

In one embodiment, the bridge line 126 and the pixel electrodes (for example, the first pixel electrode PE1 and the second pixel electrode PE2) are made of the same patterned conductive layer. In this way, there is no need for an additional process to form the bridge. The line 126 connects the first data line DL1 and the second data line DL2 to achieve the effect of the normal display of the display panel. In this way, the size flexibility of the display panel can be achieved at the same time The advantages of optimizing and saving cost and time. The material of the bridge line 126 can be a metal material or other conductive materials. For example: alloys, metal nitrides, metal oxides, metal oxynitrides, or other suitable materials), or stacked layers of metal materials and other conductive materials.

In summary, the array substrate of an embodiment of the present invention includes a substrate and a first fan-out trace, a first data line, a second fan-out trace, a second data line, a conductive line, and a first pixel disposed on the substrate. Unit and second pixel unit, the first fan-out wiring and the second fan-out wiring are respectively connected to the first pixel unit and the second pixel unit through the first data line and the second data line, the first fan-out wiring has One end is connected to the first data line and the other end is aligned with the edge of the substrate. The first fan-out trace is electrically connected to the second fan-out trace, so that the display data signal from the source driver module can be sequentially routed through the second fan-out The wire, the conductive wire and the first fan-out wire are transferred to the first pixel unit. In this way, the first pixel unit and the second pixel unit can display the same screen, and by making the first pixel unit and the second pixel unit The two-pixel unit is in a dark state to avoid the problem of poor display quality at the cutout of the array substrate.

The above summarizes the features of several implementations or embodiments, so that those with ordinary knowledge in the field can better understand the disclosure from various aspects. Those skilled in the art should understand, and can easily design or modify other processes and structures based on this disclosure, so as to achieve the same purpose and/or to achieve the implementations or embodiments introduced herein The same advantages. Those skilled in the art should also understand that these equivalent structures do not deviate from the spirit and scope of the disclosure. Without departing from the spirit and scope of this disclosure, various changes, substitutions or modifications can be made to this disclosure.

100a‧‧‧Array substrate

106‧‧‧Substrate

108‧‧‧Conductive wire

110‧‧‧Gate drive module

112b‧‧‧Second source driver module

112c‧‧‧Third source driver module

114‧‧‧First side

116‧‧‧Second side

118‧‧‧Third side

120‧‧‧Fourth side

AA‧‧‧display area

CUT1‧‧‧First disconnect

D1‧‧‧First direction

D2‧‧‧Second direction

DL‧‧‧Data line

FL1‧‧‧First fan out wiring

FL1a‧‧‧Disconnect part

FL2‧‧‧Second fan out wiring

FL3‧‧‧The third fan-out wiring

FL4‧‧‧The fourth fan out wiring

NA‧‧‧Non-display area

S1‧‧‧Pitch

S2‧‧‧Pitch

P1‧‧‧The first pixel unit

P2‧‧‧Second pixel unit

P3‧‧‧The third pixel unit

P4‧‧‧Fourth pixel unit

Claims (10)

An array substrate includes: a substrate having a display area and a non-display area located on one side of the display area, wherein the non-display area has an edge; a first data line arranged in the display area; and a first sector Outgoing wiring is arranged in the non-display area and connected to the first data line, the first fan-out wiring has an end substantially flush with the edge of the non-display area; a second data line is arranged in the display area; A driving circuit is disposed in the non-display area; a second fan-out wiring is disposed in the non-display area and connects the second data line and the driving circuit, wherein the first fan-out wiring is closer to the non-display area than the second fan-out wiring The edge of the display area; and a conductive line disposed in the non-display area and connected to the first fan-out wiring and the second fan-out wiring. The array substrate according to claim 1, wherein the first fan-out wiring, the second fan-out wiring, the first data line, the second data line, and the conductive line are composed of the same patterned conductive layer. An array substrate includes: a substrate having a display area and a non-display area located on one side of the display area, wherein the non-display area has an edge; a first fan-out wiring is arranged in the non-display area and has a The non-significant The edge of the display area is substantially flush with one end; a first data line is arranged in the display area and connected with the first fan-out wiring; a second fan-out wiring is arranged in the non-display area; a second A data line is arranged in the display area and connected to the second fan-out wiring; and a conductive line is arranged in the non-display area and is respectively routed to the first fan-out through a first contact hole and a second contact hole The wire and the second fan-out wire are electrically connected, wherein the first fan-out wire and the second fan-out wire are electrically connected through the conductive wire. The array substrate according to claim 3, further comprising: a scan line disposed on the display area and intersecting the first data line and the second data line respectively, wherein the scan line has a cross-section facing The first data line. The array substrate according to claim 3, further comprising: a first pixel unit disposed on the display area, wherein the first pixel unit includes a first pixel electrode, the first pixel unit and the The minimum distance between the substrates is between about 25 microns and about 200 microns; and a first bridge line is disposed on the display area, wherein the first bridge line is connected to the first data line through a third contact hole, The first bridge wire contacts the first pixel electrode. The array substrate according to claim 3, further comprising: a second pixel unit disposed on the display area, wherein the second pixel unit includes a second pixel electrode, the second pixel unit and the The minimum distance between the substrates is between about 50 microns and about 400 microns; and a second bridge line is disposed on the display area, wherein the second bridge line is connected to the second data line through a fourth contact hole, The second bridge wire contacts the second pixel electrode. A method for manufacturing an array substrate includes: providing an array mother board, wherein the array mother board includes a substrate, a patterned conductive layer disposed on the substrate, and a driving circuit, the patterned conductive layer includes a first fan Outgoing wiring, a first data line, a second fan-out wiring, a second data line, and a conductive line, wherein the first data line and the second data line pass through the first fan-out wiring and the second The fan-out wiring is electrically connected to the driving circuit, the conductive line is electrically connected to the first data line and the second data line, and the conductive line intersects the first data line and the second data line respectively; and cutting In the array mother board, the first fan-out wiring has one end substantially in line with the edge of the substrate. The method according to claim 7, wherein the patterned conductive layer further includes a third fan-out trace, a third data line, a fourth fan-out trace, and a fourth data line, and the third data line passes through the The third fan-out wiring is electrically connected to the driving circuit, the fourth data line is electrically connected to the driving circuit through the fourth fan-out wiring, and the third fan-out wiring is located between the fourth fan-out wiring and the Between the first fan-out wiring, a part of the conductive wire is located between the third fan-out wiring and the fourth fan-out wiring, so that the third fan-out wiring is electrically connected to the fourth fan-out wiring, the method It further includes: cutting the part of the conductive thread. A method for manufacturing an array substrate includes: providing an array motherboard, wherein the array motherboard includes a substrate, the substrate has a display area and a non-display area located on one side of the display area, the array motherboard includes A first data line, a second data line, and a scan line in the display area, and a first fan-out wiring, a second fan-out wiring, and a driving circuit located in the non-display area. The first data line and the second The two data lines are electrically connected to the driving circuit through the first fan-out wiring and the second fan-out wiring, and the scan line intersects the first data line and the second data line respectively; cutting the array motherboard , So that the first fan-out trace has one end substantially cut to the edge of the substrate; and a conductive line is arranged between the first fan-out trace and the second fan-out trace, so that the conductive line passes through a first The contact hole and a second contact hole are electrically connected to the first fan-out wiring and the second fan-out wiring. The method according to claim 9, wherein the array motherboard further includes a third fan-out trace and a third data line located in the non-display area, and an active device located in the display area and electrically connected to the active device A pixel electrode, the third data line is electrically connected to the driving circuit through the third fan-out wiring, wherein the scan line has a part located between the third data line and the second Between the data lines, the method further includes: cutting the portion of the scan line so that the scan line has a cross section facing the second data line; and arranging a bridge line between the first data line and the pixel electrode In between, the bridge wire is electrically connected to the first data line through a third contact hole.

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