CN108713355B - 路由组件及使用路由组件的系统 - Google Patents
路由组件及使用路由组件的系统 Download PDFInfo
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- H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
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- H05K7/00—Constructional details common to different types of electric apparatus
- H05K7/14—Mounting supporting structure in casing or on frame or rack
- H05K7/1438—Back panels or connecting means therefor; Terminals; Coding means to avoid wrong insertion
- H05K7/1439—Back panel mother boards
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Abstract
用于一电子设备的一种路由组件具有一前面,前面具有一阵列的连接器端口且各连接器端口包括安装于其中的一第一连接器。一线缆的一第一端能直接端接于所述第一连接器且所述线缆能埋设于一托盘中,托盘设置成朝向一芯片封装延伸。所述线缆从托盘延伸且端接于一第二连接器,第二连接器能连接于所述芯片封装以提供在所述第一连接器和所述第二连接器之间的一通信路径,通信路径绕过任何支撑电路基板。
Description
相关申请
本申请是2017年1月11提交的PCT申请PCT/US2017/012917的国家阶段,该申请通过援引其整体上并入本文并进而主张于2016年1月11日提交的美国临时专利申请US62/277275的优先权。
技术领域
本发明概括而言涉及适合用于将高速信号从一芯片封装的芯片或者处理器以低损耗传输至背板连接器和输入/输出(I/O)连接器,而更具体而言涉及一集成连接器接口芯片封装路由组件,其构造成安装在一电子设备的壳体内且提供直接从芯片/处理器引导至一阵列的外部连接器的多个数据传输通道。
背景技术
电子设备(诸如路由器、服务器、交换机等)需要以高数据传输速度传输数据,以满足在许多终端用户设备中的对带宽和流模式音频及视频的传送日益提高的需求。芯片是这些路由器、交换机及其它设备的心脏。这些芯片典型地包括一处理器(诸如一ASIC(专用集成电路)或者一FPGA(现场可编程门阵列)等),这些芯片具有多个晶粒,晶粒通常通过导电焊料凸点或者其它方便的连接方式连接于一基板(创建一封装)。所述封装可以包括穿过基板延伸至焊料球的微导孔或镀覆的通孔。这些焊料球包括一球栅格阵列,所述封装通过球栅格阵列贴接于母基板(motherboard)。母基板包括形成于其内的多条迹线,所述多条迹线限定包括用于传输高速数据信号的差分信号对的传输线、与差分信号对相关的接地路径以及用于电源、时钟和逻辑信号以及其它组件的各种低速传输线。这些迹线包括从ASIC路由至所述设备的I/O连接器(外部连接器连接于I/O连接器,以提供一个或多个外部插头连接器和芯片元件之间的一连接)的迹线。其它迹线从ASIC路由至背板连接器,背板连接器允许所述设备连接于一总体系统(诸如一网络服务器等)。
这些导电迹线因此形成作为母基板一部分的传输线且在芯片元件和连接器之间延伸,以提供一个或多个外部插头连接器和芯片元件之间的一连接。电路基板通常由一便宜的材料(公知的便宜的FR4)形成。虽然FR4便宜,但是熟知的是,FR4在以约6Gbps及更高的速率传输数据的高速信号传输线中将产生损耗。这些损耗随着速率增大而增加且由此使得FR4材料用于约10Gbps及更高的速率的高速数据传输应用是不令人满意的。这种衰减(dropoff)在约6Gbps开始(或者使用NRZ编码在3GHz开始)且随着数据速率增大而增加。为了在FR4中使用这种迹线,一设计者可能不得不采用放大器和均衡器,这增加了所述设备的最终成本。
用于电路基板的定制材料(诸如MEGATRON)可用于减少这样的损耗,但是这些材料的价格使得电路基板以及由此使用它们的电子设备的成本大幅增加。此外,当迹线用于形成信号传输线时,传输线的总体长度能超过阈值长度,此时在操作中出现问题。这些迹线的长度能接近10英寸及更长的长度,且可能包括能形成反射及噪声问题以及另外损耗的弯曲(bends)和转向(turns)。损耗有时能通过使用放大器、中继器以及均衡器来校正,但是这些元件增加了制造电路基板的成本。然而,这样做使得设计复杂化,因为需要另外的基板空间来收容这些放大器和中继器。另外,这样的传输线的迹线的路由可能要求多次转向。这些转向以及发生在端接点处的转变(transitions)影响由传输线传送的信号的完整性。这些定制的电路基板材料因此在频率10Ghz以上(above)比线缆传输线损耗更大。这随后变得难于以获得穿过传输线迹线的一致的阻抗和一低信号损耗的方式路由传输线迹线。
因此变得难以在电路基板和背板中充分地设计信号传输线,以满足用于高速应用所需的串扰和损耗要求。因此,某些人群会赏识一集成、高速、连接器接口芯片封装路由组件,其不在电路基板上采用迹线而为传输高速数据信号(20Gbps以上(above))提供传输线。
发明内容
一种路由组件具有一整体L形结构,其包括具有一前板的一框架以及一托盘,两者都可以由绝缘性的或者导电性的材料形成且前板竖直延伸而托盘水平延伸。框架还可包括设置在托盘一端的一对支撑臂。支撑臂可安装于前板且结构上支撑托盘。前板包括多个连接器端口以及设置于连接器端口中的多个第一连接器。线缆具有端接于多个第一连接器且延伸的第一端且在一路由结构中受托盘支撑。线缆的第二端从托盘延伸且端接于第二连接器。第二连接器设置成连接于一电路基板和/或芯片封装(或相邻的这种芯片封装)以基本上避免使用一电路基板来路由芯片封装和第一连接器之间的高速信号迹线。第一连接器、框架、线缆以及第二连接器集成到路由组件中作为一独立元件,从而该组件可作为一个部件容易地插入到所述电子设备中。
为了提供结构上的灵活性,托盘可设置在主设备的母基板的上方或者下方。托盘可包括与一芯片封装对齐的一开口。如果第二连接器是低高度式连接器,那么第二连接器之间连接且在芯片封装中支撑一处理器的结构可设置成基本上在开口中以最小化空间需求。
路由组件优选地采用各种双轴式线缆,用于将差分信号从芯片封装传输至连接器端口。线缆在其朝向芯片封装的范围内可以是自由的且通过夹子(clips)等方式固定于托盘,或者它们可埋设或者包裹(encase)在托盘的本体中(从托盘的一前端延伸至芯片收容开口(在此线缆的导体端接于将与对应相对的和芯片封装相关的连接器对接的连接器))。线缆埋设于托盘的本体保护双轴式线缆在组装期间免受破坏。
第二连接器可设置成具有垂直于托盘的一对接方向且可具有一即插即用特性,使得在成排的第二连接器上方安装就位成排的第二连接器。优选地第二连接器灵活地受托盘支撑,使得它们可被控制与母基板上和/或芯片封装上相对的连接器接合。
连接器端口的堆叠提供连接器端口的后方的一竖直空间,该竖直空间能收容一更大的可直接接触于芯片封装的传热元件,从而潜在地改善传热问题。当然,与常规结构相比,线缆的使用还减少损耗。另外,整体结构提供可容易地设置于一交换机或者服务器的一系统,从而改善安装。通过考虑以下详细说明将清楚地理解这些和其它的特征和优点。
附图说明
本发明通过举例示出但不限于附图,在附图中类似的附图标记表示类似的部件,且在附图中
图1是一现有技术电子设备的内部的一立体图,其中一芯片封装就位于一母基板上;
图1A是图1的电子设备的一示意剖面图,示出电路基板是如何用于路由设备的芯片封装和外部连接器接口之间的信号传输通道;
图2是一路由组件的一实施例的一立体图;
图2A是图2的路由组件的一示意剖面图,示出线缆如何能埋设在托盘中,以用于在组件的一芯片封装基板和外部连接器接口之间路由信号;
图3是一路由组件就位于一母板下方的一实施例的一立体图,而且其中芯片封装在其上具有一散热器;
图3A是图3所示的实施例的另一立体图;
图4是一路由组件的一实施例的一立体图,其中一开口形成在托盘上;
图4A是图4所示的开口的一放大图,其中一芯片封装设置于开口中;
图5是图2的路由组件的一俯视平面图,其中托盘的上表面的一部分移除,以示出在托盘内的路由的线缆;
图5A是图5的芯片封装开口的一放大立体图;
图5B是图5的路由组件的一立体图,其中芯片封装移除但托盘的顶部不移除;
图6是路由组件芯片封装开口的一放大图,示出第二连接器的排列和一对应的芯片封装;
图7是一路由组件就位在一母基板下方的一实施例的一立体图;
图8是图7所示的实施例的另一立体图;
图8A是图8所示的路由组件的一示意剖面图;
图8B是适合用于连接于一芯片封装的第二连接器的一实施例的一立体图;
图9是在位置上一母基板和芯片封装用于与一路由组件的一实施例对接的一侧视图;
图9A是图9所示的实施例的一侧视图,但是其中母基板位于托盘上和路由组件框架的侧支撑元件以虚线示出;
图10是一剖面示意图,示出当一托盘位于一母基板下方时,一路由组件的一实施例连接一芯片封装的;以及
图11是系统的一实施例的一立体图,该实施例具有路由经过一路由组件的一些连接器和路由经过一电路基板的其它连接器。
具体实施方式
下面的具体说明描述示范性实施例且不意欲限制于这些明确公开的组合。由此,除非另有说明,本文所公开的特征可以组合在一起,以形成出于简明目的未给出的另外的组合。
本发明因此涉及一集成路由组件,集成路由组件构造成以以一独立元件安装在一电子设备的壳体中且提供从一芯片或者处理器(ASIC或者FPGA型的)直接引导至一阵列的外部连接器的多个数据传输通道。传输通道采用线缆固定在路由组件中的形式,从而省去了通过在主设备的一母基板上的高速迹线的方式路由高速通道的需要。
图1示出一常规电子设备30(诸如一路由器、交换机等),其具有一金属板壳体31,金属板壳体31具有一前壁32以及一相对的后壁34。设备30在壳体内之处一母基板36,母基板36包括各种电子元件,诸如具有一相关处理器(associated processor)40的一芯片封装38、一电源42和另外的集成电路、连接器、电容器、电阻等。前壁32具有与第一连接器43对齐的一系列开口33,以限定用于设备30的连接器端口。典型地,如图1A所示,一阵列的第一连接器43安装于母基板36的前端且封闭在金属屏蔽罩体44或者适配器框架内,金属屏蔽罩体44或者适配器框架放置在连接器43上和母基板36上。同样地,一系列第二连接器46沿母基板36的后缘安装且与基座31的后壁上的开口对齐。
在图1的设备的公知结构中,芯片封装38通过从芯片封装接触件穿过母基板36延伸至两个连接器43、46的长的导电迹线47连接于第一连接器和第二连接器。成对的导电迹线47被要求为限定各差分信号传输线,且一第三导电迹线可用于提供跟随信号传输线的路径的一相关的接地。各条这样的信号传输线路由穿过母基板或者路由在母基板上且这种路由具有一定的缺点。FR4是通常用于电路基板的材料,但可惜的是,在5Ghz以上的频率时它产生的损耗不断增大。这些信号传输线迹线的转向、弯曲和交叉通常被要求,以在母基板上从芯片封装接触件到连接器路由传输线。迹线上的这些方向的变化会产生信号反射和噪声的问题以及另外的损耗。尽管损耗有时可通过使用放大器、中继器以及均衡器来纠正,但这些元件增加了最终电路(母)基板的制造成本以及增加了功率消耗(以及操作的成本)。这些元件的使用使电路基板的布局复杂化,因为需要另外的基板空间来收容这些放大器和中继器且这个另外的基板空间在设备的预期尺寸下可能得不到。用于电路基板的低损耗的定制材料是可使用的,但是这些材料的成本增加了电路基板以及由此采用电路基板的主设备(host devices)的成本。更进一步,长的电路迹线需要增加功率,以驱动流经电路迹线的高速信号,且如此,它们阻碍设计者开发“绿色”(节能)设备的尝试。
为了克服这些实际的缺点,我们开发了一种集成的路由组件50,组件50将一主设备51的外部连接器接口并入一独立(single)的组件中且以在连接器接口和芯片封装88(芯片封装88包括一处理器90且可包括一基板91)之间延伸的细长的线缆62的形式为高速差分对信号传输线提供一支持,省去了对母基板53上的高速路由迹线的需要。这一组件在图2中以50标出。如图2至图8B所示,组件50包括一前部,前部收容预定阵列的多个第一连接器55和第二连接器57及其相关的基座60,预定阵列以彼此竖直堆叠的四个水平排的连接器基座60示出。
连接器基座60限定连接器端口54、56形式的用于设备的外部连接器接口且各该连接器基座60包括优选插座式的一第一连接器55、57。在一些例子中,如图所示,连接器端口56可以沿主设备51的前部设置于基座60的I/O连接器端口,且连接器端口的位置和类型不意欲是限制,除非另有说明。
如能认识的是,多个连接器55、57可以以一集成方式排列成多个水平行排,如图2所示,其中通过延伸穿过形成于连接器基座60外表的凸台60a的紧固件(诸如螺丝),连接器基座60和相关的散热器61在支撑板58之间被保持在它们的水平位置(extent)且竖向对齐。这样一种排列能易于收容一面板70(图3),面板70在两个侧支撑部68之间沿宽度方向延伸且面板70和两个侧支撑部68配合形成一框架66。两个侧支撑部68具有向后延伸的槽道72a、72b,槽道72a、72b以一悬臂的方式帮助支撑一托盘75。框架66和托盘75限定一路由组件74。如图所示,路由组件74具有可以在内部受支撑并且可插入一基座的一大致L形结构。应注意的是,所示出的构造是基于采用经由一铸造结构形成的连接器基座60。可替代地,如已知的,连接器基座能由以一所需结构形成的板金属来形成,通常以多片交织(intertwined)在一起以形成所需结构。板金属与铸造形成一连接器基座是熟知的且无需在本文此进一步说明。
如图4所示,托盘75是大体平的且具有一预定的厚度并能由绝缘性或者导电性的材料形成。如能够认识到的,导电性的材料可提供另外的屏蔽且因此在某些应用中可能是需要。所示的托盘75具有形成在其中的一托盘开口76,如图所示地位于托盘75的外周内。托盘开口76如图所示地具有两个不同的形状且各开口具有一中央部78,中央部78在结构上可以是具有四个缘部80a-80d的正方形或者长方形或者它可具有如图4和图4A所示的一十字形结构,在十字形结构中,托盘开口76包括与开口中央部78连通且合并托盘开口76的四个缘部80a-80d的四个翼部79a-79d。当然,对于托盘75不延伸结果且因此完全包围芯片封装的各种形式(versions)而言,托盘开口76可以被托盘75或者仅托盘75的端部中的一凹口代替。
位于N乘M阵列(其中N和M均可为2或者更多)的连接器端口54、56中的连接器55、57未详细示出但可以是任何所需的具有设置成传送和接收通道结构的信号端子和接地端子的插座式,以与相对的具有一插头式的连接器对接。例如,SFP式连接器、QSFP式连接器和CFP式连接器只是许多可能的选择中的几个且连接器55、57不意欲限制于特定式的连接器。还应注意的是,如果需要,可以设置一单排连接器57。线缆62可在线缆62的第一端82直接端接于各连接器55、57的端子且如图4、图7和图8所示地相邻低速导线63(可用于逻辑、时钟、电源和其它电路)。线缆62优选地包括由一绝缘包覆层(dielectric covering)包覆的具有一所需的间隔的一对信号导体且可包括一相关的包围在一绝缘外皮中的加蔽导线和/或一外导电包覆层,以形成一传输线。线缆62随着线缆62从芯片封装88行进至连接器55、57帮助在线缆62的整个长度上保持信号导体的有序的几何形状(ordered geometry)。因为它们的整个长度的这种几何形状保持有序,所以线缆62可容易地在其路径上转向、弯曲或交叉而不会引起到传输线的信号反射或阻抗不连续的问题。
线缆62和低速导线63在它们的第一端82直接端接于连接器55、57。这使得取消与母基板53的一直接连接成为可能且允许一能容易堆叠同时依然提供能接受的气流并同时避免通常发生在一连接器-电路基板安装接口处的阻抗不连续的结构。线缆62示出为在连接器基座60的后部成排布置。线缆62如图8A、图9和图9A最佳所示地成排设置,下连接器基座排的线缆62和低速导线63布置在最高的连接器基座排的内侧。这有助于线缆62从连接器55、57到托盘75的有序布置。在所示的(在图9和图9A中)的组件50中,与上三排连接器55、57和连接器端口54、56相关的线缆62可看到具有向下延伸至托盘75的水平面且在托盘75的前端进入基板中的一大体S形结构,而在最下排的线缆几乎水平地延伸到托盘75中。
线缆62如图5所示地具有从连接器55,57朝向托盘75延伸的第一端82。线缆62的第二端84如图所示地延伸到托盘开口76中,在托盘开口76中,线缆62的第二端84端接于将与芯片封装88对接的连接器86。连接器86可设置成连接于安装在或相邻于一基板91的一连接器(例如下面讨论的插座式连接器95)或者可设置成直接压在基板91上(或者相邻基板的一支撑母基板)。线缆62的第二端84离开托盘75以进入托盘开口76。在一实施例中,芯片封装88设置在母基板53上,且芯片封装88包括插座式连接器95的形式的多个接触件,插座式连接器95优选地围绕芯片封装88的外周排列且与托盘开口76对准以允许在线缆第二端84处与连接器86对接。在另一方面,芯片封装88可以作为整个路由组件74的一部分而被包含(图2和图2A)。
应注意的是,托盘75可设置在电路基板的上方,诸如图4A至图6所示。或者,如图7至图10所示,托盘75可设置在母基板53的下方。在这种结构中,如图3和图3A所示,母基板53上方的区域自由地收容热传递元件93,热传递元件93可包括具有比处理器90大的外周的热扩散器和/或散热器,因为线缆62集成到托盘75中释放托盘75上方的大部分(如果不是全部)空间而用于其它用途。
线缆62(和低速导线63)可以各种从它们进入路由组件74的位置(诸如沿托盘75的一前端83)到它们离开托盘75且进入托盘开口76的位置将它们合适地保持就位的方式定位成托盘75的一部分。线缆62通过将线缆62包围在托盘75中而可收容在托盘75中。线缆62的本体部优选地完全被托盘75围绕,从而两者形成可设置于路由组件74中的一一体部分。线缆62的一个布线图案如图5所示,为了清楚起见,托盘75的上部移除,以示出线缆62铺设的路径。
在托盘75成形之前,线缆62可在其第二端84端接于前述的连接器86。因为线缆62的第一端直接端接于线缆连接器55、57的端子,所以第二连接器允许线缆62直接连接于芯片封装88,从而完全避免(bypassing)母基板53作为一路由支撑件。在托盘75位于母基板53的上方的情况下,多个连接器86设置在芯片封装88的周围且优选地沿托盘开口76的所述多个缘部布置。或者,如图7至图10所示,多个连接器86可设置成从下方与芯片封装88对接,应当理解的是,这种构型在某些情况下可能是优选的。
在这种情况下,路由组件74可插入到主设备基座中且母基板53在托盘75上方放置在主设备51的壳体中,其中它可以通过托脚(standoffs)92等从下方与母基板间隔开。图6示出连接器86和它们相关的基座87面向托盘开口76中的基板91以与基板91接触,以提供到处理器90(或者可代替地与支撑基板91的一母基板53接触,如图10所示)。当然,可为设置在母基板53下方的一托盘75提供一类似的结构。连接器基座87可以采用能只可容纳一对信号导体的多个芝克莱特(chiclets)的形式。如能够认识到的,连接器基座87可容易地与母基板53或者基板91上的插座式连接器95对接。另外,如果线缆62在位置上固定在托盘中从而在端接于连接器86之前线缆62只延伸出托盘75一短的距离,那么该结构也帮助确保连接器86与母基板或者芯片封装88(和任何对接的插座连接器)正确地对齐且可使组装对齐极其更容易。连接器86和对接的插座连接器可设置有一低高度以安装在托盘开口76中且潜在地不会突出托盘开口76外,因此最小化路由组件74的空间需求。如能够认识到的,线缆从至少两个方向延伸到开口中且优选地将从托盘的多个缘部延伸。
这种结构示意地示出在图8A和图10的剖开图中,其中基板连接器如图所示地接触延伸穿过母基板53以与基板91连接的导电性的过孔(vias)96。如能够认识到的,一BGA结构可将基板91安装于母基板53。能看到的是,线缆62的第二端84和它们对应的连接器86可收容在托盘开口76的空间(volume)中,以免过度增加主设备51的高度。如能够认识到的,所示出的连接器86具有一垂直于托盘的一对接方向。
图11示出本发明的一路由组件100的另一实施例,其中连接器端口102就位在母基板104上且连接器107如所需地沿一前部110设置。连接器端口102在它们的屏蔽罩体103中设置成两个水平排且就位在母基板104上,母基板104具有就位的一芯片封装106。路由组件100具有以一高度保持在框架中的两排连接器端口107,该高度允许将组件置于存在的连接器端口102上方且将路由组件100的线缆62的高速优势用于那组连接器端口。这个结构将允许经由线缆的连接于一电路基板的连接器端口和连接于一芯片封装的连接器端口的一组合,从而在系统架构中提供灵活性。同时所示出的实施例示出包括两排安装于电路基板的连接器端口和两排由路由组件提供的连接器端口的一系统,替代实施例可以使各类端口为一排或可以改变排数,这取决于系统需要。
在此提供的说明书借助其优选且示例性的实施例说明了各个特征。本领域普通技术人员通过阅读本说明书,将可在随附权利要求的范围和精神内做出许多其它的实施例、修改和变形。
Claims (15)
1.一种路由组件,包括:
一框架,具有限定一N乘M阵列的多个端口的一前面,其中N和M均至少为2;
一托盘,从所述框架延伸;
多个第一连接器,设置于所述多个端口中;
多根线缆,具有连接于所述多个第一连接器的第一端以及从所述托盘延伸的第二端,所述多根线缆的一部分以一预定结构延伸穿过所述托盘,其中所述多根线缆中的至少一些在所述托盘内弯曲;以及
多个第二连接器,安装于多个所述第二端,所述第二连接器具有与所述托盘垂直的一对接方向,其中所述多根线缆设置成允许信号在所述多个第一连接器和所述多个第二连接器之间通过同时绕过一电路基板。
2.如权利要求1所述的路由组件,其中,所述框架包括支撑所述托盘的侧支撑部。
3.如权利要求2所述的路由组件,其中,所述托盘由一导电性的材料形成。
4.如权利要求1所述的路由组件,其中,所述多根线缆以一预定结构能被固定地埋设在所述托盘中。
5.如权利要求1所述的路由组件,其中,所述N乘M阵列设置至少两排连接器,且从其中一排连接器延伸的线缆在进入所述托盘之前延伸一距离。
6.如权利要求5所述的路由组件,其中,所述框架设置至少三排连接器。
7.一种路由组件,包括:
一框架,具有限定一N乘M阵列的多个端口的一前面,其中N和M均至少为2;
一托盘,从所述框架延伸;
多个第一连接器,设置于所述多个端口中;
多根线缆,具有连接于所述多个第一连接器的第一端以及从所述托盘延伸的第二端,所述多根线缆的一部分以一预定结构延伸穿过所述托盘;以及
多个第二连接器,安装于多个所述第二端,所述第二连接器具有与所述托盘垂直的一对接方向,其中所述多根线缆设置成允许信号在所述多个第一连接器和所述多个第二连接器之间通过同时绕过一电路基板;
其中,所述托盘包括一内部的开口且所述线缆从至少两个不同的方向延伸到所述开口中。
8.如权利要求7所述的路由组件,其中,所述多个第二连接器设置成以所述开口的两个不同侧上的两排对接。
9.一种使用路由组件的系统,包括:
一箱体,具有一前侧;
一母基板,设置于所述箱体,所述母基板支撑一芯片封装;
一路由组件,设置于所述箱体中,所述路由组件包括限定一第一排的连接器端口的一前面,所述前面设置在所述前侧,所述路由组件包括从所述前面延伸的一托盘,所述托盘具有靠近所述芯片封装的缘部;
多个第一连接器,设置于多个所述连接器端口中;
多根线缆,埋设于所述托盘中,所述多根线缆各具有端接于所述多个第一连接器其中之一的一第一端以及延伸通过所述缘部的一第二端;
多个第二连接器,与所述芯片封装和所述缘部相邻,所述第二连接器电连接于所述芯片封装;以及
多个第三连接器,端接于所述第二端且与所述芯片封装相邻设置,所述第三连接器对接于所述第二连接器以提供在所述第一连接器和所述第二连接器之间的一信号路径,这避免行进通过所述母基板。
10.如权利要求9所述的系统,其中,所述托盘以一悬臂的方式从所述前面延伸。
11.如权利要求9所述的系统,其中,所述托盘设置在所述母基板下方。
12.如权利要求9所述的系统,其中,所述托盘设置在所述母基板上方。
13.如权利要求9所述的系统,其中,所述母基板支撑具有设置在其中的多个第四连接器的一第二排的连接器端口,所述第四连接器电连接于所述母基板,其中,所述第一连接器经由所述线缆与所述芯片封装通信且所述第四连接器经由所述母基板中的迹线通信。
14.如权利要求9所述的系统,其中,所述多根线缆以将所述多个第三连接器定位在所述芯片封装的两侧的一预设的布局设置。
15.如权利要求9所述的系统,其中,所述托盘由一导电性的材料形成。
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TW201732493A (zh) | 2017-09-16 |
US20180309214A1 (en) | 2018-10-25 |
JP6821746B2 (ja) | 2021-01-27 |
US11108176B2 (en) | 2021-08-31 |
JP2019504417A (ja) | 2019-02-14 |
WO2017123574A1 (en) | 2017-07-20 |
JP6549327B2 (ja) | 2019-07-24 |
CN108713355A (zh) | 2018-10-26 |
US20190319380A1 (en) | 2019-10-17 |
US11688960B2 (en) | 2023-06-27 |
US20210359438A1 (en) | 2021-11-18 |
JP2020009433A (ja) | 2020-01-16 |
US20200403335A1 (en) | 2020-12-24 |
KR20180094119A (ko) | 2018-08-22 |
KR102092627B1 (ko) | 2020-03-24 |
TWI648613B (zh) | 2019-01-21 |
US10424856B2 (en) | 2019-09-24 |
US10797416B2 (en) | 2020-10-06 |
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