CN107112213A - 在低温下生长薄外延膜的方法 - Google Patents

在低温下生长薄外延膜的方法 Download PDF

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CN107112213A
CN107112213A CN201580054090.5A CN201580054090A CN107112213A CN 107112213 A CN107112213 A CN 107112213A CN 201580054090 A CN201580054090 A CN 201580054090A CN 107112213 A CN107112213 A CN 107112213A
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precursor gas
silane
epitaxial film
seconds
facet
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CN107112213B (zh
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阿布舍克·杜贝
仲华
王振宇
李学斌
黄奕樵
舒伯特·S·楚
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Applied Materials Inc
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Abstract

本公开内容的实现方式一般地涉及外延膜上的硅材料的外延生长的方法。在一个实现方式中，该方法包括于半导体鳍片(fin)之上形成外延膜，其中外延膜包括具有第一刻面与第二刻面的顶表面，以及通过在约375℃至约450℃的温度与约5Torr至约20Torr的腔室压力处将顶表面交替暴露于第一前驱物气体与第二前驱物气体而至少在外延膜的顶表面上形成外延层，第一前驱物气体包含一或多个硅烷，第二前驱物气体包含一或多个氯化硅烷。

Description

在低温下生长薄外延膜的方法
技术领域
本公开内容的实现方式大体上涉及半导体制造工艺与器件的领域，尤其是，涉及用于硅材料在外延膜上外延生长的方法。
背景技术
随着对于下一代器件的电路密度增加，互连件(诸如穿孔、沟槽、接触件、栅极结构与其他特征)的宽度以及于互连件之间的介电材料减小至22nm或更小的尺寸，但是介电层的厚度保持实质不变，而有特征的深宽比(aspect ratio)增加的结果。近来，互补式金属氧化物半导体(CMOS)FinFET器件已经广泛地用于许多逻辑与其他应用中并整合入半导体器件的各式不同类型。
FinFET器件通常包括带有高深宽比的半导体鳍片(fin)，其中用于晶体管的通道与源极/漏极区域于半导体鳍片上形成。利用通道与源极/漏极区域的增加的表面积的优势而接着于鳍片(fin)器件的部分的侧面之上且沿着鳍片器件的部分的侧面形成而产生更快、更可靠的且更好控制的半导体晶体管器件。FinFETs的进一步优势包括减少短通道效应以及提供更高的电流流动。
为了改善晶体管性能，应力源(stressor)材料可填充源极/漏极区域，且该应力源材料可通过外延而于源极/漏极区域中生长。外延膜由{111}平面刻面(facet)且沿着晶体管通道方向而具有金刚石形状。随着晶体管的缩减，对于形成FinFET的改善方法总是有所需求。
发明内容
本公开内容的实现方式一般地涉及用于硅材料在外延膜上外延生长的方法。在一个实现方式中，该方法包括于半导体鳍片之上形成外延膜，该半导体鳍片在该基板上形成，其中外延膜包含具有第一刻面与第二刻面的顶表面，以及通过在约375℃至约450℃的温度与约5Torr至约20Torr的腔室压力处将顶表面交替暴露于第一前驱物气体与第二前驱物气体而至少在外延膜的顶表面上形成外延层，该第一前驱物气体包含一或多个硅烷，该第二前驱物气体包含一或多个氯化硅烷。
在另一个实现方式中，该方法包括将半导体结构装载入处理腔室中，其中半导体结构包含基板、于基板上形成的多个半导体鳍片以及设置于基板上的半导体鳍片之间的介电材料，于多个半导体鳍片上形成外延膜，其中各外延膜包括具有第一刻面与第二刻面的顶表面，及通过在小于约450℃的温度与约5Torr至约20Torr的腔室压力处将顶表面交替暴露于第一前驱物气体与第二前驱物气体而在外延膜的顶表面上形成硅层，该第一前驱物气体包含一或多个硅烷，该第二前驱物气体包含一或多个氯化硅烷。
在又另一个实现方式中，该方法包括(a)于半导体鳍片之上形成外延膜，该半导体鳍片于该基板上形成，其中各外延膜包括具有第一刻面与第二刻面的顶表面，(b)在小于约450℃温度与约5Torr至约20Torr的腔室压力处将外延膜暴露于第一前驱物气体，该第一前驱物气体包含硅烷(SiH4)或乙硅烷(Si2H6)，(c)在(b)步骤之后，用脉冲输送(pulse)第一前驱物气体第一周期时间，(d)在(c)步骤之后，将净化气体引入处理腔室中，(e)在(d)步骤之后，在小于约450℃的温度与约5Torr至约20Torr的腔室压力处将外延膜暴露于第二前驱物气体，该第二前驱物气体包含一或多个氯化硅烷，(f)在(e)步骤之后，用脉冲输送第一前驱物气体第二周期时间，以及(g)在(f)步骤之后，将净化气体引入处理腔室中。在各式实施例中，该方法进一步包括重复(b)至(g)步骤约10个循环或300个循环直至所需的硅层厚度生长于外延膜的顶表面上。
附图说明
以上简要概述的本公开内容的上述详述特征能够被详细理解的方式，以及实施方式的更特定描述，可以参考实现方式而获得，实现方式中的一些实现方式绘示于附图中。然而，值得注意的是，附图只绘示了本公开内容的典型实现方式，因而不应视为对本发明范围的限制，因为本公开内容可允许其他等同有效的实现方式。
图1是根据本公开内容的实现方式的用于制造半导体结构的示例性方法的流程图。
图2A至2C图示在根据图1的流程图的制造某些阶段期间简化的半导体结构的截面图。
为了便于理解，尽可能地，使用相同的附图标号指示附图中共通的元件。考虑到，一个实现方式中公开的元件在没有特定描述下可有益地用于其它实现方式中。
具体实施方式
图1为根据本公开内容的实现方式的用于制造半导体结构的示例性方法的流程图。图2A至2C图示在根据图1的流程图的制造某些阶段期间简化的半导体结构的截面图。本领域技术人员将进一步了解用于形成半导体器件与相关结构的全部处理过程未绘示于附图中或于此发明中描述。反之，为求简单清楚，只绘示与描述了对于本公开内容独特或对于了解本公开内容必要的用于形成半导体器件与相关结构的某些处理过程。此外，虽然各式步骤绘示于附图中及描述于本说明书中，但是没有暗示对这些步骤的顺序或中间步骤存在与否有所限制。除非明确指示，否则所绘示与描述的步骤仅用作解释用途依序绘示与描述，如果没完全实施的话，不排除个别的步骤实际上以同时或重叠的方式至少部分地施行的可能性。
方法100在方块102通过将半导体结构200装载入处理腔室而开始。半导体结构200包括基板202、多个半导体鳍片203(只显示了两个)以及设置于基板202上的半导体鳍片203之间的介电材料206，如图2A所示。处理腔室可为ALE(原子层外延)或ALD(原子层沉积)、CVD(化学气相沉积)或等离子体辅助处理技术领域中公知的任何适合的沉积处理腔室。
本说明书所用术语“基板”意欲广泛涵盖可以在处理腔室中处理的任何物件。例如，基板202可为能够具有材料沉积于基板上的任何基板，诸如硅基板，例如硅(掺杂的或未掺杂的)、结晶硅(例如Si<100>或Si<111>)、氧化硅、应变硅、掺杂或未掺杂的多晶硅或类似物，锗、III-V族化合物的基板，硅锗(SiGe)基板，碳化硅锗(SiGeC)基板，氧化硅锗(SiGeO)基板，氮氧化硅锗(SiGeON)基板，碳化硅(SiC)基板，碳氮化硅(SiCN)基板，碳氧化硅(SiCO)，外延基板，硅上绝缘体(SOI)基板，碳掺杂氧化物，氮化硅，例如液晶显示器(LCD)的显示基板，等离子体显示器，电致发光(EL)灯显示器，太阳能阵列，太阳能板，发光二极管(LED)基板，图案化或非图案化的半导体晶片，玻璃，蓝宝石，或任何其它材料，例如金属、金属合金和其它导电材料。基板202可为平坦基板或图案化基板。图案化基板包括在基板的处理表面中或上形成的电子特征的基板。基板202可包括多个层或包括例如部分制造的器件，诸如晶体管、快闪存储器件及其类似物)。
在一个实现方式中，基板202为单晶体硅，诸如P掺杂硅。半导体鳍片203可包括与基板202相同或不同的材料。在所示实现方式中，半导体鳍片203与基板202由相同材料形成。介电材料206可形成隔离区域，例如浅沟槽隔离(STI)区域，且可包括SiO、SiN、SiCN或任何适合的介电材料。
半导体鳍片203可实施在用于较后面阶段中的FinFET晶体管的形成通道中。各半导体鳍片203可包括第一部分204与第二部分205，第一部分204具有与介电材料206的表面209共面的表面207，第二部分205自第一部分204向上突出。第二部分205可作为源极或漏极区域的功能。因此，半导体结构200的顶表面包括一或多个半导体区域(即半导体鳍片203的第一部分204和/或第二部分205)以及一或多个介电区域(即介电材料206)。
在方块104，外延应力源膜214、215于第二部分205(即源极/漏极区域)上的各半导体鳍片203上生长以改善晶体管性能。外延应力源膜214、215可为源极或漏极区域的部分。外延应力源膜214、215可密封或覆盖半导体鳍片203的第二部分205所暴露的表面，如图2A所示。或者，半导体鳍片203的第二部分205可被移除且外延应力源膜214、215可于半导体鳍片203的第一部分204上形成。
外延应力源膜214、215可包括Si:P、SiGe、SiGe:B、Si:CP或其他合适的半导体材料。在一个实现方式中，外延应力源膜214、215包括SiGe材料。在某些应用中，其中需要高浓度的锗，例如用于导电节点先进7nm及更进一步中使用的pMOS源极与漏极材料，在硅中的锗的浓度可在约30％之上，例如约45％或更多，举例而言，约70％至约100％。
外延应力源膜214、215可使用选择性沉积处理形成，而使得外延应力源膜214、215于半导体鳍片203上生长而不是在介电材料206上生长。生成的外延应力源膜214可具有单晶体结构。可通过将蚀刻剂与前驱物气体共同流入沉积腔室而达成选择性沉积处理。蚀刻剂的实施例可为HCl、Cl2或任何适合的卤素气体。前驱物气体可包括任何适合的含硅气体，如硅烷、乙硅烷、有机硅烷或卤化硅烷，以及任何合适的含锗气体，如锗烷。
外延应力源膜214、215可于半导体鳍片203上外延生长，且由于在不同表面平面上的不同生长速率，刻面经形成以导致当沿着晶体管通道方向(该通道沿着半导体鳍片203的顶与相对侧壁延伸)观察刻面时，外延应力源膜214、215具有金刚石形状。外延应力源膜214、215由{111}平面刻面、固定在顶角落与侧壁角落处。例如，外延应力源膜214可包括多个刻面216、218、220、222(为求清楚，半导体鳍片203中只有一个标示于图2A中)。刻面216、218可接触半导体鳍片203。刻面216与刻面220可互相接触，且角(corner)224可在接触点处形成。刻面218与刻面222可互相接触，且角226可在接触点处形成。刻面220与刻面222可互相接触，且角228可在接触点处形成。
在方块106，外延应力源膜214、215的部分可选择性地在侧向维度上移除。具体言之，外延应力源膜214的相对侧上的部分经移除以增加半导体鳍片上的外延应力源膜214与邻近半导体鳍片上生长的外延应力源膜215之间的距离。接触点处的角228的部分可选择性地被移除，如图2B所示。随着晶体管缩减，鳍片间距(fin pitch，两邻近鳍片之间的距离)变得更小。因此，源极/漏极上生长的外延应力源膜可以被碰触(touched)或合并(merged)。一旦合并产生，(晶体管通道上的应变上的)应力源的效应减小且缺陷容易在合并区域的连接点处形成，这对半导体结构的性能以及晶体管性能有负面影响。由于邻近外延膜之间的距离增加，而防止外延应力源膜214与邻近应力源膜215互相碰触或合并。可通过蚀刻、研磨或其他适合的移除处理而达成外延应力源膜的部分的选择性移除。蚀刻处理可在用于沉积的相同腔室中实施，或在分开但整合的腔室中实施。
在方块108，硅帽层217、219保形地(conformally)于外延应力源膜214、215上分别形成以钝化外延应力源膜214、215，使得例如栅极介电的后续的层可以轻易地于半导体鳍片203的部分之上形成，栅极介电，诸如二氧化硅、掺杂碳的硅氧化物、硅锗氧化物、或高k介电材料。硅帽层可在应力源膜214、215的至少顶表面(即刻面220、222)上形成。硅帽层217、219可通过化学气相沉积(CVD)工艺、原子层外延(ALE)或原子层沉积(ALD)工艺而生长。在一个实现方式中，硅帽层217、219由ALE工艺形成。ALE是一种周期性沉积工艺，它运用化学吸附(chemisorption)技术以将前驱物分子依顺序周期传送于加热的基板表面上。在各式实现方式中，外延应力源膜214、215依序暴露于第一前驱物气体、净化气体、第二前驱物气体与净化气体。第一与第二前驱物气体反应以于外延应力源膜214、215的表面上形成作为膜的化学化合物。重复此周期以一层一层的方式生长硅帽层217、219直到所需的厚度达到。在一个实现方式中，其中下面的SiGe外延应力源膜214、215为约3-6nm厚度，硅帽层217、219可具有约1nm至约5nm的厚度，例如约2nm至约3nm。硅帽层的沉积可于相同腔室中实施以用于沉积外延应力源膜214、215，或是在分开但整合的腔室中实施。
在各式实现方式中，第一前驱物气体与第二前驱物气体可为含硅气体。适合的含硅气体可包括硅烷、卤化硅烷或有机硅烷中的一或多个。硅烷可包括硅烷(SiH4)与带有经验方程式SixH(2x+2)的更高阶的硅烷(higher silanes)，例如乙硅烷(Si2H6)、丙硅烷(Si3H8)与四硅烷(Si4H10)，或其他更高阶的硅烷，如聚氯硅烷。卤化硅烷可包括带有经验化学式的化合物X’ySixH(2x+2-y)，其中X’＝F,Cl,Br或I，例如六氯二硅烷(Si2Cl6)、四氯硅烷(SiCl4)、二氯硅烷(Cl2SiH2)与三氯硅烷(Cl3SiH)。有机硅烷可包括带有经验化学式RySixH(2x+2-y)的化合物，其中R＝甲基、乙基、丙基或丁基，例如甲基硅烷((CH3)SiH3)、二甲基硅烷(CH3)2SiH2)、乙基硅烷(CH3CH2)SiH3)、甲基二硅烷(CH3)Si2H5)、二甲基二硅烷((CH3)2Si2H4)与六甲基二硅烷((CH3)6Si2)。合适的含锗气体可包括但不限于锗烷(GeH4)、二锗烷(Ge2H6)、三锗烷(Ge3H8)或以上两个或更多个的组合。在某些实现方式中，四乙氧基硅烷(TEOS)亦可用作第一或第二前驱物气体。
在一个示例的实现方式中，第一前驱物气体为硅基前驱物气体，诸如硅烷(SiH4)与带有经验化学式SixH(2x+2)的更高阶的硅烷如乙硅烷(Si2H6)、丙硅烷(Si3H8)或四硅烷(Si4H10)。如需要的话，第一前驱物气体可包括本发明所述的硅基前驱物气体中的一或多个。第二前驱物气体为卤化硅烷，例如氯化硅烷，如一氯硅烷(SiH3Cl,MCS)、二氯硅烷(Si2H2Cl2,DCS)、三氯硅烷(SiHCl3,TCS)、六氯二硅烷(Si2Cl6,HCDS)、八氯三硅烷(Si3Cl8,OCTS)或四氯化硅(STC)。如需要的话，第二前驱物气体可包括本发明所述的卤化硅烷中的一或多个。合适的净化气体可包括氦、氩、氮、氢、形成气体或以上各者的组合。
在使用ALE工艺的一个示例性实施例中，第一前驱物气体为乙硅烷而第二前驱物气体系HCDS。ALE工艺在约350℃至约550℃的温度范围(诸如375℃至约450℃，举例而言，约425℃)以及约1Torr至约40Torr(诸如约5Torr至约20Torr，举例而言，约10Torr)腔室压力处实施。在下面外延应力源膜214、215于硅中具有高浓度Ge(例如30％或以上，举例而言，40％或以上)的情况下，使用较低沉积温度(例如约425℃或更低，举例而言，350℃至约375℃)可我有优势的，以避免外延应力源膜的变形。
在操作中，外延应力源膜214、215暴露于使用乙硅烷的第一前驱物气体。第一前驱物气体以约5sccm至约35sccm范围的流动速率被引入处理腔室中，例如约10sccm至约25sccm，举例而言，约20sccm。接着用脉冲输送(pulse)第一前驱物气体约5秒至约25秒，如约15秒。下一步，净化气体以约5sccm至约25sccm范围的流动速率被引入处理腔室中，例如约10sccm至约20sccm，举例而言，约15sccm。下一步，外延应力源膜214、215暴露于使用HCDS的第二前驱物气体。第二前驱物气体以约250sccm至约550sccm范围的流动速率被引入处理腔室中，例如约350sccm至约450sccm，举例而言，约400sccm。第二前驱物气体稀释于氮气或氢气载体气体中，氮气或氢气载体气体以约1SLM至约30SLM的流动速率流动入处理腔室中，例如约3SLM。接着用脉冲输送(pulse)第二前驱物气体约5秒至约25秒，例如约15秒。之后，净化气体以约5sccm至约25sccm范围的流动速率被引入处理腔室中，例如约10sccm至约20sccm，举例而言，约15sccm。通过上述工艺状况交替乙硅烷与HCDS而将硅帽层保形地且均匀地生长于外延应力源膜上。加入六氯二硅烷(Si2Cl6,HCDS)而在表面处将-H配位基(ligand)换成Cl终端(termination)并在其上形成额外的硅层。此处理过程以约/周期的生长速率重复约300个周期以达到所需的厚度。
在使用ALE工艺的另一个示例实施例中，第一前驱物气体仍为乙硅烷而第二前驱物气体仍为HCDS。然而，调整为较长的脉冲时间(pulse time)。在此实施例中，ALE工艺在约350℃至约550℃的温度范围(例如约375℃至约450℃，举例而言，约425℃)以及约1Torr至约40Torr(例如约5Torr至约20Torr，举例而言，约10Torr)的腔室压力处实施。在下面的外延应力源膜214、215于硅中具有高浓度Ge(例如30％或以上，举例而言，40％或以上)的情况下，使用较低沉积温度(例如约425℃或更低，举例而言，350℃至约375℃)可为有优势的，以避免外延应力源膜的变形。
在操作中，外延应力源膜214、215暴露于使用乙硅烷的第一前驱物气体。第一前驱物气体以约5sccm至约35sccm范围的流动速率被引入处理腔室中，例如约10sccm至约25sccm，举例而言，约20sccm。接着用脉冲输送(pulse)第一前驱物气体约350秒至约550秒，例如约450秒。下一步，净化气体以约5sccm至约25sccm范围的流动速率被引入处理腔室中，例如约10sccm至约20sccm，举例而言，约15sccm。下一步，外延应力源膜214、215暴露于使用HCDS的第二前驱物气体。第二前驱物气体以约250sccm至约550sccm范围的流动速率被引入处理腔室中，例如约350sccm至约450sccm，举例而言，约400sccm。第二前驱物气体稀释于氮气或氢气载体气体中，氮气或氢气载体气体以约1SLM至约30SLM的流动速率流动入处理腔室中，例如约3SLM。接着用脉冲输送(pulse)第二前驱物气体约350秒至约550秒，例如约450秒。之后，净化气体以约5sccm至约25sccm范围的流动速率被引入处理腔室中，例如约10sccm至约20sccm，举例而言，约15sccm。通过上述工艺状况交替乙硅烷与HCDS而将单层的硅保形地且均匀地生长于外延应力源膜上。此处理过程以约/周期的生长速率重复约10个周期以达到所需的厚度。
在使用ALE工艺的又另一个示例实施例中，第一前驱物气体为硅烷而第二前驱物气体为HCDS。因为硅烷在半导体鳍片203的侧壁上显示有较少的侧向膜生长，所以观察到硅烷在某些应用中是有优势的。在此示例实施例中，ALE工艺在约350℃至约550℃的温度范围(例如375℃至约450℃，举例而言，约425℃)以及约1Torr至约40Torr(例如约5Torr至约20Torr，举例而言，约10Torr)的腔室压力处实施。在下面外延应力源膜214、215于硅中具有高浓度Ge(例如30％或以上，举例而言，40％或以上)的情况下，使用较低沉积温度(例如约425℃或更低，举例而言，350℃至约375℃)可为有优势的，以避免外延应力源膜的变形。
在操作中，外延应力源膜214、215暴露于使用硅烷的第一前驱物气体。第一前驱物气体以约25sccm至约55sccm范围的流动速率被引入处理腔室中，例如约30sccm至约45sccm，举例而言，约40sccm。接着用脉冲输送(pulse)第一前驱物气体约650秒至约1200秒，例如约900秒。下一步，净化气体以约5sccm至约25sccm范围的流动速率被引入处理腔室中，例如约10sccm至约20sccm，举例而言，约15sccm。下一步，外延应力源膜214、215暴露于使用HCDS的第二前驱物气体。第二前驱物气体以约250sccm至约550sccm范围的流动速率被引入处理腔室中，例如约350sccm至约450sccm，举例而言，约400sccm。第二前驱物气体稀释于氮气或氢气载体气体中，氮气或氢气载体气体以约1SLM至约30SLM的流动速率流动入处理腔室中，例如约3SLM。接着用脉冲输送(pulse)第二前驱物气体约350秒至约550秒，例如约450秒。之后，净化气体以约5sccm至约25sccm范围的流动速率被引入处理腔室中，例如约10sccm至约20sccm，举例而言，约15sccm。通过上述工艺状况交替硅烷与HCDS而将单层的硅保形地且均匀地生长于外延应力源膜上。此处理过程以约/周期的生长速率重复约10个周期以达到所需的厚度。
在硅帽层217、219以所需的厚度生长于外延应力源膜214、215上后，栅极介电层(未图示)可于硅帽层217、219上形成。栅极电极接着于半导体鳍片203的部分上且沿着半导体鳍片203的部分的侧面形成以形成FinFET的一般结构。
本公开内容的实现方式中所述的概念亦适用于其他外延材料。某些实施例可包括Si:CP、纯Ge、GeSn、GeP、GeB或GeSnB等，可用于逻辑与存储器的应用。在这些情况中，可能的硅前驱物可包括如上所述的卤化硅化合物与选择性的含硅化合物，而可能的锗前驱物可包括如上所述的卤化锗化合物与选择性的含锗化合物。例如，如果硅锗用作为帽层，可通过将外延应力源膜交替暴露于第一前驱物气体与第二前驱物气体而达到硅锗的外延生长，第一前驱物气体包括本公开内容中所述的含硅气体中的一或多个，第二前驱物气体包括卤化锗气体中的一或多个，卤化锗气体诸如氯化锗烷气体、含锗气体或含硅气体。净化气体与任何所需的掺杂气体可依以上相对于硅帽层所述的方式引入处理腔室中。在一个示例性实现方式中，第一前驱物气体可为硅烷或乙硅烷，而第二前驱物气体可为氯化锗烷气体，如四氯化锗(GeCl4)、二氯锗烷(GeH2Cl2)或锗烷(GeH4)。
本公开内容的好处包括通过使用第一前驱物气体与第二前驱物气体的原子层外延(ALE)而于SiGe外延应力源层上直接生长薄硅帽层，第一前驱物气体包括硅烷，第二前驱物气体包括氯化硅烷。已经观察到通过交替硅烷或乙硅烷与HCDS可以在较低生长温度达到硅帽层于包含SiGe的外延应力源膜上的生长。具体言之，因为通过使用自我限制一层一层的方式(self-limiting layer-by-layer fashion)的ALE工艺生长硅帽层，所以硅帽层可以均匀且保形地生长于外延应力源膜而不失电介质(例如硅氧化物与硅氮化物)生长的选择性。使用硅烷与氯化硅烷的硅外延生长以钝化应力源膜而允许后续栅极电介质有更好的生长，而使得用于FinFET的外延材料有更好的整合与表面形状控制(surfacemorphology)。
虽然前述针对本公开内容的实现方式，但在不背离本发明基本范围下，可设计本公开内容的其他的与进一步的实现方式，而本发明范围由以下权利要求来确定。

Claims (20)

1.一种在处理腔室中处理基板的方法，包括以下步骤：
于半导体鳍片之上形成外延膜，所述半导体鳍片在所述基板上形成，其中所述外延膜包含具有第一刻面与第二刻面的顶表面；及
通过在约550℃或小于550℃的温度与约5Torr至约20Torr的腔室压力处将所述顶表面交替暴露于第一前驱物气体与一第二前驱物气体而至少在所述外延膜的所述顶表面上形成外延层，所述第一前驱物气体包含一或多个硅烷，所述第二前驱物气体包含一或多个氯化硅烷。
2.如权利要求1所述的方法，其中所述第一前驱物气体包括硅烷(SiH4)、乙硅烷(Si2H6)、丙硅烷(Si3H8)、四硅烷(Si4H10)或四乙氧基硅烷(TEOS)。
3.如权利要求1所述的方法，其中所述第二前驱物气体包括一氯硅烷(SiH3Cl)、二氯硅烷(Si2H2Cl2)、三氯硅烷(SiHCl3)、六氯二硅烷(Si2Cl6)、八氯三硅烷(Si3Cl8)或四氯化硅(STC)。
4.如权利要求1所述的方法，进一步包括以下步骤：
将净化气体引入所述第一前驱物气体的流动与所述第二前驱物气体的流动之间的所述处理腔室中。
5.一种处理基板的方法，包括以下步骤：
将半导体结构装载入处理腔室中，其中所述半导体结构包含基板、于所述基板上形成的多个半导体鳍片以及设置于所述基板上的所述半导体鳍片之间的介电材料；
于所述多个半导体鳍片之上形成外延膜，其中各外延膜包括具有第一刻面与第二刻面的顶表面；以及
通过在小于约550℃的温度与约5Torr至约20Torr的腔室压力处将所述顶表面交替暴露于第一前驱物气体与第二前驱物气体而在所述外延膜的所述顶表面上形成硅层，所述第一前驱物气体包含一或多个硅烷，所述第二前驱物气体包含一或多个氯化硅烷。
6.如权利要求5所述的方法，其中所述第一前驱物气体包括硅烷(SiH4)、乙硅烷(Si2H6)、丙硅烷(Si3H8)或四硅烷(Si4H10)。
7.如权利要求6所述的方法，其中所述第一前驱物气体包括硅烷(SiH4)。
8.如权利要求6所述的方法，其中所述第一前驱物气体包括乙硅烷(Si2H6)。
9.如权利要求5所述的方法，其中所述第二前驱物气体包括一氯硅烷(SiH3Cl)、二氯硅烷(Si2H2Cl2)、三氯硅烷(SiHCl3)、六氯二硅烷(Si2Cl6)、八氯三硅烷(Si3Cl8)或四氯化硅(STC)。
10.如权利要求9所述的方法，其中所述第二前驱物气体包括六氯二硅烷(Si2Cl6)。
11.如权利要求5所述的方法，其中所述基板与所述半导体鳍片包括单晶硅。
12.如权利要求5所述的方法，进一步包含以下步骤：在所述外延膜的所述顶表面上形成硅层之前，在侧向方向上移除所述外延膜的部分。
13.如权利要求12所述的方法，其中所述外延膜进一步包括接触所述第一刻面与所述半导体鳍片的第三刻面以及接触所述第二刻面与所述半导体鳍片的第四刻面，及其中在所述侧向方向上移除所述外延膜的部分的所述步骤包括移除所述第一、第二、第三与第四刻面的一部分。
14.如权利要求5所述的方法，进一步包括以下步骤：
将净化气体引入所述第一前驱物气体的流动与所述第二前驱物气体的流动之间的所述处理腔室中。
15.如权利要求14所述的方法，进一步包括以下步骤：
在将所述顶表面暴露于第一前驱物气体之后且在将所述净化气体引入所述处理腔室之前，用脉冲输送(pulse)所述第一前驱物气体约5秒至约25秒。
16.如权利要求14所述的方法，进一步包括以下步骤：
在将所述顶表面暴露于第二前驱物气体之后且在将所述净化气体引入所述处理腔室之前，用脉冲输送(pulse)所述第二前驱物气体约350秒至约550秒。
17.一种在处理腔室中处理基板的方法，包括以下步骤：
(a)于半导体鳍片之上形成外延膜，所述半导体鳍片于所述基板上形成，其中各外延膜包括具有第一刻面与第二刻面的顶表面；
(b)在约350℃至约550℃的温度与约5Torr至约20Torr的腔室压力处将所述外延膜暴露于第一前驱物气体，所述第一前驱物气体包含硅烷(SiH4)或乙硅烷(Si2H6)；
(c)在(b)步骤之后，用脉冲输送所述第一前驱物气体第一周期时间；
(d)在(c)步骤之后，将净化气体引入所述处理腔室中；
(e)在(d)步骤之后，在小于约450℃的温度与约5Torr至约20Torr的腔室压力处将所述外延膜暴露于第二前驱物气体，所述第二前驱物气体包含氯化硅烷；
(f)在(e)步骤之后，用脉冲输送所述第一前驱物气体第二周期时间；以及
(g)在(f)步骤之后，将所述净化气体引入所述处理腔室中。
18.如权利要求17所述的方法，其中所述第二前驱物气体包括六氯二硅烷(Si2Cl6)。
19.如权利要求17所述的方法，其中所述第一周期时间为约5秒至约25秒或约350秒至约550秒，及所述第二周期时间为约5秒至约25秒或约350秒至约550秒。
20.如权利要求17所述的方法，进一步包括以下步骤：
重复(b)至(g)步骤约10个循环或300个循环以将硅层生长于所述外延膜的所述顶表面上。
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