TW201628065A - 在低溫下生長薄磊晶膜的方法 - Google Patents

在低溫下生長薄磊晶膜的方法 Download PDF

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TW201628065A
TW201628065A TW104135804A TW104135804A TW201628065A TW 201628065 A TW201628065 A TW 201628065A TW 104135804 A TW104135804 A TW 104135804A TW 104135804 A TW104135804 A TW 104135804A TW 201628065 A TW201628065 A TW 201628065A
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seconds
epitaxial film
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督比阿布希雪克
仲華
王振宇
李學斌
黃奕樵
諸紹芳
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應用材料股份有限公司
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Abstract

本發明揭露的實施一般係關於磊晶薄膜上的矽材料的磊晶成長之方法。在一個實施中,該方法包括於半導體片(fin)上形成磊晶薄膜,其中磊晶薄膜包括具有第一刻面與第二刻面的頂表面,以及藉由在約375℃至約450℃的溫度與約5Torr至約20Torr的腔室壓力處將頂表面交替暴露於第一前驅物氣體與第二前驅物氣體而至少在磊晶薄膜的頂表面上形成磊晶層,第一前驅物氣體包含一或多個矽烷,第二前驅物氣體包含一或多個氯化矽烷。

Description

在低溫下生長薄磊晶膜的方法
本發明揭露的實施一般係關於半導體製程與裝置的領域,更特定言之,係關於用於矽材料在磊晶薄膜上磊晶成長的方法。
隨著對於下一代裝置的電路密度增加,互連件(如穿孔、溝槽、接觸件、閘極結構與其他特徵)的寬度以及於其間的介電材料減小至22nm或更小的尺寸,但是介電層的厚度保持實質不變,而有特徵的深寬比(aspect ratio)增加的結果。近來,互補式金屬氧化物半導體(CMOS)FinFET裝置已經廣泛地用於許多邏輯與其他應用中並整合入半導體裝置的各式不同類型。
FinFET裝置通常包括帶有高深寬比的半導體片(fin),其中用於電晶體的通道與源極/汲極區域於其上形成。利用通道與源極/汲極區域的增加之表面積的優勢而接著於片(fin)裝置的部分的側之上且沿著片裝置的部分的側形成而產生更快、更可靠的且更好控制的半導體電晶體裝置。FinFETs的進一步優勢包括減少短通道效應以及提供更高的電流流動。
為了改善電晶體效能,應力源(stressor)材料可填充源極/汲極區域,且該應力源材料可藉由磊晶而於源極/汲極區域中成長。磊晶薄膜由{111}平面刻面(facet)且沿著電晶體通道方向而具有金剛石形狀。隨著電晶體的縮減,對於形成FinFET的改善方法總是有所需求。
本發明揭露的實施一般係關於用於矽材料在磊晶薄膜上磊晶成長的方法。在一個實施中,該方法包括於半導體片上形成磊晶薄膜,該半導體片在該基板上形成,其中磊晶薄膜包含具有第一刻面與第二刻面的頂表面,以及藉由在約375℃至約450℃的溫度與約5Torr至約20Torr的腔室壓力處將頂表面交替暴露於第一前驅物氣體與第二前驅物氣體而至少在磊晶薄膜的頂表面上形成磊晶層,該第一前驅物氣體包含一或多個矽烷,該第二前驅物氣體包含一或多個氯化矽烷。
在另一個實施中,該方法包括將半導體結構裝載入處理腔室中,其中半導體結構包含基板、於基板上形成的複數個半導體片以及設置於基板上的半導體片之間的介電材料,於複數個半導體片上形成磊晶薄膜,其中各磊晶薄膜包括具有第一刻面與第二刻面之頂表面,及藉由在小於約450℃的溫度與約5Torr至約20Torr的腔室壓力處將頂表面交替暴露於第一前驅物氣體與第二前驅物氣體而至少在磊晶薄膜的頂表面上形成矽層,該第一前 驅物氣體包含一或多個矽烷,該第二前驅物氣體包含一或多個氯化矽烷。
在又另一個實施中,該方法包括(a)於半導體片上形成磊晶薄膜,該半導體片於該基板上形成,其中各磊晶薄膜包括具有第一刻面與第二刻面之頂表面,(b)在約450℃溫度與約5Torr至約20Torr的腔室壓力處將磊晶薄膜暴露於第一前驅物氣體,該第一前驅物氣體包含矽烷(SiH4)或乙矽烷(Si2H6),(c)在(b)步驟之後,用脈衝輸送第一前驅物氣體一第一周期時間,(d)在(c)步驟之後,將淨化氣體引入處理腔室中,(e)在(d)步驟之後,在小於約450℃的溫度與約5Torr至約20Torr的腔室壓力處將磊晶薄膜暴露於第二前驅物氣體,該第二前驅物氣體包含氯化矽烷,(f)在(e)步驟之後,用脈衝輸送第一前驅物氣體一第二周期時間,以及(g)在(f)步驟之後,將淨化氣體引入處理腔室中。在各式示範例中,該方法進一步包括重複(b)至(g)步驟約10個循環或300個循環直至所需的矽層厚度成長於磊晶薄膜的頂表面上。
100‧‧‧方法
102‧‧‧方塊
104‧‧‧方塊
106‧‧‧方塊
108‧‧‧方塊
200‧‧‧半導體結構
202‧‧‧基板
203‧‧‧半導體片
204‧‧‧第一部分
205‧‧‧第二部分
206‧‧‧介電材料
207‧‧‧表面
209‧‧‧表面
214‧‧‧磊晶應力源薄膜
215‧‧‧磊晶應力源薄膜
216‧‧‧刻面
217‧‧‧矽帽層
218‧‧‧刻面
219‧‧‧矽帽層
220‧‧‧刻面
222‧‧‧刻面
224‧‧‧角
226‧‧‧角
228‧‧‧角
本發明揭露之特徵已簡要概述於前,並在以下有更詳盡之討論,可以藉由參考附圖中繪示之本發明實施以作參考。然而,值得注意的是,附圖只繪示了本發明揭露的典型實施,而由於本發明可允許其他等效之實施例,附圖並不會視為本發明範圍之限制。
圖1係根據本發明揭露的用於製造半導體結構之示範方法的流程圖。
圖2A至2C繪示在根據圖1的流程圖的製造某些階段期間簡化的半導體結構之截面圖。
為便於理解,在可能的情況下,使用相同的數字編號代表圖示中相同的元件。可以明白,一個實施例中的元件與特徵可有利地用於其它實施例中而無需贅述。
圖1係根據本發明揭露實施的用於製造半導體結構之示範方法的流程圖。圖2A至2C繪示在根據圖1的流程圖的製造某些階段期間簡化的半導體結構之截面圖。本發明所屬領域具有通常知識者將進一步了解用於形成半導體裝置與相關結構的全部處理過程未繪示於圖式中或於此發明中描述。反之,為求簡單清楚,只繪示與描述了對於本發明揭露獨特或對於了解本發明揭露必要之用於形成半導體裝置與相關結構的某些處理過程。此外,雖然各式步驟繪示於圖式中及描述於本說明書中,但是沒有表示此等步驟的順序或中間步驟存在與否有所限制。除非明確指示,否則所繪示與描述的步驟僅用作解釋用途依序繪示與描述,如果沒完全實施的話,不排除個別的步驟實際上以同時或重疊的方式至少部分地施行之可能性。
方法100在方塊102藉由將半導體結構200裝載入處理腔室而開始。半導體結構200包括基板202、複數個半導體片203(只顯示了兩個)以及設置於基板 202上的半導體片203之間的介電材料206,如圖2A所示。處理腔室可係ALE(原子層磊晶)或ALD(原子層沈積)、CVD(化學氣相沈積)或電漿輔助處理技術領域中習知的任何適合的沈積處理腔室。
本說明書所用術語「基板」意欲廣泛涵蓋可以在處理腔室中處理的任何物件。例如,基板202可係能夠具有材料沈積於其上的任何基板,如矽基板,例如矽(摻雜的或未摻雜的)、晶狀矽(如Si<100>或Si<111>)、氧化矽、應變矽、摻雜或未摻雜的多晶矽或類似物,鍺、III-V族化合物的基板,矽鍺(SiGe)基板,碳化矽鍺(SiGeC)基板,氧化矽鍺(SiGeO)基板,氮氧化矽鍺(SiGeON)基板,碳化矽(SiC)基板,碳氮化矽(SiCN)基板,碳氧化矽(SiCO),磊晶基板,矽上絕緣體(SOI)基板,碳摻雜氧化物,氮化矽,如液晶顯示器(LCD)的顯示基板,電漿顯示器,電致發光(EL)燈顯示器,太陽能陣列,太陽能板,發光二極管(LED)基板,圖案化或非圖案化的半導體晶圓,玻璃,藍寶石,或任何其它材料,例如金屬、金屬合金和其它導電材料。基板202可係平坦基板或圖案化基板。圖案化基板係包括在基板的處理表面中或上形成的電子特徵之基板。基板202可包括多個層或包括如部分製造的裝置(如電晶體、快閃記憶體裝置及其類似物)。
在一個實施中,基板202係單晶體矽,如P摻雜矽。半導體片203可包括與基板202相同或不同的材 料。在所示實施中,半導體片203與基板202由相同材料形成。介電材料206可形成隔離區域,如淺溝槽隔離(STI)區域,且可包括SiO、SiN、SiCN或任何適合的介電材料。
半導體片203可實施在用於較後面階段中的FinFET電晶體的形成通道中。各半導體片203可包括第一部分204與第二部分205,第一部分204具有與介電材料206的表面209共面的表面207,第二部分205自第一部分204向上突出。第二部分205可作為源極或汲極區域的功能。因此,半導體結構200的頂表面包括一或多個半導體區域(即半導體片203的第一部分204與(或)第二部分205)以及一或多個介電區域(即介電材料206)。
在方塊104,磊晶應力源薄膜214、215於第二部分205(即源極/汲極區域)上的各半導體片203上成長以改善電晶體效能。磊晶應力源薄膜214、215可係源極或汲極區域的部份。磊晶應力源薄膜214、215可密封或覆蓋半導體片203的第二部分205所暴露的表面,如圖2A所示。或者,半導體片203的第二部分205可被移除且磊晶應力源薄膜214、215可於半導體片203的第一部分204上形成。
磊晶應力源薄膜214、215可包括Si:P、SiGe、SiGe:B、Si:CP或其他適合的半導體材料。在一個實施中,磊晶應力源薄膜214、215包括SiGe材料。在某些應用中,其中需要高濃度的鍺,例如用於導電節點 先進7nm及更進一步中使用的pMOS源極與汲極材料,在矽中的鍺之濃度可係在約30%之上,如約45%或更多,如約70%至約100%。
磊晶應力源薄膜214、215可使用選擇性沈積處理形成,而使得磊晶應力源薄膜214、215於半導體片203上成長而不是在介電材料206上成長。生成的磊晶應力源薄膜214可具有單晶體結構。可藉由將蝕刻劑與前驅物氣體共同流入沈積腔室而達成選擇性沈積處理。蝕刻劑的示範例可係HCl、Cl2或任何適合的鹵素氣體。前驅物氣體可包括任何適合的含矽氣體,如矽烷、乙矽烷、有機矽烷或鹵化矽烷,以及任何合適的含鍺氣體,如鍺烷。
磊晶應力源薄膜214、215可於半導體片203上磊晶成長,且由於在不同表面平面上的不同成長速率,刻面經形成以導致當注意到其沿著電晶體通道方向(該通道沿著半導體片203的頂與相對側壁延伸)時,磊晶應力源薄膜214、215具有金剛石形狀。磊晶應力源薄膜214、215由{111}平面刻面、固定在頂角落與側壁角落處。例如,磊晶應力源薄膜214可包括複數個刻面216、218、220、222(為求清楚,半導體片203中只有一個標示於圖2A中)。刻面216、218可接觸半導體片203。刻面216與刻面220可互相接觸,且角(corner)224可在接觸點處形成。刻面218與刻面222可互相接觸,且角226可在接觸點處形成。刻面220與刻面222可互相接觸,且角228可在接觸點處形成。
在方塊106,磊晶應力源薄膜214、215的部分可選擇性地在側向維度上移除。具體言之,磊晶應力源薄膜214的相對側上的部分經移除以增加半導體片上的磊晶應力源薄膜214與鄰近半導體片上成長的磊晶應力源薄膜215之間的距離。接觸點處的角228的部分可選擇性地被移除,如圖2B所示。隨著電晶體縮減,片間距(fin pitch,兩鄰近片之間的距離)變得更小。因此,源極/汲極上成長的磊晶應力源薄膜可以被碰觸(touched)或合併(merged)。一旦合併產生,(電晶體通道上的應變上的)應力源的效應減小且缺陷容易在合併區域的連接點處形成,其對半導體結構的效能以及電晶體效能有負面影響。由於鄰近磊晶薄膜之間的距離增加,而防止磊晶應力源薄膜214與鄰近應力源薄膜215互相碰觸或合併。可藉由蝕刻、研磨或其他適合的移除處理而達成磊晶應力源薄膜的部分之選擇性移除。蝕刻處理可在用於沈積的相同腔室中實施,或在分開但整合的腔室中實施。
在方塊108,矽帽層217、219一致地於磊晶應力源薄膜214、215上分別形成以鈍化磊晶應力源薄膜214、215,使得後續的層(如閘極介電,如二氧化矽、摻雜碳的矽氧化物、矽鍺氧化物、或高k介電材料)可以輕易地於半導體片203的部分上形成。矽帽層可在應力源薄膜214、215的至少頂表面(即刻面220、222)上形成。矽帽層217、219可藉由化學氣相沈積(CVD)處理、原子層磊晶(ALE)或原子層沈積(ALD)處理而 成長。在一個實施中,矽帽層217、219由ALE處理形成。ALE係一種周期性沈積處理,其施用沈積技術以將前驅物分子依順序周期傳送於加熱的基板表面上。在各式實施中,磊晶應力源薄膜214、215依序暴露於第一前驅物氣體、淨化氣體、第二前驅物氣體與淨化氣體。第一與第二前驅物氣體反應以形成化學化合物而形成薄膜於磊晶應力源薄膜214、215的表面上。重複此周期以一層一層的方式成長矽帽層217、219直到所需的厚度達到。在一個實施中,其中下面的SiGe磊晶應力源薄膜214、215係約3-6nm厚度,矽帽層217、219可具有約1nm至約5nm的厚度,例如約2nm至約3nm。矽帽層的沈積可於相同腔室中實施以用於沈積磊晶應力源薄膜214、215,或是在分開但整合的腔室中實施。
在各式實施中,第一前驅物氣體與第二前驅物氣體可係含矽氣體。適合的含矽氣體可包括矽烷、鹵化矽烷或有機矽烷中的一或多個。矽烷可包括矽烷(SiH4)與帶有經驗方程式SixH(2x+2)的更高階的矽烷(higher silanes),如乙矽烷(Si2H6)、丙矽烷(Si3H8)與四矽烷(Si4H10),或其他更高階的矽烷,如聚氯矽烷。鹵化矽烷可包括帶有經驗方程式的化合物X ySixH(2x+2-y),其中X=F,Cl,Br或I,如六氯二矽烷(Si2Cl6)、四氯矽烷(SiCl4)、二氯矽烷(Cl2SiH2)與三氯矽烷(Cl3SiH)。有機矽烷可包括帶有經驗方程式RySixH(2x+2-y)的化合物,其中R=甲基、乙基、丙 基或丁基,如甲基矽烷((CH3)SiH3)、二甲基矽烷(CH3)2SiH2)、乙基矽烷(CH3CH2)SiH3)、甲基二矽烷(CH3)Si2H5)、二甲基二矽烷((CH3)2Si2H4)與六甲基二矽烷((CH3)6Si2)。合適的含鍺氣體可包括但不局限於鍺烷(GeH4)、二鍺烷(Ge2H6)、三鍺烷(Ge3H8)或以上其中兩個或更多之組合。在某些實施中,四乙氧基矽烷(TEOS)亦可用作第一或第二前驅物氣體。
在一個示範的實施中,第一前驅物氣體係矽基前驅物氣體,如矽烷(SiH4)與帶有經驗方程式SixH(2x+2)的更高階的矽烷如乙矽烷(Si2H6)、丙矽烷(Si3H8)或四矽烷(Si4H10)。如需要的話,第一前驅物氣體可包括本發明所述的矽基前驅物氣體中的一或多個。第二前驅物氣體係鹵化矽烷,例如氯化矽烷,如一氯矽烷(SiH3Cl,MCS)、二氯矽烷(Si2H2Cl2,DCS)、三氯矽烷(SiHCl3,TCS)、六氯二矽烷(Si2Cl6,HCDS)、八氯三矽烷(Si3Cl8,OCTS)或四氯化矽(STC)。如需要的話,第二前驅物氣體可包括本發明所述的鹵化矽烷中的一或多個。合適的淨化氣體可包括氦、氬、氮、氫、形成氣體或以上各者之組合。
在使用ALE處理的一個示範例中,第一前驅物氣體係乙矽烷而第二前驅物氣體係HCDS。ALE處理在約350℃至約550℃的溫度範圍(如375℃至約450°C,如約425℃)以及約1Torr至約40Torr(如約5Torr 至約20Torr,例如約10Torr)腔室壓力處實施。在下方磊晶應力源薄膜214、215於矽中具有高濃度Ge(如30%或以上,如40%或以上)的情況下,使用較低沈積溫度(如約425℃或更低,如350℃至約375℃)可係有優勢的,以避免磊晶應力源薄膜的變形。
在操作中,磊晶應力源薄膜214、215暴露於使用乙矽烷的第一前驅物氣體。第一前驅物氣體以約5sccm至約35sccm範圍的流動速率被引入處理腔室中,如約10sccm至約25sccm,例如約20sccm。接著用脈衝輸送(pulse)第一前驅物氣體約5秒至約25秒,如約15秒。下一步,淨化氣體以約5sccm至約25sccm範圍的流動速率被引入處理腔室中,如約10sccm至約20sccm,例如約15sccm。下一步,磊晶應力源薄膜214、215暴露於使用HCDS的第二前驅物氣體。第二前驅物氣體以約250sccm至約550sccm範圍的流動速率被引入處理腔室中,如約350sccm至約450sccm,例如約400sccm。第二前驅物氣體稀釋於氮氣或氫氣載體氣體中,氮氣或氫氣載體氣體以約1SLM至約30SLM的流動速率流動入處理腔室中,如約3SLM。接著用脈衝輸送(pulse)第二前驅物氣體約5秒至約25秒,如約15秒。之後,淨化氣體以約5sccm至約25sccm範圍的流動速率被引入處理腔室中,如約10sccm至約20sccm,例如約15sccm。藉由上述處理狀況交替乙矽烷與HCDS而將矽帽層一致地(conformally)且均勻地 成長於磊晶應力源薄膜上。加入六氯二矽烷(Si2Cl6,HCDS)而在表面處將-H配位基(ligand)換成Cl終端(termination)並在其上形成額外的矽層。此處理過程以約0.1Å/周期的成長速率重複約300個周期以達到所需的厚度。
在使用ALE處理的另一個示範例中,第一前驅物氣體仍係乙矽烷而第二前驅物氣體仍係HCDS。然而,調整為較長的脈衝時間(pulse time)。在此示範例中,ALE處理在約350℃至約550℃的溫度範圍(如約375℃至約450℃,例如約425℃)以及約1Torr至約40Torr(如約5Torr至約20Torr,例如約10Torr)的腔室壓力處實施。在下方磊晶應力源薄膜214、215於矽中具有高濃度Ge(如30%或以上,如40%或以上)的情況下,使用較低沈積溫度(如約425℃或更低,如350℃至約375℃)可係有優勢的,以避免磊晶應力源薄膜的變形。
在操作中,磊晶應力源薄膜214、215暴露於使用乙矽烷的第一前驅物氣體。第一前驅物氣體以約5sccm至約35sccm範圍的流動速率被引入處理腔室中,如約10sccm至約25sccm,例如約20sccm。接著用脈衝輸送(pulse)第一前驅物氣體約350秒至約550秒,如約450秒。下一步,淨化氣體以約5sccm至約25sccm範圍的流動速率被引入處理腔室中,如約10sccm至約20sccm,例如約15sccm。下一步,磊晶應力源 薄膜214、215暴露於使用HCDS的第二前驅物氣體。第二前驅物氣體以約250sccm至約550sccm範圍的流動速率被引入處理腔室中,如約350sccm至約450sccm,例如約400sccm。第二前驅物氣體稀釋於氮氣或氫氣載體氣體中,氮氣或氫氣載體氣體以約1SLM至約30SLM的流動速率流動入處理腔室中,如約3SLM。接著用脈衝輸送(pulse)第二前驅物氣體約350秒至約550秒,如約450秒。之後,淨化氣體以約5sccm至約25sccm範圍的流動速率被引入處理腔室中,如約10sccm至約20sccm,例如約15sccm。藉由上述處理狀況交替乙矽烷與HCDS而將一單層的矽一致地(conformally)且均勻地成長於磊晶應力源薄膜上。此處理過程以約0.1Å/周期的成長速率重複約10個周期以達到所需的厚度。
在使用ALE處理的又另一個示範例中,第一前驅物氣體係矽烷而第二前驅物氣體係HCDS。因為矽烷在半導體片203的側壁上顯示有較少的側向薄膜成長,所以觀察到矽烷在某些應用中是有優勢的。在此示範例中,ALE處理在約350℃至約550℃的溫度範圍(如375℃至約450℃,例如約425℃)以及約1Torr至約40Torr(如約5Torr至約20Torr,例如約10Torr)的腔室壓力處實施。在下方磊晶應力源薄膜214、215於矽中具有高濃度Ge(如30%或以上,如40%或以上)的情況下, 使用較低沈積溫度(如約425℃或更低,如350℃至約375℃)可係有優勢的,以避免磊晶應力源薄膜的變形。
在操作中,磊晶應力源薄膜214、215暴露於使用矽烷的第一前驅物氣體。第一前驅物氣體以約25sccm至約55sccm範圍的流動速率被引入處理腔室中,如約30sccm至約45sccm,例如約40sccm。接著用脈衝輸送(pulse)第一前驅物氣體約650秒至約1200秒,如約900秒。下一步,淨化氣體以約5sccm至約25sccm範圍的流動速率被引入處理腔室中,如約10sccm至約20sccm,例如約15sccm。下一步,磊晶應力源薄膜214、215暴露於使用HCDS的第二前驅物氣體。第二前驅物氣體以約250sccm至約550sccm範圍的流動速率被引入處理腔室中,如約350sccm至約450sccm,例如約400sccm。第二前驅物氣體稀釋於氮氣或氫氣載體氣體中,氮氣或氫氣載體氣體以約1SLM至約30SLM的流動速率流動入處理腔室中,如約3SLM。接著用脈衝輸送(pulse)第二前驅物氣體約350秒至約550秒,如約450秒。之後,淨化氣體以約5sccm至約25sccm範圍的流動速率被引入處理腔室中,如約10sccm至約20sccm,例如約15sccm。藉由上述處理狀況交替矽烷與HCDS而將一單層的矽一致地且均勻地成長於磊晶應力源薄膜上。此處理過程以約0.1Å/周期的成長速率重複約10個周期以達到所需的厚度。
在矽帽層217、219以所需的厚度成長於磊晶應力源薄膜214、215上後,閘極介電層(未圖示)可於矽帽層217、219上形成。閘極電極接著於半導體片203的部分上且沿著半導體片203的部分側形成以形成FinFET的一般結構。
本發明揭露的實施中所述之概念亦適用於其他磊晶材料。某些示範例可包括Si:CP、純Ge、GeSn、GeP、GeB或GeSnB等,其可用於邏輯與記憶體應用。在此等情況中,可能的矽前驅物可包括如上所述的鹵化矽化合物與選擇性的含矽化合物,而可能的鍺前驅物可包括如上所述的鹵化鍺化合物與選擇性的含鍺化合物。例如,如果矽鍺用作為帽層,可藉由將磊晶應力源薄膜交替暴露於第一前驅物氣體與第二前驅物氣體而達到矽鍺的磊晶成長,第一前驅物氣體包括本發明揭露中所述的含矽氣體中的一或多個,第二前驅物氣體包括鹵化鍺氣體(如氯化鍺烷氣體、含鍺氣體或含矽氣體)中的一或多個。淨化氣體與任何所需的摻雜氣體可依以上相對於矽帽層所述的方式引入處理腔室中。在一個示範實施中,第一前驅物氣體可係矽烷或乙矽烷,而第二前驅物氣體可係氯化鍺烷氣體,如四氯化鍺(GeCl4)、二氯鍺烷(GeH2Cl2)或鍺烷(GeH4)。
本發明揭露的好處包括藉由使用第一前驅物氣體與第二前驅物氣體的原子層磊晶(ALE)而於SiGe磊晶應力源層上直接成長薄矽帽層,第一前驅物氣體包括 矽烷,第二前驅物氣體包括氯化矽烷。已經觀察到藉由交替矽烷或乙矽烷與HCDS可以在較低成長溫度達到矽帽層於包含SiGe的磊晶應力源薄膜上的成長。具體言之,因為藉由使用自我限制一層一層的方式(self-limiting layer-by-layer fashion)的ALE處理成長矽帽層,所以矽帽層可以均勻且一致地成長於磊晶應力源薄膜而不失介電質(如矽氧化物與矽氮化物)成長的選擇性。使用矽烷與氯化矽烷的矽磊晶成長鈍化應力源薄膜而允許後續閘極介電質有更好的成長,而使得用於FinFET的磊晶材料有更好的整合與表面形狀控制(surface morphology)。
雖然前面所述係針對本發明揭露的實施,但在不背離本發明基本範圍下,可設計本發明揭露的其他與進一步的實施例,而本發明範圍由以下申請專利範圍所界定。
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Claims (20)

  1. 一種在一處理腔室中處理一基板的方法,包括以下步驟:於一半導體片形成一磊晶薄膜,該半導體片在該基板上形成,其中該磊晶薄膜包含具有一第一刻面與一第二刻面的一頂表面;及藉由在約550℃或小於550℃的一溫度與約5Torr至約20Torr的一腔室壓力處將該頂表面交替暴露於一第一前驅物氣體與一第二前驅物氣體而至少在該磊晶薄膜的該頂表面上形成一磊晶層,該第一前驅物氣體包含一或多個矽烷,該第二前驅物氣體包含一或多個氯化矽烷。
  2. 如請求項1所述之方法,其中該第一前驅物氣體包括矽烷(SiH4)、乙矽烷(Si2H6)、丙矽烷(Si3H8)、四矽烷(Si4H10)或四乙氧基矽烷(TEOS)。
  3. 如請求項1所述之方法,其中該第二前驅物氣體包括一氯矽烷(SiH3Cl)、二氯矽烷(Si2H2Cl2)、三氯矽烷(SiHCl3)、六氯二矽烷(Si2Cl6)、八氯三矽烷(Si3Cl8)或四氯化矽(STC)。
  4. 如請求項1所述之方法,進一步包括以下步 驟:將一淨化氣體引入該第一前驅物氣體的流動與該第二前驅物氣體的流動之間的該處理腔室中。
  5. 一種處理一基板的方法,包括以下步驟:將一半導體結構裝載入一處理腔室中,其中該半導體結構包含一基板、於該基板上形成的複數個半導體片以及設置於該基板上的該等半導體片之間的一介電材料;於該複數個半導體片上形成一磊晶薄膜,其中各磊晶薄膜包括具有一第一刻面與一第二刻面之一頂表面;及藉由在小於約550℃的一溫度與約5Torr至約20Torr的一腔室壓力處將該頂表面交替暴露於一第一前驅物氣體與一第二前驅物氣體而至少在該磊晶薄膜的該頂表面上形成一矽層,該第一前驅物氣體包含一或多個矽烷,該第二前驅物氣體包含一或多個氯化矽烷。
  6. 如請求項5所述之方法,其中該第一前驅物氣體包括矽烷(SiH4)、乙矽烷(Si2H6)、丙矽烷(Si3H8)或四矽烷(Si4H10)。
  7. 如請求項6所述之方法,其中該第一前驅物氣體包括矽烷(SiH4)。
  8. 如請求項6所述之方法,其中該第一前驅物氣體包括乙矽烷(Si2H6)。
  9. 如請求項5所述之方法,其中該第二前驅物氣體包括一氯矽烷(SiH3Cl)、二氯矽烷(Si2H2Cl2)、三氯矽烷(SiHCl3)、六氯二矽烷(Si2Cl6)、八氯三矽烷(Si3Cl8)或四氯化矽(STC)。
  10. 如請求項9所述之方法,其中該第二前驅物氣體包括六氯二矽甲烷(Si2Cl6)。
  11. 如請求項5所述之方法,其中該基板與該等半導體片包括一單晶矽。
  12. 如請求項5所述之方法,進一步包含以下步驟:在該磊晶薄膜的該頂表面上形成一矽層之前,在一側向方向上移除該磊晶薄膜的部分。
  13. 如請求項12所述之方法,其中該磊晶薄膜進一步包括接觸該第一刻面與該半導體片的一第三刻面以及接觸該第二刻面與該半導體片的一第四刻面,及其中在該側向方向上移除該磊晶薄膜的部分之該步驟包括移除該第一、第二、第三與第四刻面之一部分。
  14. 如請求項5所述之方法,進一步包括以下步驟:將一淨化氣體引入該第一前驅物氣體的流動與該第 二前驅物氣體的流動之間的該處理腔室中。
  15. 如請求項14所述之方法,進一步包括以下步驟:在將該頂表面暴露於一第一前驅物氣體之後且在將該淨化氣體引入該處理腔室之前,用脈衝輸送(pulse)該第一前驅物氣體約5秒至約25秒。
  16. 如請求項14所述之方法,進一步包括以下步驟:在將該頂表面暴露於一第二前驅物氣體之後且在將該淨化氣體引入該處理腔室之前,用脈衝輸送(pulse)該第二前驅物氣體約350秒至約550秒。
  17. 一種在一處理腔室中處理一基板的方法,包括以下步驟:(a)於一半導體片上形成一磊晶薄膜,該半導體片於該基板上形成,其中各磊晶薄膜包括具有一第一刻面與一第二刻面之一頂表面;(b)在約350℃至約550℃的一溫度與約5Torr至約20Torr的一腔室壓力處將該磊晶薄膜暴露於一第一前驅物氣體,該第一前驅物氣體包含矽烷(SiH4)或乙矽烷(Si2H6);(c)在(b)步驟之後,用脈衝輸送該第一前驅物氣體一第一周期時間; (d)在(c)步驟之後,將一淨化氣體引入該處理腔室中;(e)在(d)步驟之後,在小於約450℃的一溫度與約5Torr至約20Torr的一腔室壓力處將該磊晶薄膜暴露於一第二前驅物氣體,該第二前驅物氣體包含氯化矽烷;(f)在(e)步驟之後,用脈衝輸送該第一前驅物氣體一第二周期時間;及(g)在(f)步驟之後,將該淨化氣體引入該處理腔室中。
  18. 如請求項17所述之方法,其中該第二前驅物氣體包括六氯二矽甲烷(Si2Cl6)。
  19. 如請求項17所述之方法,其中該第一周期時間係約5秒至約25秒或約350秒至約550秒,及該第二周期時間係約5秒至約25秒或約350秒至約550秒。
  20. 如請求項17所述之方法,進一步包括以下步驟:重複(b)至(g)步驟約10個循環或300個循環以將一矽層成長於該磊晶薄膜的該頂表面上。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI658178B (zh) * 2017-06-23 2019-05-01 上海新昇半導體科技有限公司 一種半導體元件及其製造方法、電子裝置
TWI748021B (zh) * 2016-12-12 2021-12-01 美商應用材料股份有限公司 形成應變通道層的方法

Families Citing this family (210)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130023129A1 (en) 2011-07-20 2013-01-24 Asm America, Inc. Pressure transmitter for a semiconductor processing environment
US10714315B2 (en) 2012-10-12 2020-07-14 Asm Ip Holdings B.V. Semiconductor reaction chamber showerhead
US20160376700A1 (en) 2013-02-01 2016-12-29 Asm Ip Holding B.V. System for treatment of deposition reactor
US10941490B2 (en) 2014-10-07 2021-03-09 Asm Ip Holding B.V. Multiple temperature range susceptor, assembly, reactor and system including the susceptor, and methods of using the same
US10276355B2 (en) 2015-03-12 2019-04-30 Asm Ip Holding B.V. Multi-zone reactor, system including the reactor, and method of using the same
KR102310076B1 (ko) 2015-04-23 2021-10-08 삼성전자주식회사 비대칭 소스/드레인 포함하는 반도체 소자
US10458018B2 (en) 2015-06-26 2019-10-29 Asm Ip Holding B.V. Structures including metal carbide material, devices including the structures, and methods of forming same
US10211308B2 (en) 2015-10-21 2019-02-19 Asm Ip Holding B.V. NbMC layers
US11139308B2 (en) 2015-12-29 2021-10-05 Asm Ip Holding B.V. Atomic layer deposition of III-V compounds to form V-NAND devices
US10529554B2 (en) 2016-02-19 2020-01-07 Asm Ip Holding B.V. Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches
KR102321839B1 (ko) * 2016-05-09 2021-11-05 어플라이드 머티어리얼스, 인코포레이티드 트랜지스터의 소스/드레인 영역 상의 에피택셜 필름에 대한 선택적 식각 방법
US11453943B2 (en) 2016-05-25 2022-09-27 Asm Ip Holding B.V. Method for forming carbon-containing silicon/metal oxide or nitride film by ALD using silicon precursor and hydrocarbon precursor
US9773870B1 (en) * 2016-06-28 2017-09-26 International Business Machines Corporation Strained semiconductor device
US10612137B2 (en) 2016-07-08 2020-04-07 Asm Ip Holdings B.V. Organic reactants for atomic layer deposition
US9859151B1 (en) 2016-07-08 2018-01-02 Asm Ip Holding B.V. Selective film deposition method to form air gaps
US9812320B1 (en) 2016-07-28 2017-11-07 Asm Ip Holding B.V. Method and apparatus for filling a gap
US9887082B1 (en) 2016-07-28 2018-02-06 Asm Ip Holding B.V. Method and apparatus for filling a gap
US11532757B2 (en) 2016-10-27 2022-12-20 Asm Ip Holding B.V. Deposition of charge trapping layers
US10714350B2 (en) 2016-11-01 2020-07-14 ASM IP Holdings, B.V. Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures
KR101960763B1 (ko) 2016-11-03 2019-03-21 주식회사 유진테크 저온 에피택셜층 형성방법
KR102546317B1 (ko) 2016-11-15 2023-06-21 에이에스엠 아이피 홀딩 비.브이. 기체 공급 유닛 및 이를 포함하는 기판 처리 장치
US10515951B2 (en) * 2016-11-29 2019-12-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
KR20180068582A (ko) 2016-12-14 2018-06-22 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치
US11581186B2 (en) 2016-12-15 2023-02-14 Asm Ip Holding B.V. Sequential infiltration synthesis apparatus
US11447861B2 (en) 2016-12-15 2022-09-20 Asm Ip Holding B.V. Sequential infiltration synthesis apparatus and a method of forming a patterned structure
EP3339244A1 (en) * 2016-12-21 2018-06-27 IMEC vzw Source and drain contacts in fin- or nanowire- based semiconductor devices.
US10269558B2 (en) 2016-12-22 2019-04-23 Asm Ip Holding B.V. Method of forming a structure on a substrate
US11390950B2 (en) 2017-01-10 2022-07-19 Asm Ip Holding B.V. Reactor system and method to reduce residue buildup during a film deposition process
US10468261B2 (en) 2017-02-15 2019-11-05 Asm Ip Holding B.V. Methods for forming a metallic film on a substrate by cyclical deposition and related semiconductor device structures
US10770286B2 (en) 2017-05-08 2020-09-08 Asm Ip Holdings B.V. Methods for selectively forming a silicon nitride film on a substrate and related semiconductor device structures
US11306395B2 (en) 2017-06-28 2022-04-19 Asm Ip Holding B.V. Methods for depositing a transition metal nitride film on a substrate by atomic layer deposition and related deposition apparatus
KR102414182B1 (ko) 2017-06-29 2022-06-28 삼성전자주식회사 반도체 소자
KR20190009245A (ko) 2017-07-18 2019-01-28 에이에스엠 아이피 홀딩 비.브이. 반도체 소자 구조물 형성 방법 및 관련된 반도체 소자 구조물
US11374112B2 (en) 2017-07-19 2022-06-28 Asm Ip Holding B.V. Method for depositing a group IV semiconductor and related semiconductor device structures
US10590535B2 (en) 2017-07-26 2020-03-17 Asm Ip Holdings B.V. Chemical treatment, deposition and/or infiltration apparatus and method for using the same
US10770336B2 (en) 2017-08-08 2020-09-08 Asm Ip Holding B.V. Substrate lift mechanism and reactor including same
US10692741B2 (en) 2017-08-08 2020-06-23 Asm Ip Holdings B.V. Radiation shield
US11769682B2 (en) 2017-08-09 2023-09-26 Asm Ip Holding B.V. Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith
US11830730B2 (en) 2017-08-29 2023-11-28 Asm Ip Holding B.V. Layer forming method and apparatus
US11295980B2 (en) 2017-08-30 2022-04-05 Asm Ip Holding B.V. Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process and related semiconductor device structures
SG11202001191VA (en) 2017-09-03 2020-03-30 Applied Materials Inc Conformal halogen doping in 3d structures using conformal dopant film deposition
US10658205B2 (en) 2017-09-28 2020-05-19 Asm Ip Holdings B.V. Chemical dispensing apparatus and methods for dispensing a chemical to a reaction chamber
US11127617B2 (en) 2017-11-27 2021-09-21 Asm Ip Holding B.V. Storage device for storing wafer cassettes for use with a batch furnace
CN111344522B (zh) 2017-11-27 2022-04-12 阿斯莫Ip控股公司 包括洁净迷你环境的装置
US10872771B2 (en) 2018-01-16 2020-12-22 Asm Ip Holding B. V. Method for depositing a material film on a substrate within a reaction chamber by a cyclical deposition process and related device structures
CN111630203A (zh) 2018-01-19 2020-09-04 Asm Ip私人控股有限公司 通过等离子体辅助沉积来沉积间隙填充层的方法
TWI799494B (zh) 2018-01-19 2023-04-21 荷蘭商Asm 智慧財產控股公司 沈積方法
US11081345B2 (en) 2018-02-06 2021-08-03 Asm Ip Holding B.V. Method of post-deposition treatment for silicon oxide film
US11685991B2 (en) 2018-02-14 2023-06-27 Asm Ip Holding B.V. Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process
US10896820B2 (en) 2018-02-14 2021-01-19 Asm Ip Holding B.V. Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process
KR102636427B1 (ko) 2018-02-20 2024-02-13 에이에스엠 아이피 홀딩 비.브이. 기판 처리 방법 및 장치
US10975470B2 (en) 2018-02-23 2021-04-13 Asm Ip Holding B.V. Apparatus for detecting or monitoring for a chemical precursor in a high temperature environment
US11473195B2 (en) 2018-03-01 2022-10-18 Asm Ip Holding B.V. Semiconductor processing apparatus and a method for processing a substrate
US11629406B2 (en) 2018-03-09 2023-04-18 Asm Ip Holding B.V. Semiconductor processing apparatus comprising one or more pyrometers for measuring a temperature of a substrate during transfer of the substrate
KR102646467B1 (ko) 2018-03-27 2024-03-11 에이에스엠 아이피 홀딩 비.브이. 기판 상에 전극을 형성하는 방법 및 전극을 포함하는 반도체 소자 구조
US11230766B2 (en) 2018-03-29 2022-01-25 Asm Ip Holding B.V. Substrate processing apparatus and method
KR20190128558A (ko) 2018-05-08 2019-11-18 에이에스엠 아이피 홀딩 비.브이. 기판 상에 산화물 막을 주기적 증착 공정에 의해 증착하기 위한 방법 및 관련 소자 구조
KR102596988B1 (ko) 2018-05-28 2023-10-31 에이에스엠 아이피 홀딩 비.브이. 기판 처리 방법 및 그에 의해 제조된 장치
US11270899B2 (en) 2018-06-04 2022-03-08 Asm Ip Holding B.V. Wafer handling chamber with moisture reduction
US11718913B2 (en) 2018-06-04 2023-08-08 Asm Ip Holding B.V. Gas distribution system and reactor system including same
US11286562B2 (en) 2018-06-08 2022-03-29 Asm Ip Holding B.V. Gas-phase chemical reactor and method of using same
US10797133B2 (en) 2018-06-21 2020-10-06 Asm Ip Holding B.V. Method for depositing a phosphorus doped silicon arsenide film and related semiconductor device structures
KR102568797B1 (ko) 2018-06-21 2023-08-21 에이에스엠 아이피 홀딩 비.브이. 기판 처리 시스템
JP2021529254A (ja) 2018-06-27 2021-10-28 エーエスエム・アイピー・ホールディング・ベー・フェー 金属含有材料ならびに金属含有材料を含む膜および構造体を形成するための周期的堆積方法
WO2020003000A1 (en) 2018-06-27 2020-01-02 Asm Ip Holding B.V. Cyclic deposition methods for forming metal-containing material and films and structures including the metal-containing material
US10612136B2 (en) 2018-06-29 2020-04-07 ASM IP Holding, B.V. Temperature-controlled flange and reactor system including same
US10388513B1 (en) 2018-07-03 2019-08-20 Asm Ip Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
US10755922B2 (en) 2018-07-03 2020-08-25 Asm Ip Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
KR102501287B1 (ko) 2018-07-30 2023-02-21 어플라이드 머티어리얼스, 인코포레이티드 낮은 온도들에서의 선택적 규소 게르마늄 에피택시 방법
US10679995B2 (en) * 2018-07-31 2020-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US11430674B2 (en) 2018-08-22 2022-08-30 Asm Ip Holding B.V. Sensor array, apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods
KR20200030162A (ko) 2018-09-11 2020-03-20 에이에스엠 아이피 홀딩 비.브이. 박막 증착 방법
US11024523B2 (en) 2018-09-11 2021-06-01 Asm Ip Holding B.V. Substrate processing apparatus and method
CN110970344A (zh) 2018-10-01 2020-04-07 Asm Ip控股有限公司 衬底保持设备、包含所述设备的系统及其使用方法
US11232963B2 (en) 2018-10-03 2022-01-25 Asm Ip Holding B.V. Substrate processing apparatus and method
KR102592699B1 (ko) 2018-10-08 2023-10-23 에이에스엠 아이피 홀딩 비.브이. 기판 지지 유닛 및 이를 포함하는 박막 증착 장치와 기판 처리 장치
US11230474B2 (en) 2018-10-11 2022-01-25 L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude Process for producing isomer enriched higher silanes
US11401166B2 (en) 2018-10-11 2022-08-02 L'Air Liaquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude Process for producing isomer enriched higher silanes
US11097953B2 (en) 2018-10-11 2021-08-24 L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude Process for producing liquid polysilanes and isomer enriched higher silanes
US10752507B2 (en) 2018-10-11 2020-08-25 L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude Process for producing liquid polysilanes and isomer enriched higher silanes
KR102546322B1 (ko) 2018-10-19 2023-06-21 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치 및 기판 처리 방법
KR102605121B1 (ko) 2018-10-19 2023-11-23 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치 및 기판 처리 방법
US11087997B2 (en) 2018-10-31 2021-08-10 Asm Ip Holding B.V. Substrate processing apparatus for processing substrates
KR20200051105A (ko) 2018-11-02 2020-05-13 에이에스엠 아이피 홀딩 비.브이. 기판 지지 유닛 및 이를 포함하는 기판 처리 장치
US11572620B2 (en) 2018-11-06 2023-02-07 Asm Ip Holding B.V. Methods for selectively depositing an amorphous silicon film on a substrate
US10818758B2 (en) 2018-11-16 2020-10-27 Asm Ip Holding B.V. Methods for forming a metal silicate film on a substrate in a reaction chamber and related semiconductor device structures
US11217444B2 (en) 2018-11-30 2022-01-04 Asm Ip Holding B.V. Method for forming an ultraviolet radiation responsive metal oxide-containing film
KR102636428B1 (ko) 2018-12-04 2024-02-13 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치를 세정하는 방법
US11158513B2 (en) 2018-12-13 2021-10-26 Asm Ip Holding B.V. Methods for forming a rhenium-containing film on a substrate by a cyclical deposition process and related semiconductor device structures
TW202037745A (zh) 2018-12-14 2020-10-16 荷蘭商Asm Ip私人控股有限公司 形成裝置結構之方法、其所形成之結構及施行其之系統
TWI819180B (zh) 2019-01-17 2023-10-21 荷蘭商Asm 智慧財產控股公司 藉由循環沈積製程於基板上形成含過渡金屬膜之方法
KR20200091543A (ko) 2019-01-22 2020-07-31 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치
KR20200102357A (ko) 2019-02-20 2020-08-31 에이에스엠 아이피 홀딩 비.브이. 3-d nand 응용의 플러그 충진체 증착용 장치 및 방법
KR102626263B1 (ko) 2019-02-20 2024-01-16 에이에스엠 아이피 홀딩 비.브이. 처리 단계를 포함하는 주기적 증착 방법 및 이를 위한 장치
JP2020136677A (ja) 2019-02-20 2020-08-31 エーエスエム・アイピー・ホールディング・ベー・フェー 基材表面内に形成された凹部を充填するための周期的堆積方法および装置
KR102638425B1 (ko) 2019-02-20 2024-02-21 에이에스엠 아이피 홀딩 비.브이. 기판 표면 내에 형성된 오목부를 충진하기 위한 방법 및 장치
JP2020133004A (ja) 2019-02-22 2020-08-31 エーエスエム・アイピー・ホールディング・ベー・フェー 基材を処理するための基材処理装置および方法
US20200283896A1 (en) * 2019-03-08 2020-09-10 Applied Materials, Inc. Methods for low temperature silicide formation
KR20200108242A (ko) 2019-03-08 2020-09-17 에이에스엠 아이피 홀딩 비.브이. 실리콘 질화물 층을 선택적으로 증착하는 방법, 및 선택적으로 증착된 실리콘 질화물 층을 포함하는 구조체
US11742198B2 (en) 2019-03-08 2023-08-29 Asm Ip Holding B.V. Structure including SiOCN layer and method of forming same
JP2020167398A (ja) 2019-03-28 2020-10-08 エーエスエム・アイピー・ホールディング・ベー・フェー ドアオープナーおよびドアオープナーが提供される基材処理装置
KR20200116855A (ko) 2019-04-01 2020-10-13 에이에스엠 아이피 홀딩 비.브이. 반도체 소자를 제조하는 방법
JP7203670B2 (ja) * 2019-04-01 2023-01-13 東京エレクトロン株式会社 成膜方法及び成膜装置
KR20200123380A (ko) 2019-04-19 2020-10-29 에이에스엠 아이피 홀딩 비.브이. 층 형성 방법 및 장치
KR20200125453A (ko) 2019-04-24 2020-11-04 에이에스엠 아이피 홀딩 비.브이. 기상 반응기 시스템 및 이를 사용하는 방법
KR20200130118A (ko) 2019-05-07 2020-11-18 에이에스엠 아이피 홀딩 비.브이. 비정질 탄소 중합체 막을 개질하는 방법
KR20200130121A (ko) 2019-05-07 2020-11-18 에이에스엠 아이피 홀딩 비.브이. 딥 튜브가 있는 화학물질 공급원 용기
KR20200130652A (ko) 2019-05-10 2020-11-19 에이에스엠 아이피 홀딩 비.브이. 표면 상에 재료를 증착하는 방법 및 본 방법에 따라 형성된 구조
JP2020188255A (ja) 2019-05-16 2020-11-19 エーエスエム アイピー ホールディング ビー.ブイ. ウェハボートハンドリング装置、縦型バッチ炉および方法
JP2020188254A (ja) 2019-05-16 2020-11-19 エーエスエム アイピー ホールディング ビー.ブイ. ウェハボートハンドリング装置、縦型バッチ炉および方法
USD947913S1 (en) 2019-05-17 2022-04-05 Asm Ip Holding B.V. Susceptor shaft
USD975665S1 (en) 2019-05-17 2023-01-17 Asm Ip Holding B.V. Susceptor shaft
KR20200141002A (ko) 2019-06-06 2020-12-17 에이에스엠 아이피 홀딩 비.브이. 배기 가스 분석을 포함한 기상 반응기 시스템을 사용하는 방법
KR20200143254A (ko) 2019-06-11 2020-12-23 에이에스엠 아이피 홀딩 비.브이. 개질 가스를 사용하여 전자 구조를 형성하는 방법, 상기 방법을 수행하기 위한 시스템, 및 상기 방법을 사용하여 형성되는 구조
KR102608830B1 (ko) * 2019-06-12 2023-11-30 어플라이드 머티어리얼스, 인코포레이티드 디바이스들 및 구조들을 제조하기 위한 선택적 방법들
USD944946S1 (en) 2019-06-14 2022-03-01 Asm Ip Holding B.V. Shower plate
JP2022539699A (ja) * 2019-06-24 2022-09-13 ラム リサーチ コーポレーション 選択的カーボン堆積
KR20210005515A (ko) 2019-07-03 2021-01-14 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치용 온도 제어 조립체 및 이를 사용하는 방법
JP2021015791A (ja) 2019-07-09 2021-02-12 エーエスエム アイピー ホールディング ビー.ブイ. 同軸導波管を用いたプラズマ装置、基板処理方法
CN112216646A (zh) 2019-07-10 2021-01-12 Asm Ip私人控股有限公司 基板支撑组件及包括其的基板处理装置
KR20210010307A (ko) 2019-07-16 2021-01-27 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치
KR20210010820A (ko) 2019-07-17 2021-01-28 에이에스엠 아이피 홀딩 비.브이. 실리콘 게르마늄 구조를 형성하는 방법
KR20210010816A (ko) 2019-07-17 2021-01-28 에이에스엠 아이피 홀딩 비.브이. 라디칼 보조 점화 플라즈마 시스템 및 방법
US11643724B2 (en) 2019-07-18 2023-05-09 Asm Ip Holding B.V. Method of forming structures using a neutral beam
CN112242296A (zh) 2019-07-19 2021-01-19 Asm Ip私人控股有限公司 形成拓扑受控的无定形碳聚合物膜的方法
CN114072544A (zh) * 2019-07-26 2022-02-18 应用材料公司 各向异性的外延生长
CN112309843A (zh) 2019-07-29 2021-02-02 Asm Ip私人控股有限公司 实现高掺杂剂掺入的选择性沉积方法
CN112309899A (zh) 2019-07-30 2021-02-02 Asm Ip私人控股有限公司 基板处理设备
CN112309900A (zh) 2019-07-30 2021-02-02 Asm Ip私人控股有限公司 基板处理设备
US11227782B2 (en) 2019-07-31 2022-01-18 Asm Ip Holding B.V. Vertical batch furnace assembly
US11587815B2 (en) 2019-07-31 2023-02-21 Asm Ip Holding B.V. Vertical batch furnace assembly
US11587814B2 (en) 2019-07-31 2023-02-21 Asm Ip Holding B.V. Vertical batch furnace assembly
CN112323048B (zh) 2019-08-05 2024-02-09 Asm Ip私人控股有限公司 用于化学源容器的液位传感器
USD965524S1 (en) 2019-08-19 2022-10-04 Asm Ip Holding B.V. Susceptor support
USD965044S1 (en) 2019-08-19 2022-09-27 Asm Ip Holding B.V. Susceptor shaft
JP2021031769A (ja) 2019-08-21 2021-03-01 エーエスエム アイピー ホールディング ビー.ブイ. 成膜原料混合ガス生成装置及び成膜装置
USD949319S1 (en) 2019-08-22 2022-04-19 Asm Ip Holding B.V. Exhaust duct
KR20210024423A (ko) 2019-08-22 2021-03-05 에이에스엠 아이피 홀딩 비.브이. 홀을 구비한 구조체를 형성하기 위한 방법
USD979506S1 (en) 2019-08-22 2023-02-28 Asm Ip Holding B.V. Insulator
USD940837S1 (en) 2019-08-22 2022-01-11 Asm Ip Holding B.V. Electrode
US11286558B2 (en) 2019-08-23 2022-03-29 Asm Ip Holding B.V. Methods for depositing a molybdenum nitride film on a surface of a substrate by a cyclical deposition process and related semiconductor device structures including a molybdenum nitride film
KR20210024420A (ko) 2019-08-23 2021-03-05 에이에스엠 아이피 홀딩 비.브이. 비스(디에틸아미노)실란을 사용하여 peald에 의해 개선된 품질을 갖는 실리콘 산화물 막을 증착하기 위한 방법
KR20210029090A (ko) 2019-09-04 2021-03-15 에이에스엠 아이피 홀딩 비.브이. 희생 캡핑 층을 이용한 선택적 증착 방법
KR20210029663A (ko) 2019-09-05 2021-03-16 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치
KR20210035449A (ko) 2019-09-24 2021-04-01 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US11562901B2 (en) 2019-09-25 2023-01-24 Asm Ip Holding B.V. Substrate processing method
CN112593212B (zh) 2019-10-02 2023-12-22 Asm Ip私人控股有限公司 通过循环等离子体增强沉积工艺形成拓扑选择性氧化硅膜的方法
TW202129060A (zh) 2019-10-08 2021-08-01 荷蘭商Asm Ip控股公司 基板處理裝置、及基板處理方法
KR20210043460A (ko) 2019-10-10 2021-04-21 에이에스엠 아이피 홀딩 비.브이. 포토레지스트 하부층을 형성하기 위한 방법 및 이를 포함한 구조체
KR20210045930A (ko) 2019-10-16 2021-04-27 에이에스엠 아이피 홀딩 비.브이. 실리콘 산화물의 토폴로지-선택적 막의 형성 방법
US11637014B2 (en) 2019-10-17 2023-04-25 Asm Ip Holding B.V. Methods for selective deposition of doped semiconductor material
KR20210047808A (ko) 2019-10-21 2021-04-30 에이에스엠 아이피 홀딩 비.브이. 막을 선택적으로 에칭하기 위한 장치 및 방법
KR20210050453A (ko) 2019-10-25 2021-05-07 에이에스엠 아이피 홀딩 비.브이. 기판 표면 상의 갭 피처를 충진하는 방법 및 이와 관련된 반도체 소자 구조
US11646205B2 (en) 2019-10-29 2023-05-09 Asm Ip Holding B.V. Methods of selectively forming n-type doped material on a surface, systems for selectively forming n-type doped material, and structures formed using same
KR20210054983A (ko) 2019-11-05 2021-05-14 에이에스엠 아이피 홀딩 비.브이. 도핑된 반도체 층을 갖는 구조체 및 이를 형성하기 위한 방법 및 시스템
US11501968B2 (en) 2019-11-15 2022-11-15 Asm Ip Holding B.V. Method for providing a semiconductor device with silicon filled gaps
KR20210062561A (ko) 2019-11-20 2021-05-31 에이에스엠 아이피 홀딩 비.브이. 기판의 표면 상에 탄소 함유 물질을 증착하는 방법, 상기 방법을 사용하여 형성된 구조물, 및 상기 구조물을 형성하기 위한 시스템
CN112951697A (zh) 2019-11-26 2021-06-11 Asm Ip私人控股有限公司 基板处理设备
KR20210065848A (ko) 2019-11-26 2021-06-04 에이에스엠 아이피 홀딩 비.브이. 제1 유전체 표면과 제2 금속성 표면을 포함한 기판 상에 타겟 막을 선택적으로 형성하기 위한 방법
CN112885693A (zh) 2019-11-29 2021-06-01 Asm Ip私人控股有限公司 基板处理设备
CN112885692A (zh) 2019-11-29 2021-06-01 Asm Ip私人控股有限公司 基板处理设备
JP2021090042A (ja) 2019-12-02 2021-06-10 エーエスエム アイピー ホールディング ビー.ブイ. 基板処理装置、基板処理方法
KR20210070898A (ko) 2019-12-04 2021-06-15 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치
US11885013B2 (en) 2019-12-17 2024-01-30 Asm Ip Holding B.V. Method of forming vanadium nitride layer and structure including the vanadium nitride layer
US11527403B2 (en) 2019-12-19 2022-12-13 Asm Ip Holding B.V. Methods for filling a gap feature on a substrate surface and related semiconductor structures
JP2021109175A (ja) 2020-01-06 2021-08-02 エーエスエム・アイピー・ホールディング・ベー・フェー ガス供給アセンブリ、その構成要素、およびこれを含む反応器システム
US11993847B2 (en) 2020-01-08 2024-05-28 Asm Ip Holding B.V. Injector
KR20210095050A (ko) 2020-01-20 2021-07-30 에이에스엠 아이피 홀딩 비.브이. 박막 형성 방법 및 박막 표면 개질 방법
TW202130846A (zh) 2020-02-03 2021-08-16 荷蘭商Asm Ip私人控股有限公司 形成包括釩或銦層的結構之方法
KR20210100010A (ko) 2020-02-04 2021-08-13 에이에스엠 아이피 홀딩 비.브이. 대형 물품의 투과율 측정을 위한 방법 및 장치
US11776846B2 (en) 2020-02-07 2023-10-03 Asm Ip Holding B.V. Methods for depositing gap filling fluids and related systems and devices
TW202146715A (zh) 2020-02-17 2021-12-16 荷蘭商Asm Ip私人控股有限公司 用於生長磷摻雜矽層之方法及其系統
TW202203344A (zh) 2020-02-28 2022-01-16 荷蘭商Asm Ip控股公司 專用於零件清潔的系統
US11876356B2 (en) 2020-03-11 2024-01-16 Asm Ip Holding B.V. Lockout tagout assembly and system and method of using same
KR20210116240A (ko) 2020-03-11 2021-09-27 에이에스엠 아이피 홀딩 비.브이. 조절성 접합부를 갖는 기판 핸들링 장치
KR20210117157A (ko) 2020-03-12 2021-09-28 에이에스엠 아이피 홀딩 비.브이. 타겟 토폴로지 프로파일을 갖는 층 구조를 제조하기 위한 방법
US11677013B2 (en) 2020-03-30 2023-06-13 Taiwan Semiconductor Manufacturing Co., Ltd. Source/drain epitaxial layers for transistors
KR20210124042A (ko) 2020-04-02 2021-10-14 에이에스엠 아이피 홀딩 비.브이. 박막 형성 방법
TW202146689A (zh) 2020-04-03 2021-12-16 荷蘭商Asm Ip控股公司 阻障層形成方法及半導體裝置的製造方法
TW202145344A (zh) 2020-04-08 2021-12-01 荷蘭商Asm Ip私人控股有限公司 用於選擇性蝕刻氧化矽膜之設備及方法
US11821078B2 (en) 2020-04-15 2023-11-21 Asm Ip Holding B.V. Method for forming precoat film and method for forming silicon-containing film
US11996289B2 (en) 2020-04-16 2024-05-28 Asm Ip Holding B.V. Methods of forming structures including silicon germanium and silicon layers, devices formed using the methods, and systems for performing the methods
KR20210132600A (ko) 2020-04-24 2021-11-04 에이에스엠 아이피 홀딩 비.브이. 바나듐, 질소 및 추가 원소를 포함한 층을 증착하기 위한 방법 및 시스템
KR20210132605A (ko) 2020-04-24 2021-11-04 에이에스엠 아이피 홀딩 비.브이. 냉각 가스 공급부를 포함한 수직형 배치 퍼니스 어셈블리
JP2021172884A (ja) 2020-04-24 2021-11-01 エーエスエム・アイピー・ホールディング・ベー・フェー 窒化バナジウム含有層を形成する方法および窒化バナジウム含有層を含む構造体
KR20210134226A (ko) 2020-04-29 2021-11-09 에이에스엠 아이피 홀딩 비.브이. 고체 소스 전구체 용기
KR20210134869A (ko) 2020-05-01 2021-11-11 에이에스엠 아이피 홀딩 비.브이. Foup 핸들러를 이용한 foup의 빠른 교환
KR20210141379A (ko) 2020-05-13 2021-11-23 에이에스엠 아이피 홀딩 비.브이. 반응기 시스템용 레이저 정렬 고정구
KR20210143653A (ko) 2020-05-19 2021-11-29 에이에스엠 아이피 홀딩 비.브이. 기판 처리 장치
KR20210145078A (ko) 2020-05-21 2021-12-01 에이에스엠 아이피 홀딩 비.브이. 다수의 탄소 층을 포함한 구조체 및 이를 형성하고 사용하는 방법
TW202200837A (zh) 2020-05-22 2022-01-01 荷蘭商Asm Ip私人控股有限公司 用於在基材上形成薄膜之反應系統
TW202201602A (zh) 2020-05-29 2022-01-01 荷蘭商Asm Ip私人控股有限公司 基板處理方法
TW202218133A (zh) 2020-06-24 2022-05-01 荷蘭商Asm Ip私人控股有限公司 形成含矽層之方法
TW202217953A (zh) 2020-06-30 2022-05-01 荷蘭商Asm Ip私人控股有限公司 基板處理方法
KR20220010438A (ko) 2020-07-17 2022-01-25 에이에스엠 아이피 홀딩 비.브이. 포토리소그래피에 사용하기 위한 구조체 및 방법
TW202204662A (zh) 2020-07-20 2022-02-01 荷蘭商Asm Ip私人控股有限公司 用於沉積鉬層之方法及系統
TW202212623A (zh) 2020-08-26 2022-04-01 荷蘭商Asm Ip私人控股有限公司 形成金屬氧化矽層及金屬氮氧化矽層的方法、半導體結構、及系統
USD990534S1 (en) 2020-09-11 2023-06-27 Asm Ip Holding B.V. Weighted lift pin
USD1012873S1 (en) 2020-09-24 2024-01-30 Asm Ip Holding B.V. Electrode for semiconductor processing apparatus
TW202229613A (zh) 2020-10-14 2022-08-01 荷蘭商Asm Ip私人控股有限公司 於階梯式結構上沉積材料的方法
KR20220053482A (ko) 2020-10-22 2022-04-29 에이에스엠 아이피 홀딩 비.브이. 바나듐 금속을 증착하는 방법, 구조체, 소자 및 증착 어셈블리
TW202223136A (zh) 2020-10-28 2022-06-16 荷蘭商Asm Ip私人控股有限公司 用於在基板上形成層之方法、及半導體處理系統
TW202235675A (zh) 2020-11-30 2022-09-16 荷蘭商Asm Ip私人控股有限公司 注入器、及基板處理設備
US11946137B2 (en) 2020-12-16 2024-04-02 Asm Ip Holding B.V. Runout and wobble measurement fixtures
TW202231903A (zh) 2020-12-22 2022-08-16 荷蘭商Asm Ip私人控股有限公司 過渡金屬沉積方法、過渡金屬層、用於沉積過渡金屬於基板上的沉積總成
USD981973S1 (en) 2021-05-11 2023-03-28 Asm Ip Holding B.V. Reactor wall for substrate processing apparatus
USD980814S1 (en) 2021-05-11 2023-03-14 Asm Ip Holding B.V. Gas distributor for substrate processing apparatus
USD980813S1 (en) 2021-05-11 2023-03-14 Asm Ip Holding B.V. Gas flow control plate for substrate processing apparatus
USD1023959S1 (en) 2021-05-11 2024-04-23 Asm Ip Holding B.V. Electrode for substrate processing apparatus
USD990441S1 (en) 2021-09-07 2023-06-27 Asm Ip Holding B.V. Gas flow control plate

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7176109B2 (en) * 2001-03-23 2007-02-13 Micron Technology, Inc. Method for forming raised structures by controlled selective epitaxial growth of facet using spacer
JP4369359B2 (ja) * 2004-12-28 2009-11-18 富士通マイクロエレクトロニクス株式会社 半導体装置
US8030108B1 (en) * 2008-06-30 2011-10-04 Stc.Unm Epitaxial growth of in-plane nanowires and nanowire devices
US8598003B2 (en) * 2009-12-21 2013-12-03 Intel Corporation Semiconductor device having doped epitaxial region and its methods of fabrication
US8263451B2 (en) 2010-02-26 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Epitaxy profile engineering for FinFETs
US8659032B2 (en) * 2012-01-31 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET and method of fabricating the same
JP5815443B2 (ja) * 2012-03-19 2015-11-17 株式会社日立国際電気 半導体装置の製造方法、基板処理方法および基板処理装置
US8497177B1 (en) * 2012-10-04 2013-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a FinFET device
US20140120678A1 (en) * 2012-10-29 2014-05-01 Matheson Tri-Gas Methods for Selective and Conformal Epitaxy of Highly Doped Si-containing Materials for Three Dimensional Structures
US9142633B2 (en) * 2012-12-13 2015-09-22 GlobalFoundries, Inc. Integrated circuits and methods for fabricating integrated circuits with silicide contacts on non-planar structures
US9812556B2 (en) * 2012-12-28 2017-11-07 Renesas Electronics Corporation Semiconductor device and method of manufacturing the semiconductor device
US20150170916A1 (en) * 2013-12-17 2015-06-18 United Microelectronics Corp. Semiconductor process for manufacturing epitaxial structures

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI748021B (zh) * 2016-12-12 2021-12-01 美商應用材料股份有限公司 形成應變通道層的方法
TWI812984B (zh) * 2016-12-12 2023-08-21 美商應用材料股份有限公司 形成應變通道層的方法
TWI658178B (zh) * 2017-06-23 2019-05-01 上海新昇半導體科技有限公司 一種半導體元件及其製造方法、電子裝置

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