CN113950736A - 用于制造器件及结构的选择性方法 - Google Patents

用于制造器件及结构的选择性方法 Download PDF

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CN113950736A
CN113950736A CN202080042756.6A CN202080042756A CN113950736A CN 113950736 A CN113950736 A CN 113950736A CN 202080042756 A CN202080042756 A CN 202080042756A CN 113950736 A CN113950736 A CN 113950736A
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processing chamber
epitaxial layer
substrate
processing
etching
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黄奕樵
吴贞莹
阿布舍克·杜贝
秦嘉政
索拉布·乔普拉
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Applied Materials Inc
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Abstract

本文描述的一个或多个实施方式涉及用于制造器件及结构的选择性方法。在这些实施方式中，器件暴露在处理腔室的处理空间内。前驱物气体以一定的流量比并在一定的处理条件下在处理空间中流动。本文所述的处理条件导致在对应于每个鳍片顶部的器件晶面的{100}面上的选择性的外延层生长。另外，处理条件导致对应于每个鳍片侧壁的晶面的{110}面的选择性蚀刻。因此，本文所述的方法提供了在不同晶面处生长或蚀刻外延膜的方法。此外，本文所述的方法允许在不同的晶面上同时发生外延膜生长和蚀刻。

Description

用于制造器件及结构的选择性方法
技术领域
本文描述的一个或多个实施方式通常涉及半导体制造，并且更具体地，涉及用于制造半导体器件及结构的选择性方法。
现有技术描述
随着下一代器件的电路密度的增加，互连(诸如过孔、沟槽、接点、栅极结构和其他特征)以及它们之间的介电质材料的宽度减小。然而，介电层的厚度保持基本恒定，导致特征的深宽比增加。近来，例如已经将FinFET器件的互补式金属氧化物半导体(CMOS)引入到各种不同类型的半导体器件中。
FinFET器件通常包括具有高深宽比的半导体鳍片，其中在所述半导体鳍片上形成用于晶体管的沟道和源极/漏极区。随后利用沟道和源极/漏极区域的表面积增加的优点，在鳍片器件的侧部上方并沿着鳍片器件的侧部形成栅电极，以生产更快、更可靠且控制得更好的半导体晶体管器件。FinFET的其他优势包括减少短沟道效应并提供更高的电流。
随着规模的不断扩大和架构的发展，将源极/漏极接点插头直接连接到FinFET器件中的窄鳍片和具有窄垂直侧壁的凹陷结构上一直是一个挑战。外延层已用于增加体积，以实现更好的接触。沿晶体管沟道方向观察时，典型的硅(Si)外延膜面具有{111}平面，呈菱形。具有主要{111}小面的外延膜可能是不利的，因为侧壁上的横向生长阻止了相邻鳍片或侧壁的进一步距离减小。通常，当器件具有多个鳍片FinFET或多个垂直侧壁时，每个外延层的菱形会合并。合并的外延层会形成空隙，从而导致器件缺陷。
因此，需要选择性生长外延膜的方法，使得侧壁上的横向生长减小。
发明内容
本文描述的一个或多个实施方式涉及用于制造半导体器件及结构的选择性方法。
在一个实施方式中，一种在处理腔室中处理基板的方法，包括以下步骤：将具有一个或多个鳍片的基板暴露于处理腔室的处理空间中；引导前驱物气体进入处理腔室中；在一个或多个鳍片的每个鳍片的顶面上生长一个外延层；及蚀刻一个或多个鳍片的每个鳍片的表面；其中生长外延层和蚀刻侧壁表面是同时发生的。
在另一个实施方式中，在处理腔室中处理基板的方法包括以下步骤：将具有带垂直侧壁的凹陷结构的基板暴露于处理腔室的处理空间中；引导前驱物气体进入处理腔室中；在每个垂直侧壁之间的基板的水平部分上生长外延层；及蚀刻每个垂直侧壁的表面，其中生长外延层与蚀刻垂直侧壁的表面同时发生。
在另一个实施方式中，在处理腔室中处理基板的方法包括以下步骤：将具有一个或多个鳍片的基板暴露于处理腔室的处理空间中，其中一个或多个鳍片的每个鳍片具有{100}平面和{110}平面；引导前驱物气体进入处理腔室中；在一个或多个鳍片的每个鳍片的{100}平面上生长外延层；及蚀刻所述一个或多个鳍片中的每个鳍片的{110}平面；其中生长外延层和蚀刻侧壁表面是同时发生的。
附图说明
为了可以详细地理解本公开内容的上述特征，可以通过过参考实施方式而对上方简要概述的本公开内容进行更特定的描述，其中一些实施方式在附图中示出。然而，应当注意，附图仅示出了本公开内容的典型实施方式，并且因此不应被认为是对本公开范围的限制，因为本公开内容可以允许其他等效的实施方式。
图1是根据本文所述的至少一个实施方式的处理系统的示意图；
图2A是根据本文所述的至少一个实施方式的FinFET器件的截面示意图；
图2B是在图2A中所示的线2B-2B处切开的FinFET器件的截面图；
图3是根据现有技术的FinFET器件的截面图；
图4是根据本文所述的至少一个实施方式的方法的流程图；
图5A-5B显示图4中描述的方法的一些文字块处的FinFET器件；
图6是根据本文所述的至少一个实施方式方法的流程图；及
图7A-7B显示图6中描述的方法的一些文字块处的凹陷结构。
为了便于理解，在可能的地方使用了相同的元件符号来表示图中共有的相同元件。可以预期一个实施方式的元件和特征可有益地并入其他实施方式中，而无需进一步叙述。
具体实施方式
在以下描述中，阐述了许多具体细节以提供对本公开内容的实施方式的更透彻的理解。然而，对于本领域的技术人员将显而易见的是，可以在没有这些具体细节中的一者或多者的情况下实践本公开内容的一个或多个实施方式。在其他情况下，未描述众所周知的特征，以避免模糊本公开内容的一个或多个实施方式。
本文描述的一个或多个实施方式涉及用于制造半导体器件及结构的选择性方法。在这些实施方式中，器件及结构暴露在处理腔室的处理空间内。随后将前驱物气体引入处理腔室的处理空间内。前驱物气体的反应导致不同晶面上的外延膜生长。如上所述，在常规实施方式中，外延膜在多鳍片FinFET器件的每个鳍片上或在凹陷结构的垂直侧壁上横向生长，从而减小了每个鳍片或垂直侧壁之间的宽度。横向生长有时会导致外延层合并在一起。外延层的合并会形成空隙，从而导致器件缺陷并降低性能。
在本文所述的实施方式中，前驱物气体以一定的流量比并在一定的处理条件下在处理腔室的处理空间中流动。本文所述的处理条件导致在对应于多鳍片FinFET器件的每个鳍片的顶部或凹陷结构的垂直侧壁的FinFET器件或凹陷结构的晶面的{100}平面上选择性的外延层生长。另外，处理条件导致对应于每个器件的侧壁的晶面的{110}平面的选择性蚀刻。因此，本文所述的方法提供了在不同晶面处生长或蚀刻外延膜的方法。感兴趣的膜可以在某些晶面上生长，但在某些其他平面上蚀刻。另外，本文描述的方法允许在不同的晶面上同时发生外延膜生长和蚀刻，从而实现某些形状的晶体形式。与常规实施方式中所需的依序生长和蚀刻工艺相比，同时生长和蚀刻提供了更快的处理量和更好的工艺控制。
图1是可用于执行本文描述的方法的处理系统100的截面图。处理系统100包括处理腔室主体102、支持系统104与控制器106。处理腔室主体102包括上部112和下部114。上部112包括位于上穹顶116和基板115之间的处理腔室主体102内的区域。下部114包括下圆顶117和基板115的底部之间的处理腔室主体102内的区域。沉积工艺通常发生在上部112内的基板115的上表面上。
支持系统104包括用于执行和监视预定工艺(例如，在处理腔室主体102中外延膜的生长)的部件。控制器106耦接至支持系统104并适以控制处理系统100与支持系统104。控制器106包括中央处理单元(CPU)、存储器与支持电路。
处理系统100包括多个热源(例如，灯118)，所述多个热源适以向位于处理腔室主体102内的部件提供热能。例如，灯118可适以向基板115、基座120和/或预热环122提供热能。下圆顶117可由例如石英的光学透明材料形成，以促进热辐射从中通过。可以想到的是，灯118可经定位以透过上穹顶116以及下圆顶117提供热能。
处理腔室主体102还包括形成在处理腔室主体102中的多个气室。气室与一个或多个气体源124(例如，载气)和一个或多个前驱物源126(例如，沉积气体和掺杂物气体)处于流体连通中。例如，第一气室148可适以提供穿过其中的沉积气体162进入处理腔室主体102的上部112中，而第二气室160可适以从上部112排出沉积气体162。以这种方式，沉积气体162可以平行于基板115的上表面流动。
在使用液体前驱物(例如，四硅烷)的情况下，处理系统100可包括与液体前驱物源128流体连通的液体蒸发器130。液体蒸发器130用于汽化将被输送到处理系统100的液体前驱物。尽管未示出，但是可以预期，液体前驱物源128可包括例如前驱物液体和溶剂液体的一个或多个安瓿、截止阀和液体流量计(LFM)。
基板支撑组件132位于处理腔室主体102的下部114中。示出了将基板115支撑在处理位置的基板支撑组件132。基板支撑组件132包括由光学透明材料形成的基座支撑轴134和由基座支撑轴134支撑的基座120。基座支撑轴134的轴136位于护罩138内，且升降杆接点140耦接至轴136。基座支撑轴134可旋转以便于在处理期间旋转基板115。由耦接到基座支撑轴134的致动器142促进了基座支撑轴134的旋转。护罩138通常固定在适当的位置，因此在处理期间不旋转。支撑杆144耦接基座支撑轴134至基座120。
升降杆146经设置通过在基座支撑轴134中形成的开口(未标记)。升降杆146是可垂直致动的，并且适以与基板115的下侧接触，以将基板115从处理位置(如图所示)提升到基板移除位置。
预热环122可移除地设置在下部衬套147上，而下部衬套147耦接至处理腔室主体102。预热环122围绕处理腔室主体102的内部空间设置，并且在基板115处于处理位置时围绕基板115。当处理气体通过邻近预热环122的第一气室148进入处理腔室主体102时，预热环122有助于对处理气体进行预热。
上穹顶116的中央窗部分150和下圆顶117的底部部分152可以由例如石英的光学透明材料形成。上穹顶116的周边凸缘154(围绕中央窗部分150的圆周接合中央窗部分150)、下圆顶117的周边凸缘156(围绕底部部分的圆周接合底部部分)可全部由不透明的石英制成，以防止靠近周边凸缘的O形环158直接暴露于热辐射中。周边边缘154可以由例如石英的光学透明材料形成。
根据本文所述至少一个实施方式，图2A是FinFET器件200的截面示意图，而图2B是在图2A中所示的线2B-2B处切开的FinFET器件200的截面图。在这些实施方式中，基板115包括垂直鳍片202与介电层204。基板115可为块状Si基板、绝缘体上硅(SOI)基板、锗(Ge)基板或类似物。垂直鳍片202从基板115的上表面垂直延伸。垂直鳍片202可以通过掩模和蚀刻基板115的上表面而形成，从而形成垂直鳍片202。然而，在其他实施方式中，也可以考虑其他形成方法。介电层204有助于在基板115上形成的器件之间的电隔离。如图2A-2B中所示，垂直鳍片202在介电层204的上表面上方延伸一定距离。在一些实施方式中，介电层204是由二氧化硅(SiO2)、氮化硅(Si3N4)、或氧氮化硅(SiOxNy)中的一者或多者所形成。然而，在其他实施方式中，也可考虑其他介电质材料。
图3是现有技术FinFET器件300的截面图。在常规实施方式中，如上所述和图3所示，外延层304在FinFET器件300中的每个鳍片302上横向生长，从而减小了每个鳍片302之间的宽度。横向生长有时导致外延层304合并在一起。外延层304的合并会形成空隙，从而导致器件缺陷并降低性能。因此，图3所示的配置经常有问题并且需要改进，而改进在以下描述的实施方式中提供。
图4是根据本文描述的至少一个实施方式方法400的流程图。在这些实施方式中，方法400是用图1-2B中描述的系统和器件来执行的，但不限于这些系统和器件，并且可以用其他类似的系统和器件来执行。图5A-5B显示图4中描述的方法400的一些文字块处的FinFET器件500。
在文字块402中，具有一个或多个鳍片502的FinFET器件500暴露于处理腔室主体102。在一些实施方式中，处理腔室102的温度等于或低于约摄氏700度(℃)，例如介于约350℃与约700℃之间。另外，在一些实施方式中，处理腔室处于等于或低于10托的压力下，例如介于约5托和约10托之间。
在文字块404中，将前驱物引导进入处理腔室主体102中。如上面论述且如图1中所示，前驱物进入处理腔室主体102。在这些实施方式中，载气用于将蒸汽输送到处理腔室102中。在一个实施方式中，载气为氢(H2)。然而，在其他实施方式中，可使用氮(N2)作为载气。载气流动速率可在约100sccm与约1000sccm之间。在一些实施方式中，前驱物为含硅(Si)前驱物并可包括硅烷(SiH4)。然而，在其他实施方式中，可使用具有经验式SixH(2X+2)的高阶硅烷，诸如二硅烷(Si2H6)、三硅烷(Si3H8)与四硅烷(Si4H10)或其他较高阶硅烷(例如，聚氯硅烷)。此外，在一些实施方式中，前驱物是含锗(Ge)前驱物并可包括氯化气体或液体，例如四氯化锗(GeCl4)。然而，在其他实施方式中，可使用其他氯化锗烷气体或液体，诸如二氯锗烷(GeH2Cl2)、三氯锗烷(GeHCl3)、六氯二锗烷(Ge2Cl6)、或上述的任何两种或更多种的组合。除了前驱物以外，在这些实施方式中，使用二硼烷(B2H6)作为掺杂物。然而，在其他实施方式中，可使用其他掺杂物，诸如膦(PH3)或胂(AsH3)。
在文字块406中，如图5A所示，在鳍片502的顶表面与侧壁表面上生长外延层504。鳍片502的顶表面对应于FinFET器件500的晶面的{100}平面。鳍片502的侧壁表面对应于FinFET器件500的晶面的{110}平面。前驱物分子506的化学作用形成在鳍片502的顶表面和侧壁表面上生长的外延层504。例如，在这些实施方式中，硅烷(SiH4)与四氯化锗(GeCl4)可为用于在鳍片502的表面上生长外延层504的前驱物分子506。尽管正在发生生长，但GeCl4中的氯(Cl)原子可同时作用以蚀刻外延层504。在鳍片502的侧壁上，蚀刻发生速率比生长更大，从而防止了在侧壁上生长的积累。因此，防止如图3中所描述的在常规实施方式中可能发生的外延层504的横向生长。这样，在多鳍片结构中防止了外延层504的合并，从而防止了器件缺陷并改善了器件性能。然而，当使用SiH4和GeCl4前驱物分子506时，在顶表面上的生长的发生速率大于蚀刻，这允许外延层504的生长累积在鳍片502的顶表面上。在一些实施方式中，鳍片502的顶表面上的外延层504的生长速率可在约
Figure BDA0003403808150000071
与约
Figure BDA0003403808150000072
Figure BDA0003403808150000073
之间。因此，方法400允许在不同的晶面上同时发生外延膜生长和蚀刻，从而获得某些晶体形式和形状。与常规实施方式中所需的依序生长和蚀刻工艺相比，同时生长和蚀刻可提供更快的处理量和更好的工艺控制。
按照方法400，在图5B中示出了所得的FinFET器件500。所得的FinFET器件500包括在鳍片502的顶部表面上形成的外延层504。然而，所得的FinFET器件500在FinFET器件500的侧壁上没有形成外延层504。因此，方法400有利地导致在例如FinFET器件500的FinFET器件上的选择性外延生长。在这些实施方式中，所得的外延层504可介于约10nm与约30nm之间，例如约20nm。
图6根据本文描述的至少一个实施方式是方法600的流程图。在这些实施方式中，方法600是用图1-2B中描述的系统和器件来执行的，但不限于这些系统和器件，并且可以用其他类似的系统和器件来执行。图7A-7B显示图6中描述的方法600的一些文字块处的凹陷结构700。
在文字块602中，具有基板702的凹陷结构700暴露于处理腔室主体102中。基板702包括垂直侧壁704。在一些实施方式中，处理腔室102的温度等于或低于约摄氏700度(℃)，例如介于约350℃与约700℃之间。另外，在一些实施方式中，处理腔室处于等于或低于10托的压力下，例如介于约5托和约10托之间。
在文字块604中，将前驱物引导进入处理腔室主体102中。如上面论述且如图1中所示，前驱物进入处理腔室主体102。在这些实施方式中，载气用于将蒸汽输送到处理腔室102中。在一个实施方式中，载气为氢(H2)。然而，在其他实施方式中，可使用氮(N2)作为载气。载气流动速率可在约100sccm与约1000sccm之间。在一些实施方式中，前驱物为含硅(Si)前驱物并可包括硅烷(SiH4)。然而，在其他实施方式中，可使用具有经验式SixH(2X+2)的高阶硅烷，诸如二硅烷(Si2H6)、三硅烷(Si3H8)与四硅烷(Si4H10)或其他较高阶硅烷(例如，聚氯硅烷)。此外，在一些实施方式中，前驱物是含锗(Ge)前驱物并可包括氯化气体或液体，例如四氯化锗(GeCl4)。然而，在其他实施方式中，可使用其他氯化锗烷气体或液体，诸如二氯锗烷(GeH2Cl2)、三氯锗烷(GeHCl3)、六氯二锗烷(Ge2Cl6)、或上述的任何两种或更多种的组合。除了前驱物以外，在这些实施方式中，使用二硼烷(B2H6)作为掺杂物。然而，在其他实施方式中，可使用其他掺杂物，诸如膦(PH3)或胂(AsH3)。
在文字块606中，如图7A所示，外延层706直接生长在每个垂直侧壁704之间的基板702上，并直接生长在垂直侧壁704上。每个垂直侧壁704之间的水平面对应于凹陷结构700的晶面的{100}平面。垂直侧壁704对应于凹陷结构700的晶面的{110}平面。前驱物分子708的化学作用形成外延层706，所述外延层706在每个垂直侧壁704之间的基板702的水平部分和直接在垂直侧壁704上生长。例如，在这些实施方式中，硅烷(SiH4)与四氯化锗(GeCl4)可为用于在基板702的表面上生长外延层706的前驱物分子708。尽管正在发生生长，但氯(Cl)原子可同时作用以蚀刻外延层706。在垂直侧壁704上，蚀刻发生速率比生长大，从而防止了在垂直侧壁704上外延层706生长的积累。因此，防止如图3中所描述的在常规实施方式中可能发生的外延层706的横向生长。这样，在凹陷结构中防止了外延层706的合并，从而防止了器件缺陷并改善了器件性能。然而，当使用SiH4和GeCl4前驱物分子708时，在垂直侧壁704之间的水平表面处的生长的发生速率大于蚀刻，这允许外延层706的生长累积在每个垂直侧壁704之间的水平表面上。在一些实施方式中，在每个垂直侧壁704之间的外延层706的生长速率可在约
Figure BDA0003403808150000081
与约
Figure BDA0003403808150000082
之间。因此，方法600允许在不同的晶面上同时发生外延膜生长和蚀刻，从而获得某些晶体形式和形状。与常规实施方式中所需的依序生长和蚀刻工艺相比，同时生长和蚀刻可提供更快的处理量和更好的工艺控制。此外，外延层706在每个垂直侧壁704之间的生长提供了更平坦的外延层706顶部，更易于抛光。
按照方法600，在图7B中示出了所得的凹陷结构700。所得的凹陷结构700包括在每个垂直侧壁704之间的基板702的水平部分上形成的外延层706。然而，所得的凹陷结构700在垂直侧壁704上没有形成外延层706。因此，方法600有利地导致在例如凹陷结构700的凹陷结构上的选择性外延生长。在这些实施方式中，所得的外延层可介于约10nm与约30nm之间，例如约20nm。
尽管前述内容针对本发明的实现，但是在不脱离本发明的基本范围的情况下，可以设计本发明的其他和进一步的实现，并且本发明的范围由所附权利要求书确定。

Claims (20)

1.一种在处理腔室中处理基板的方法，包括以下步骤：
暴露具有一个或多个鳍片的所述基板进入所述处理腔室的处理空间中；
引导前驱物气体进入所述处理腔室中；
在所述一个或多个鳍片的每个鳍片的顶表面上生长外延层；以及
蚀刻所述一个或多个鳍片的每个鳍片的侧壁表面，其中生长所述外延层与蚀刻所述侧壁表面同时发生。
2.如权利要求1所述的方法，其中所述前驱物气体包括硅烷(SiH4)与四氯化锗(GeCl4)。
3.如权利要求2所述的方法，所述方法进一步包括在所述处理腔室中的掺杂物气体。
4.如权利要求1所述的方法，其中将所述处理腔室加热至约350℃与约700℃之间的温度。
5.如权利要求1所述的方法，其中将所述处理腔室控制在约5托与约10托之间的压力下。
6.如权利要求1所述的方法，其中所述外延层在约
Figure FDA0003403808140000011
与约
Figure FDA0003403808140000012
之间的生长速率下生长。
7.如权利要求1所述的方法，其中具有所述一个或多个鳍片的所述基板包括鳍式场效晶体管(FinFET)器件。
8.一种在处理腔室中处理基板的方法，包括以下步骤：
暴露具有带有垂直侧壁的凹陷结构的所述基板进入所述处理腔室的处理空间中；
引导前驱物气体进入所述处理腔室中；
在所述垂直侧壁的每个垂直侧壁之间的所述基板的水平部分上生长外延层；以及
蚀刻所述垂直侧壁的每个垂直侧壁的表面，其中生长所述外延层与蚀刻所述垂直侧壁的表面同时发生。
9.如权利要求8所述的方法，其中所述前驱物气体包括硅烷(SiH4)与四氯化锗(GeCl4)。
10.如权利要求9所述的方法，所述方法进一步包括在所述处理腔室中的掺杂物气体。
11.如权利要求8所述的方法，其中将所述处理腔室加热至约350℃与约700℃之间的温度。
12.如权利要求8所述的方法，其中将所述处理腔室控制在约5托与约10托之间的压力下。
13.如权利要求8所述的方法，其中所述外延层在约
Figure FDA0003403808140000021
与约
Figure FDA0003403808140000022
之间的生长速率下生长。
14.如权利要求8所述的方法，其中所述垂直侧壁包括两个垂直侧壁。
15.一种在处理腔室中处理基板的方法，包括以下步骤：
暴露具有一个或多个鳍片的所述基板进入所述处理腔室的处理空间中，其中所述一个或多个鳍片的每个鳍片具有{100}平面与{110}平面；
引导前驱物气体进入所述处理腔室中；
在所述一个或多个鳍片的每个鳍片的所述{100}平面上生长外延层；以及
蚀刻所述一个或多个鳍片的每个鳍片的所述{110}平面，其中生长所述外延层与蚀刻所述侧壁表面同时发生。
16.如权利要求15所述的方法，其中所述前驱物气体包括硅烷(SiH4)与四氯化锗(GeCl4)。
17.如权利要求16所述的方法，所述方法进一步包括在所述处理腔室中的掺杂物气体。
18.如权利要求15所述的方法，其中将所述处理腔室加热至约350℃与约700℃之间的温度。
19.如权利要求15所述的方法，其中将所述处理腔室控制在约5托与约10托之间的压力下。
20.如权利要求15所述的方法，其中所述外延层在约
Figure FDA0003403808140000023
与约
Figure FDA0003403808140000024
之间的生长速率下生长。
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