CN106663684B - 具有自对准背侧特征的半导体器件 - Google Patents

具有自对准背侧特征的半导体器件 Download PDF

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CN106663684B
CN106663684B CN201580041881.4A CN201580041881A CN106663684B CN 106663684 B CN106663684 B CN 106663684B CN 201580041881 A CN201580041881 A CN 201580041881A CN 106663684 B CN106663684 B CN 106663684B
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insulator
region
layer
semiconductor
grid
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CN106663684A (zh
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S·A·法内利
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Qualcomm Inc
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Abstract

提供了涉及绝缘体上半导体工艺上的自对准特征的各种方法和器件。一种示例性方法包括在绝缘体上半导体晶片上形成栅极。该绝缘体上半导体晶片包括器件区、埋藏绝缘体和基板。该示例性方法进一步包括使用该栅极作为掩模向该绝缘体上半导体晶片应用处理。该处理在该埋藏绝缘体中创建了经处理的绝缘体区。该示例性方法还包括移除基板的至少一部分。该示例性方法还包括，在移除基板的该部分之后，从该埋藏绝缘体选择性地移除经处理的绝缘体区以形成剩余的绝缘体区。

Description

具有自对准背侧特征的半导体器件
相关申请
本申请要求2014年8月6日提交且题为“SEMICONDUCTOR DEVICE WITH SELF-ALIGNED BACK SIDE FEATURES(具有自对准背侧特征的半导体器件)”的美国非临时专利申请No.14/453,595的优先权，该专利申请由此出于所有目的通过引用纳入于此。
发明背景
以不断减小的几何尺寸以及以更低的成本来生产半导体器件在长久以来被认为是对于数字化时代的广泛益处的关键贡献因素之一。半导体器件的成本很大程度上取决于基板的大小、随着基板被处理而消耗的材料的成本，以及取决于可分派给每个部分的资本开销量。成本的前两个贡献因素可以通过减小器件的大小，以及通过使用现成可用的材料来减小。资本开销成本可以通过使用现成可用的制造装备，以及通过发展消除对于更多外来装备的需求以及减少建造每个器件所花费的时间的处理技术来减小。这些处理技术有时与提供如何制作器件的证据的不同制造特征相关联。
自对准栅极是指示可以参照图1来描述的特定处理技术的制造特征。半导体晶片100包括被栅极102覆盖的基板101。如所解说的，栅极102包括光掩模103、栅电极104和栅极绝缘体105。在该工艺中的该点，光掩模103被用来创建栅极堆叠。换言之，栅电极104和栅极绝缘体105先前具有附加部分，使得它们跨基板101的表面横向延伸。光掩模103随后被用来遮蔽栅极堆叠，而那些附加的部分被移除。一旦栅极102形成，光掩模103就可以在另一处理步骤中投入使用。如图1中所解说的，栅极102可以用作遮蔽沟道107的掩模，而晶片100暴露于掺杂剂108的扩散。结果是，光掩模103不仅可以被用来形成栅极堆叠，也可以被用来创建晶体管109的源极区和漏极区。因此，对于栅极堆叠102和源极区与漏极区109的创建不要求不同的掩模。
除了减少所要求的处理步骤的数目之外，自对齐栅极工艺产生的附加益处在于，与根据特定替换性处理方法体系形成的器件相比，结果所得的器件具有优越的特性。晶体管的性能受到晶体管的栅极、沟道、源极和漏极区的相互依赖的直接影响。具体而言，严格控制源极-沟道结和漏极-沟道结相对于晶体管的栅极的位置是重要的。由于在自对准栅极工艺中同一掩模被用来形成栅极堆栈和源极与漏极区二者，所以消除了由于两个不同掩模未对准而造成的误差。自对准栅极工艺因此提供了更为成本有效的且功能优越的器件。
发明概述
在一个实施例中，一种方法包括在绝缘体上半导体晶片上形成栅极。该绝缘体上半导体晶片包括器件区、埋藏绝缘体和基板。该方法还包括使用该栅极作为掩模向该绝缘体上半导体晶片应用处理。该处理在该埋藏绝缘体中创建了经处理的绝缘体区。该方法还包括移除基板的至少一部分。该方法还包括，在移除基板的该部分之后，从该埋藏绝缘体选择性地移除经处理的绝缘体区以形成剩余的绝缘体区。
在另一个实施例中，一种方法包括在绝缘体上半导体晶片上形成栅极。该绝缘体上半导体晶片包括器件区、埋藏绝缘体和基板。该示例性方法进一步包括使用该栅极作为掩模向该绝缘体上半导体晶片应用处理。该处理在该埋藏绝缘体中创建了经处理的绝缘体区。该示例性方法还包括移除基板的至少一部分。该示例性方法还包括，在移除基板的该部分之后，从该埋藏绝缘体选择性地移除经处理的绝缘体区以形成剩余的绝缘体区。
在另一个实施例中，一种半导体器件包括形成在绝缘体上半导体晶片上的栅极。该绝缘体上半导体晶片包括器件区和埋藏绝缘体。该栅极形成在该器件区的顶侧上。该器件区的厚度小于100纳米。该器件区还包括沉积层，该沉积层位于：(i)该埋藏绝缘体的挖出区域中；(ii)该器件区的背侧上；以及(iii)沿该埋藏绝缘体的剩余区域的垂直边沿。该栅极的垂直边沿在误差余裕内对准到该埋藏绝缘体的剩余区域的垂直边沿。该误差余裕小于80纳米。
图2解说了绝缘体上半导体(SOI)结构200，该结构包括绝缘体上半导体晶片201、接触层202和金属化层203。SOI晶片201进而包括基板204、绝缘体层205，和有源器件层206。基板204可以是半导体材料，诸如硅。绝缘体层205可以是电介质，诸如通过基板204氧化形成的二氧化硅。有源器件层206可包括进行器件200的信号处理和功率操作的晶体管。如所绘出的，栅极207用作晶体管的栅极，该晶体管在有源器件层206中具有紧邻栅极207之下的沟道。有源器件层206经由接触层202耦合到金属化层203。这些层可包括掺杂剂、电介质、多晶硅、金属导线、钝化层以及在电路系统形成于其中之后呈现的其它层、材料或组件的组合。该电路系统包括金属导线，无源器件(诸如电阻器、电容器和电感器)；以及有源器件(诸如晶体管和二极管)。
如本文中以及所附权利要求中所使用的，SOI结构200的“顶部”是指顶面208，而SOI结构200的“底部”是指底面209。无论SOI结构200与其他参考框架的相对取向如何，是从SOI结构200移除层还是向SOI结构200增加层，该取向方案都持续不变。因此，有源层206总是在绝缘体层205“上方”。此外，无论SOI结构200与其他参考框架的相对取向如何，是从SOI结构200移除层还是向SOI结构200增加层，源自有源层206的中心并向底面209延伸的向量将总是指向SOI结构200的“背侧”方向。
附图简述
图1解说了用于形成晶体管的源极和漏极的自对准注入。
图2解说了绝缘体上半导体结构。
图3解说了用于生产具有自对准背侧特征的半导体器件的工艺的流程图。
图4A-E解说了参照图3所解说的工艺的不同阶段的半导体结构。
图5解说了晶体管的沟道上的自对准背侧应变层的效应。
图6解说了用于生产具有双栅极晶体管和自对准背侧特征的半导体器件的工艺的流程图。
图7A-E解说了参照图6所解说的工艺的不同阶段的半导体结构。
实施例详细描述
现在将详细参考所公开的发明的各实施例，其一个或多个示例在附图中得以解说。藉由本技术的解释而非作为本技术的限定来提供每个示例。实际上，将对本领域技术人员明显的是，可在本技术中作出修改和变形而不会脱离本技术的精神和范围。例如，作为一个实施例的一部分来解说或描述的特征可与另一实施例联用以产生又进一步的实施例。由此，本主题内容旨在涵盖所附权利要求书及其等效技术方案的范围内的全部此类修改和变形。
绝缘体上半导体(SOI)结构200的有源器件层206对于结构200作为其一部分的半导体器件的性能而言是关键的区域。为了创建具有期望特性的有源器件，需要作出努力来保护器件层不受向该有源层引入过度的变化的处理步骤的损害。例如，不破坏有源器件层206和绝缘体层205之间的界面一般是有益的。具体而言，在沟道要在其中形成的有源器件层206的区域中，该界面的中断可以产生将改变栅极207的栅电极中的电压和沟道区中的电流的关系的悬空接合，并且可以有害地使得沟道中的载流子的迁移率降级，这导致器件不能够以高频进行操作。然而，从背侧将绝缘体层205图案化，使得不同的材料可以放置成紧邻有源器件的沟道而不过度破坏有源层可以产生益处。例如，热耗散层可以在有源器件层206中放置成紧邻有源器件的沟道区以从有源器件将热量引走。如另一示例，应变层可以紧邻有源器件的沟道区沉积以增强沟道中的载流子迁移率。如进一步的示例，可以穿过经图案化的绝缘体来形成电接触，该经图案化的绝缘体需要与在有源器件层206中或在有源器件层206上方的接触区对准。
可以参照图3中的流程图和图4A-E中的结构横截面来描述用于生产具有自对准背侧特征的半导体结构的方法。图3的过程始于步骤301，其中在SOI晶片上形成了栅极。该栅极可以是场效应晶体管(FET)的栅极，该FET可以是金属氧化物半导体(MOS)FET或绝缘栅双极结型晶体管(IGBT)。该栅极也可以是任何类型的FET的栅极，该任何类型的FET包括FinFET、横向扩散MOS(LDMOS)或垂直器件。有源层可以为完全耗尽(FD)FET提供沟道，并可以用作此类器件的超薄本体区。栅极一般会包括绝缘体和栅电极。例如，栅极绝缘体可以是二氧化硅，且栅电极可以是形成在栅极绝缘体上的多晶硅层。栅电极也可以包括金属，诸如铜、钨、钼或金属硅化物。栅极还可包括附加的绝缘体或钝化层来将栅极隔离。例如，栅极可包括以垂直方向覆盖栅极堆叠的侧壁分隔件，并可以包括与栅极绝缘体相对的以横向方向覆盖栅极堆叠的栅极盖。最后，栅极也可以包括用以从具有比最终栅极堆叠更大的横向延伸的材料层形成栅极堆叠的光致抗蚀剂层或一些其他形式的硬掩模。这些层可以是栅极的永久特征，或者它们可以是在器件完成之前被移除的临时层。
图4A中的SOI结构400包括具有基板405、埋藏绝缘体层406和有源器件层407的SOI晶片401。如先前所提及的，基板405可包括半导体(诸如硅)或绝缘体(诸如蓝宝石)。在基板405是绝缘体的情形中，埋藏绝缘体层406和基板405之间可以没有区别。埋藏绝缘体层406也可以通过将离子注入施体晶片来形成，并且基板405也可以是用来稳定有源器件层407的处理晶片，因为该基板405与施体晶片分开。在基板405是硅的情形中，埋藏绝缘体层405可包括通过将基板405氧化形成的二氧化硅。在这些情形中，有源器件层407可以通过外延生长来形成。替换地，埋藏绝缘体层406可以通过应用SIMOX工艺在均匀基板中形成。不管用来制备SOI晶片401的具体工艺如何，埋藏绝缘体层406可以被称为埋藏绝缘体，因为其顶侧上被有源器件层407覆盖，并且其背侧上被基板405覆盖。即使基板或有源层被移除以暴露绝缘体，但是术语埋藏绝缘体也可以被用来描述该层(即，术语“埋藏”指的是物理区域，而不管在完成的器件中其是否仍然被掩埋)。
图4A中的SOI结构400进一步解说了在器件区域的顶侧上形成的栅极408。如所解说的，栅极408包括三层材料。栅极绝缘体409覆盖了有源器件区407的一部分，有源器件区407的这一部分将用作形成在有源器件区407中的器件的沟道。栅极绝缘体409被栅电极410覆盖。在该特定示例中，栅极408还包括覆盖栅电极410的光致抗蚀剂层411。然而，如先前所提及的，栅极408可以不包括该附加的层，并且该层可以是或者可以不是栅极408的永久特征。在所解说的示例中，光致抗蚀剂411在器件完成之前从栅极堆栈408移除。然而，光致抗蚀剂411也可以在附图中被将用作掩模以及用作栅极的永久部分的电介质替代。
过程300以步骤302继续，其中使用栅极作为掩模，向SOI晶片应用处理。该处理在埋藏绝缘体层中形成了经处理的绝缘体区。在具体的办法中，处理被应用到SOI晶片的顶侧。例如，该处理可包括掺杂剂离子向有源层和埋藏绝缘体中的扩散。作为另一示例，该处理可包括离子注入以掺杂埋藏绝缘体层。该处理使用栅极作为掩模，从而该处理是有效自对准的。然而，栅极可以被用作负掩模或正掩模，从而经处理的绝缘体区可以形成在栅极下的埋藏绝缘体层中，或者形成在栅极的横向范围外。该处理可以应用于晶片级工艺中，从而多个器件上的多个栅极会提供经处理的绝缘体层的图案。在栅极充当负掩模的情形中，第一次暴露会将在栅极的横向范围之外的绝缘体层涂上底层以耐受第二处理步骤，该第二处理步骤意在于栅极的横向范围内最终形成经处理的绝缘体区。在特定示例中，该处理将是自对准离子注入到氧化物上覆硅晶片的埋藏氧化层中以形成与晶片的沟道对准，但是在晶片的沟道的横向范围之外的埋藏氧化物的掺杂区。
图4A中的SOI结构400进一步解说了离子轰击412，该离子轰击412使用栅极408作为掩模，指向到SOI晶片401的顶侧。离子轰击可以涉及将掺杂剂离子注入埋藏绝缘体层406中。离子轰击的能量可以被调节成将其效果集中在绝缘体层406上，同时使得对有源器件层407的损坏最小化。离子轰击也可以被调节成仅影响埋藏绝缘体层406的一部分，从而经处理绝缘体区会在横向维度和垂直维度二者上与未经处理的绝缘体区区分开。具体而言，经处理的绝缘体区可以被放置成朝向埋藏绝缘体层406的背侧，从而经处理的绝缘体区在未经处理的绝缘体部分之下，以及在未经处理的绝缘体的右侧和左侧。
离子轰击412可包括各种离子注入种类。例如，轰击可包括硼、磷或砷。具体而言，离子轰击412可包括具有小于碳且大于锂的原子重量的掺杂剂离子。在具体办法中，离子轰击412将通过将最终形成FET的源极区和漏极区或IGBT的发射极的硅有源器件层的区域来传导。由此，掺杂剂离子可以被选择为使得对于这些区域的破坏最小化。虽然具有较小原子重量的掺杂剂离子不太可能破坏有源层，因为它们通过了，它们也不太可能在将埋藏绝缘体层处理成可以被选择性地处理的程度中起作用。具有小于碳但是大于锂的原子重量的掺杂剂离子不太可能破坏源极区，因为它们通过了，而同时它们也保持了它们作为经处理的绝缘体区的创建者的功效。
过程300以步骤303继续，其中基板的一部分被移除。在具体的办法中，基板被从SOI晶片的背侧移除以暴露埋藏绝缘体层。基板可以通过研磨工艺来移除并可以涉及应用化学机械抛光(CMP)处理步骤。基板可以在单个步骤中移除或者在多个步骤过程中被移除。具体而言，可以应用快速研磨来移除基板的大部分，同时具有对于埋藏绝缘体的较高选择性的较慢工艺(诸如湿法刻蚀)可以被应用作为第二步骤。在步骤303期间，晶片可以由真空卡盘或替换的处置器保持在位置上，使得SOI晶片的背侧可以被容易地碰到。替换地，SOI晶片可以由附连在SOI晶片的顶侧的处理晶片保持在位置上。
过程300可包括附加步骤304，其中在步骤302中将处理应用到SOI晶片之后，处理晶片被接合到SOI晶片。该处理晶片可以接合到SOI晶片的顶侧。该接合可以是永久性接合或临时性接合。在该接合是临时的情形中，SOI晶片可以在稍后的时间转移到另一永久性处理晶片。处理晶片可以向SOI晶片的有源器件层提供稳定力，而基板在步骤303中被移除。附加地，处理晶片可以用作总体SOI结构的永久性特征，从而处理晶片在基板被移除之后继续为有源器件层提供稳定力。如被共同转让的美国专利No.8,466,036及其相关专利中所描述的，处理晶片可包括富陷阱层。处理晶片也可以包括可以电耦合到SOI晶片的有源器件层的附加的有源或无源器件。
图4B中的SOI结构420解说了经处理的绝缘体区421形成在埋藏绝缘体层406中之后的SOI晶片401。SOI结构420进一步解说了SOI晶片401如何被接合到处理晶片422以及随后被反转以供背侧处理。可以使用永久性或临时性接合而将处理晶片422接合到SOI晶片401。处理晶片422可包括富陷阱层并可附加地全然包括富陷阱材料。如所解说的，在该过程的该点，可以从栅极408移除掩模411。然而，如先前所陈述的，掩模411可包括该器件的永久性部分。有源器件层407解说为具有将其连接到处理晶片422的触点423。然而，触点423仅仅表示SOI晶片401在接合处理晶片422之前将经历的附加处理。虽然有源器件层407可以连接到处理晶片422中的电路系统，这些触点也可以连接到意在于在SOI晶片401内单独路由信号的金属化层。
各种附加层可以被添加到SOI晶片401以存在于有源层407和处理晶片422之间。这些层可包括用于在有源器件层407中的有源器件之间路由信号的金属化层。根据横截面400和420的不同办法之间存在的数个步骤可包括与变体技术(诸如CMOS或BiCOMS)相关联的任何类型的处理。在具体的办法中，标准CMSO制造在步骤302之后将继续并继续直到沉积层级间电介质，在该点可以执行步骤304。在另一办法中，在执行步骤304之前，可以向SOI晶片的顶侧增加任意数目个附加晶片。这些附加晶片可包括富陷阱层并且也可包括附加无源或有源电路系统，可使用直接金属触点、通过硅通孔(TSV)或类似结构将该附加无源或有源电路系统耦合到有源器件层407的电路系统，。
图4C中的SOI结构440解说了移除基板405之后的SOI晶片。如所解说的，基板405被完全从SOI晶片401的背侧移除以藉此暴露经处理的绝缘体区421。
然而，还可用图案化方式来移除该基板。例如，基板可以仅在总体管芯的特定区域(诸如，其中将最终形成有源器件的区域)之下被移除。作为进一步的示例，基板可以仅在特定特征(诸如直接位于栅极(诸如栅极408)之下的区域)之下被移除。具体而言，基板可以被部分移除，使得基板的剩余部分随着基板被移除继续向有源器件层407提供稳定力。基板的剩余部分还可以向最终器件中的有源器件层407提供稳定力。在这些办法中，可能不需要处理晶片，或者可能仅在虽然基板被部分移除但是剩余的基板可以向最终器件中的有源器件层提供所需稳定力时需要处理晶片。
过程300以步骤305继续，其中经处理的绝缘体区被选择性地从埋藏绝缘体层移除。从绝缘体层中移除经处理的绝缘体区形成了剩余的绝缘体区。因为栅极被用来将经处理的绝缘体区图案化，所以剩余的绝缘体区将对准到栅极并且位于在栅极下面的SOI结构的有源区下。该办法的优点在于绝缘体区藉此被图案化而不需要附加的掩模。
可以使用对于经处理的绝缘体区是选择性的任何工艺来在步骤305中移除绝缘体。由此，移除工艺与步骤302中应用的处理链接。作为一个特定的示例，处理可以是硼离子注入到包括二氧化硅的埋藏绝缘体层以形成掺杂氧化物，并且移除工艺可以是以蒸汽的形式传递的氢氟酸蚀刻，该氢氟酸蚀刻会移除掺杂氧化物并保留未经处理的二氧化硅。选择性移除工艺可包括湿法氢氟酸蚀刻或蒸汽氢氟酸蚀刻。可以替换地使用等离子蚀刻来移除绝缘体。
图4D中的SOI结构460解说了经处理的绝缘体区421被移除之后的SOI晶片401。结果所得结构包括有源区407中的沟道背侧上的剩余绝缘体461的自对准特征。从晶片的其他部分移除原始SOI绝缘体，而其在栅极的下面仍然保留，该栅极被用来图案化在步骤302中应用的处理。如所示出的，剩余的绝缘体和栅极二者都与形成在器件区中的沟道接触。取决于步骤305中应用的移除工艺的选择性，剩余的绝缘体区461可以在横向维度和垂直维度二者上比原始绝缘体区更薄。然而，所告知的对于步骤302中应用的处理和步骤305中的移除工艺(这二者都是基于包括原始埋藏绝缘体层的材料)的选择将会导致对于剩余绝缘体区461与有源区407中的器件的沟道的可靠对准产生贡献的高度选择性移除工艺。
在替换性办法中，步骤305中的选择性移除工艺将会导致步骤302中应用的处理的负片图案。在替换性步骤中，就在步骤305之前，整个绝缘体区可以在通过移除基板被暴露之后经历第二次处理，并随后通过选择性移除工艺起作用，从而仅会剩下步骤302中处理的绝缘体区。在这些办法中，第一次处理用来抵消第二次处理的效果，从而在应用选择性移除工艺之后，仅会剩下那些未接受第一次处理的绝缘体部分。
虽然SOI结构460将经处理的绝缘体区421解说为在特定位置中被完全移除，作为替代，经处理的绝缘体会在沿SOI结构的背侧的横向跨度的不同点处被不同程度地移除。如先前所提及的，来自步骤302的处理的目标可以是埋藏绝缘体区的特定深度，从而经处理的绝缘体区421不延伸通过原始埋藏绝缘体的整个垂直跨度。例如，若来自步骤302的处理的目标是仅仅覆盖绝缘体层的后半，那么步骤305中的选择性移除可以导致仅有一半的绝缘体区在总体图案中的特定点处被移除，从而剩余的绝缘体区461会是被变薄的剩余绝缘体的跨度围绕的凸起的高出部分。
过程300以步骤306继续，其中沉积一层。该层可以沉积在SOI晶片的背侧上。该层可以形成在剩余绝缘体区上。该层可以经由毯覆沉积来沉积或者其可以是针对性沉积。沉积步骤可以使用掩模，或者其可以仅依赖由剩余的绝缘体区形成的图案。该沉积可包括增强化学气相沉积(CVD)、等离子体增强CVD、原子层沉积(ALD)、电介质旋涂或喷涂涂覆，或高密度等离子沉积(HDP)。替换地，该层可以通过将SOI晶片与共形材料层接触来形成，该共形材料层会依照剩余绝缘体区的形状。可以使用附加晶片来接触共形层。
图4E中的横截面480解说了在晶片的背侧上沉积层481之后的SOI晶片。虽然仅解说了单个层，但是在SOI晶片上可以沉积多个层以达成各种结果。在所解说的示例中，移除经处理绝缘体区暴露了器件区407，而形成层481包括将材料毯覆沉积在剩余绝缘体区461和器件区407上。在所解说的示例中，沉积是指向SOI晶片的背侧的。层481可包括应变层，热耗散层，或会受益于被图案化成围绕器件区407中的有源器件的沟道的任何其他材料区。
与图4E中解说的示例形成对比，但根据先前所提及的示例，栅极408可以与剩余绝缘体区具有负片图案关系，从而绝缘体被从沟道下面移除但是留在结构的其他区域中。在这些示例中，所沉积的层可以是电绝缘热耗散层。该办法会带来将热耗散层与有源器件的热生成沟道尽可能紧地放置的益处。然而，这些办法会伴生有损坏层407中的有源器件的微小沟道的风险，除非为选择性移除绝缘体所涉及的处理步骤以及层481的沉积选择特定容限。
图5显示了根据参照图3所描述的规程处理的SOI器件中的晶体管的横截面500。横截面500包括形成在SOI晶片上的栅极408。栅极包括栅电极501和栅极绝缘体502。横截面还解说了与栅极408相关联的沟道区503，并且该沟道区503与剩余绝缘体区461和栅极408二者接触。如先前所描述的，栅极408形成在器件区407的顶侧。因为栅极被用来图案化剩余的绝缘体区461，所以层481位于埋藏绝缘体504的挖出区域，在有源器件区407的背侧上，且沿剩余绝缘体区461的垂直边沿。
某些益处归因于其中剩余绝缘体区461的边缘可以可靠地对准到栅极408的办法。参照图3所描述的过程提供了原本不能通过合理的商业努力而得到的这两个特征的对准程度。使用过程300，栅极408的垂直边沿可以在误差余裕内可靠地对准到剩余绝缘体461的垂直边沿，该误差余裕由有源器件层407的厚度、用以处理绝缘体层的任何离子的种类和注入能量、经处理的绝缘体区的掺杂浓度、以及可以更改经处理的绝缘体区的扩展的注入后热状况来约束。随着有源器件层407的厚度减小，误差余裕增加。随着用以处理绝缘体层的任何离子的注入能量和重量增加，误差余裕也增加。随着经处理的绝缘体区的掺杂浓度增加，误差余裕减小。基于仿真，参照图3所描述的办法可以针对小于100纳米厚度的器件区域，在小于80纳米的误差余裕内提供栅极408和剩余绝缘体461的可靠对准。值得注意的是，即使当最终的器件包括具有特别薄的有源层的完全耗尽的SOI器件时，过程300也可以达成可靠的对准。这些情形中的沟道区503会包括超薄本体区。
如先前所提及的，层481可以是应变引发层。应变引发层可以是压缩薄膜或拉伸薄膜。应变引发层还可以通过晶格失配效应在有源器件层407中引发应变。例如，应变引发层481可包括硅锗，而有源器件层407包括硅，在该情形中，两种材料的失配会在有源器件层407中引发应变。应变引发层可以通过在沟道区503中引发应变505来增强器件中的载流子的迁移率。应变层481增强沟道区503中的载流子的迁移率，并藉此增强了器件层407中形成的器件的性能。应变层受益于更为紧密地与沟道区对准，因为其藉此能够更为直接地在器件上施加应变，而同时不直接与沟道区交叠并有害地更改器件的行为。
应用到绝缘体层的处理的类型以及所沉积的应变层的类型的不同组合在沟道区503中产生了不同类型的应变。如先前所提及的，取决于应用到绝缘体层的处理，栅极可以被用作负掩模或正掩模，从而经处理的绝缘体区可以形成在栅极下的绝缘体层中，或者形成在栅极的横向范围外。应变层所引发的应变也可以被认为展现了负应变或正应变，其中沉积的薄膜可以分别是压缩膜或拉伸膜。值得注意的是，薄膜的该特性可以独立于薄膜应用于其上的图案。因此，独立正应变膜或负应变膜与正片图案或负片图案的组合产生了四个不同配置的电势，这四个配置产生了两个不同的应变分布(即，具有负片图案的负薄膜产生了正应变，两个负和正的组合产生了负应变，以及具有负片图案的正薄膜产生了正应变)。使用不同组合达成给定应变分布的能力为设计者提供了出于成本或关于技术可行性的关注而回避某些种类的绝缘体处理或应变层材料的自由度。
层481的附加变体还受益于严格对准到栅极408。例如，因为沟道是半导体器件中最大的热源之一，所以热耗散层受益于紧密对准到沟道区从而使得热量在被高效地从器件中消除之前必须扩散通过的距离最小化。同时，将埋藏绝缘体保留在沟道下是重要的，因为热耗散层一般是对于原始埋藏绝缘体不那么有效的替代。
在步骤306之后，可以进行附加的处理步骤从而连接到有源器件层407中的电路系统以及封装最终的器件。例如，沉积层可以被图案化及蚀刻以形成去往有源器件层407中的器件的触点以允许外部连接。此外，可以在SOI晶片的背侧上形成背侧金属以提供器件层407中的不同电路组件之间的互连。例如，背侧金属化可以被用来将一个晶体管连接到另一个晶体管，将晶体管连接到二极管，或将晶体管连接到无源组件。
图6解说了在步骤303处继续进行方法300的方法600。在方法600中，步骤301-304可以如上文所描述的那样进行。然而，方法600旨在使用先前所描述的结构的替代结构来在晶片上操作。方法600生产自对准双栅极器件。图7A中的SOI结构700解说了可以根据方法600处理的SOI晶片701。起始晶片包括SOI晶片401的许多特征，并且主要的区别在于基板702不仅与埋藏绝缘体层406和有源器件层407相关联，而且也与第二有源层703和第二埋藏绝缘体层704相关联。如图7A中所示，栅极408被用作掩模以供向SOI晶片701中注入掺杂剂离子。与方法300形成对比，离子注入，或者方法600中使用的其他处理，必须受到控制以通过第二埋藏绝缘体层704以作为替代处理埋藏绝缘体区406并形成经处理的绝缘体区705。若之前所述，形成经处理绝缘体区705将未经处理的绝缘体区706保留在它的原始状态中。
参照过程300所描述的任何处理步骤可以类似地应用到方法600，如同这些处理步骤继续那样。图7B解说了了SOI结构720，如同处理以参照图4B所描述的类似方式继续那样。SOI晶片被反转，并且可任选的处理晶片422被接合到晶片的顶部。如先前所提及的，处理晶片422可包括富陷阱层。图7C解说了基板702被移除之后的横截面740。
方法600继续到步骤601，其中经处理的绝缘体区被从埋藏绝缘体层移除。该处理步骤的一个示例由图7D中的SOI结构760解说。SOI结构760示出了经处理的绝缘体区705被移除，从而仅剩未经处理的绝缘体层706之后的SOI晶片。在该过程的该点，有源器件层407被暴露，而第二有源层703和第二埋藏绝缘体层704仍然被覆盖。
方法600继续到步骤602或603。在步骤602中，所暴露的器件区的一部分被移除。可以使用剩余的埋藏绝缘体706作为掩模来移除器件区，或者可以替代地使用附加的掩模。用来蚀刻器件区407的蚀刻剂可以执行各向同性蚀刻并且也可以涉及对于第二埋藏绝缘体704选择性的特定化学蚀刻剂。在步骤603，一材料层被沉积在晶片的背侧上。步骤603可以根据上文所讨论的步骤306的任何变体来进行。
图7E解说了示出器件区407的一部分被移除以形成剩余器件区781，以及层481被沉积在晶片的背侧上之后的SOI晶片701的SOI结构780。在该情形中，剩余的器件区781用作第二器件区703中形成的沟道的附加栅电极，而第二埋藏绝缘体704用作附加栅极的栅极绝缘体。结果所得结构包括自对准DG-FET。在该结构中，栅极408接触第二器件区703并与形成在第二器件区703中的沟道相关联。剩余的器件区781用作相同沟道的第二栅电极，并且剩余埋藏绝缘体706用以隔离并遮蔽剩余器件区781。
图7A-E中的绝缘体层406比第二绝缘体层704更厚以解说归因于此类结构的某些优点。具体而言，在对于埋藏绝缘体层的处理是离子注入步骤的情形中，绝缘体层406的厚度使其成为用于注入的更简单的目标。同时，栅极绝缘体的厚度和与晶体管相关联的特定品质因数(诸如其跨导)成反比。因为绝缘体层704将用作附加栅极的栅极绝缘体，所以使得绝缘体层704相对较薄是有益的。因此，当与离子注入处理联用时，过程600特别适合于创建高性能DG-FET。
图7E中解说的双栅极结构极大地受益于由过程300和600提供的对准的程度，其中DG-FET中的未对准的栅极可以导致电流驱动的额外电容和相当损耗。然而，当栅极以高度准确性可靠地对准时，DG-FET的速度和功率耗散显著低于单栅极FET的速度和功率耗散。因此，根据自对准工艺(诸如过程600)来创建双栅极结构可以产生比用单个掩模来创建附加的栅电极781的办法更优越的晶体管。图3和图6的过程可以用对于上文所讨论的对准的类似的约束来可靠地对准DG-FET的双栅极。然而，在该情形中，埋藏绝缘体的厚度也是对于对准的可靠性的约束，因为注入是通过埋藏绝缘体和顶部有源区二者的。基于仿真，参照图3和图6所描述的办法可以针对厚度小于80纳米，埋藏绝缘体厚度为10纳米的器件区，在小于70纳米的误差余裕内提供栅极408和剩余器件区781的可靠的对准。值得注意的是，即使当最终的器件包括具有特别薄的有源层的完全耗尽的SOI器件时，过程300也可以达成可靠的对准。这些情形中的沟道区503会包括超薄本体区。
沉积层481可以采取参照图4E和图5描述的任何特性。具体而言，沉积层481可以是增强形成在第二器件层703中的沟道中的载流子的迁移率的应变层。如先前所描述的，薄膜可以是压缩薄膜或拉伸薄膜。层481还可以是热耗散层。同样，如上文参照图4E所注意到的，SOI结构780可以经历附加的处理步骤以连接到有源层703中的电路系统。此外，SOI结构780可以经历附加的处理步骤来将栅电极781连接到封装上的不同晶片中的电路系统，或连接到有源层703中的电路系统。具体而言，栅电极781可以被连接到与栅极408的栅电极相同的电路系统。
虽然，以上公开中的一些实施例是通过其中栅极结构被用作SOI绝缘体层的初始处理的掩模的横截面来具体解说的，但是其他特征可以被替代地用来作为初始处理的掩模。事实上，背侧对准所期望的任何特征可以被用来图案化所应用的处理。取决于特征的特性，用来定义特征的材料可以被用作掩模本身，或者用以图案化该特征的实际掩模可以被用作初始处理的掩模。作为特定的示例，用以在SOI晶片中图案化TSV的掩模也可以被用来向绝缘体应用处理。此类办法在TSV旨在通过背侧绝缘体连接的情形中会是有用的。
尽管已经参考本发明的具体实施例详细描述了本说明书，但是应领会，本领域技术人员在理解了上述内容之后，可以容易地想到这些实施例的变更、变型或等效方案。对本发明的这些及其他修改和变型可由本领域技术人员实践，而不脱离本发明的精神和范围，这在所附权利要求中更加具体地进行了阐述。

Claims (16)

1.一种用于提供半导体器件的方法，包括：
在绝缘体上半导体晶片上形成栅极，其中所述绝缘体上半导体晶片包括器件区、埋藏绝缘体和基板；
使用所述栅极作为掩模向所述绝缘体上半导体晶片应用处理，其中所述处理在所述埋藏绝缘体中创建经处理的绝缘体区；
移除所述基板的至少一部分；以及
在移除所述基板的该部分之后，从所述埋藏绝缘体选择性地移除所述经处理的绝缘体区以形成与所述栅极对准的剩余的绝缘体区并且暴露所述器件区的有源层的背侧。
2.如权利要求1所述的方法，其特征在于，进一步包括：
在向所述绝缘体上半导体晶片应用所述处理之后，将处理晶片接合到所述绝缘体上半导体晶片；
其中移除所述基板的至少一部分包括移除整个基板；以及
其中当所述基板被移除时以及在所述基板被移除之后，所述处理晶片向所述绝缘体上半导体晶片的所述器件区提供稳定力。
3.如权利要求1所述的方法，其特征在于，进一步包括：
在移除所述经处理的绝缘体区之后，在所述剩余的绝缘体区上形成热传导层。
4.如权利要求1所述的方法，其特征在于：
所述处理包括将掺杂剂离子注入到所述埋藏绝缘体中；以及
使用气相蚀刻剂来移除所述经处理的绝缘体。
5.如权利要求4所述的方法，其特征在于：
所述掺杂剂离子具有比碳小的原子重量；以及
所述蚀刻剂是氢氟酸。
6.如权利要求1所述的方法，其特征在于，进一步包括：
在移除所述经处理的绝缘体区之后，移除所述器件区的一部分；
其中所述绝缘体上半导体晶片包括第二埋藏绝缘体和第二器件区；
其中所述栅极包括用于形成在所述第二器件区中的沟道的栅电极；以及
其中所述器件区包括用于形成在所述第二器件区中的沟道的附加栅电极。
7.如权利要求6所述的方法，其特征在于：
所述第二埋藏绝缘体比所述埋藏绝缘体薄。
8.如权利要求1所述的方法，其特征在于，进一步包括：
在移除所述经处理的绝缘体区之后，在所述剩余的绝缘体区上形成应变层。
9.如权利要求8所述的方法，其特征在于：
移除所述经处理的绝缘体区暴露了所述器件区；并且
形成所述应变层包括在所述剩余的绝缘体区和所述器件区上毯覆沉积应变材料。
10.如权利要求9所述的方法，其特征在于：
所述剩余的绝缘体和所述栅极二者都与形成在所述器件区中的沟道接触；以及
所述应变层增强所述沟道中的载流子的迁移率。
11.一种用于提供半导体器件的方法，包括：
在绝缘体上半导体晶片的顶侧上并且在有源层上方形成栅极；
在形成所述栅极之后，向所述绝缘体上半导体晶片的所述顶侧应用处理以在所述绝缘体上半导体晶片的绝缘体层中形成经处理的区域；
从所述绝缘体上半导体晶片的背侧移除基板以暴露所述绝缘体层；以及
在移除所述基板之后，从所述绝缘体层选择性地移除所述经处理的区域以暴露所述有源层的背侧并形成与所述栅极对准的剩余的绝缘体区；
其中所述栅极被用来图案化所述经处理的区域，从而用自对准的方式形成所述经处理的区域。
12.如权利要求11所述的方法，其特征在于：
所述处理包括将离子注入到所述绝缘体层中；以及
使用气相蚀刻剂移除所述经处理的区域。
13.如权利要求11所述的方法，其特征在于，进一步包括：
在移除所述基板之前，将处理晶片附连到所述绝缘体上半导体晶片的顶侧；以及
在移除所述经处理的区域之后，在所述绝缘体上半导体晶片的背侧上沉积应变层；
其中所述应变层增强了沟道中的载流子的迁移率，所述沟道位于所述绝缘体层的剩余部分之上和所述栅极之下。
14.如权利要求13所述的方法，其特征在于：
所述绝缘体上半导体晶片包括硅基板；
通过从所述绝缘体上半导体晶片的所述背侧进行研磨来至少部分地移除所述基板；
所述绝缘体层包括二氧化硅；
所述处理包括将离子注入到所述绝缘体层中；
使用气相蚀刻剂来移除所述经处理的区域；以及
所述栅极控制完全耗尽晶体管的沟道。
15.如权利要求11所述的方法，其特征在于，进一步包括：
在移除所述经处理的区域之后，移除所述绝缘体上半导体晶片的器件区的一部分；
其中所述绝缘体上半导体晶片包括在所述绝缘体层上方的第二埋藏绝缘体，以及在所述器件区上方的第二器件区；
其中所述栅极包括用于形成在所述第二器件区中的沟道的栅电极；以及
其中所述器件区包括用于形成在所述第二器件区中的沟道的附加栅电极。
16.如权利要求15所述的方法，其特征在于：
所述第二埋藏绝缘体比所述绝缘体层薄。
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