FR2848724B1 - Connexions enterrees dans un substrat de circuit integre - Google Patents
Connexions enterrees dans un substrat de circuit integreInfo
- Publication number
- FR2848724B1 FR2848724B1 FR0215837A FR0215837A FR2848724B1 FR 2848724 B1 FR2848724 B1 FR 2848724B1 FR 0215837 A FR0215837 A FR 0215837A FR 0215837 A FR0215837 A FR 0215837A FR 2848724 B1 FR2848724 B1 FR 2848724B1
- Authority
- FR
- France
- Prior art keywords
- integrated circuit
- circuit substrate
- bonded connections
- connections
- bonded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0215837A FR2848724B1 (fr) | 2002-12-13 | 2002-12-13 | Connexions enterrees dans un substrat de circuit integre |
US10/735,518 US20040145058A1 (en) | 2002-12-13 | 2003-12-12 | Buried connections in an integrated circuit substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0215837A FR2848724B1 (fr) | 2002-12-13 | 2002-12-13 | Connexions enterrees dans un substrat de circuit integre |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2848724A1 FR2848724A1 (fr) | 2004-06-18 |
FR2848724B1 true FR2848724B1 (fr) | 2005-04-15 |
Family
ID=32338777
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0215837A Expired - Fee Related FR2848724B1 (fr) | 2002-12-13 | 2002-12-13 | Connexions enterrees dans un substrat de circuit integre |
Country Status (2)
Country | Link |
---|---|
US (1) | US20040145058A1 (fr) |
FR (1) | FR2848724B1 (fr) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1790005A1 (fr) * | 2004-09-02 | 2007-05-30 | Koninklijke Philips Electronics N.V. | Mise en contact avec des structures d'isolation par tranchee profonde et remplissage de celles-ci avec du tungstene |
US7285477B1 (en) * | 2006-05-16 | 2007-10-23 | International Business Machines Corporation | Dual wired integrated circuit chips |
EP1873822A1 (fr) * | 2006-06-27 | 2008-01-02 | STMicroelectronics S.r.l. | Contact avant-arrière de dispositifs électroniques avec défauts induits pour améliorer la conductivité |
FR2910704A1 (fr) * | 2007-04-05 | 2008-06-27 | Commissariat Energie Atomique | Procede de realisation d'un dispositif a circuit integre interconnecte |
EP3373329B1 (fr) | 2014-02-28 | 2023-04-05 | LFoundry S.r.l. | Circuit integré comprenant un transistor mos a diffusion laterale |
US9515181B2 (en) | 2014-08-06 | 2016-12-06 | Qualcomm Incorporated | Semiconductor device with self-aligned back side features |
CN108054157B (zh) * | 2017-12-15 | 2021-01-12 | 浙江清华柔性电子技术研究院 | 用于系统级封装的tsv转接板 |
CN108010853B (zh) * | 2017-12-15 | 2021-06-22 | 西安科锐盛创新科技有限公司 | 基于硅通孔的转接板及其制备方法 |
US10685947B2 (en) | 2018-01-12 | 2020-06-16 | Intel Corporation | Distributed semiconductor die and package architecture |
US11404270B2 (en) * | 2018-11-30 | 2022-08-02 | Texas Instruments Incorporated | Microelectronic device substrate formed by additive process |
US10861715B2 (en) | 2018-12-28 | 2020-12-08 | Texas Instruments Incorporated | 3D printed semiconductor package |
US10910465B2 (en) | 2018-12-28 | 2021-02-02 | Texas Instruments Incorporated | 3D printed semiconductor package |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US64553A (en) * | 1867-05-07 | moohe | ||
US615A (en) * | 1838-02-22 | Machine for washing bags in the manufacture of paper | ||
US5091331A (en) * | 1990-04-16 | 1992-02-25 | Harris Corporation | Ultra-thin circuit fabrication by controlled wafer debonding |
US5621239A (en) * | 1990-11-05 | 1997-04-15 | Fujitsu Limited | SOI device having a buried layer of reduced resistivity |
US5426072A (en) * | 1993-01-21 | 1995-06-20 | Hughes Aircraft Company | Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate |
US5670387A (en) * | 1995-01-03 | 1997-09-23 | Motorola, Inc. | Process for forming semiconductor-on-insulator device |
US5776789A (en) * | 1995-06-05 | 1998-07-07 | Fujitsu Limited | Method for fabricating a semiconductor memory device |
US5807783A (en) * | 1996-10-07 | 1998-09-15 | Harris Corporation | Surface mount die by handle replacement |
US6291858B1 (en) * | 2000-01-03 | 2001-09-18 | International Business Machines Corporation | Multistack 3-dimensional high density semiconductor device and method for fabrication |
JP2003110108A (ja) * | 2001-09-28 | 2003-04-11 | Mitsubishi Electric Corp | 半導体装置の製造方法及びその構造 |
-
2002
- 2002-12-13 FR FR0215837A patent/FR2848724B1/fr not_active Expired - Fee Related
-
2003
- 2003-12-12 US US10/735,518 patent/US20040145058A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20040145058A1 (en) | 2004-07-29 |
FR2848724A1 (fr) | 2004-06-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20070831 |