DE60323003D1 - Organisches Flipchipbond-Substrat - Google Patents

Organisches Flipchipbond-Substrat

Info

Publication number
DE60323003D1
DE60323003D1 DE60323003T DE60323003T DE60323003D1 DE 60323003 D1 DE60323003 D1 DE 60323003D1 DE 60323003 T DE60323003 T DE 60323003T DE 60323003 T DE60323003 T DE 60323003T DE 60323003 D1 DE60323003 D1 DE 60323003D1
Authority
DE
Germany
Prior art keywords
bond substrate
chip bond
flip
organic
organic flip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60323003T
Other languages
English (en)
Inventor
Eiichi Hosomi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE60323003D1 publication Critical patent/DE60323003D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
DE60323003T 2002-05-07 2003-01-30 Organisches Flipchipbond-Substrat Expired - Lifetime DE60323003D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/141,685 US6768206B2 (en) 2002-05-07 2002-05-07 Organic substrate for flip chip bonding

Publications (1)

Publication Number Publication Date
DE60323003D1 true DE60323003D1 (de) 2008-10-02

Family

ID=29249820

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60323003T Expired - Lifetime DE60323003D1 (de) 2002-05-07 2003-01-30 Organisches Flipchipbond-Substrat

Country Status (4)

Country Link
US (1) US6768206B2 (de)
EP (1) EP1361612B1 (de)
JP (1) JP3730625B2 (de)
DE (1) DE60323003D1 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4170137B2 (ja) 2003-04-24 2008-10-22 新光電気工業株式会社 配線基板及び電子部品実装構造
US7105926B2 (en) * 2003-11-24 2006-09-12 Lsi Logic Corporation Routing scheme for differential pairs in flip chip substrates
US7057284B2 (en) * 2004-08-12 2006-06-06 Texas Instruments Incorporated Fine pitch low-cost flip chip substrate
US7081672B1 (en) * 2005-03-07 2006-07-25 Lsi Logic Corporation Substrate via layout to improve bias humidity testing reliability
US7368667B2 (en) * 2005-08-10 2008-05-06 Alcatel Using rows/columns of micro-vias to create PCB routing channels in BGA interconnect grid (micro-via channels)
US7671450B2 (en) * 2007-12-17 2010-03-02 Agere Systems Inc. Integrated circuit package for high-speed signals
US8186051B2 (en) 2008-03-28 2012-05-29 Intel Corporation Method for fabricating package substrate and die spacer layers having a ceramic backbone
US8552563B2 (en) 2009-04-07 2013-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional semiconductor architecture
US8561004B2 (en) * 2010-02-04 2013-10-15 Advanced Micro Devices, Inc. Ring power gating with distributed currents using non-linear contact placements
US8338948B2 (en) 2010-06-30 2012-12-25 International Business Machines Corporation Ball grid array with improved single-ended and differential signal performance
EP2503594A1 (de) * 2011-03-21 2012-09-26 Dialog Semiconductor GmbH Ball-/Padlayout einer integrierten Schaltungspackung mit optimiertem Signalrouting
EP2808890A4 (de) * 2012-01-27 2015-08-19 Panasonic Corp Mehrschichtige leiterplatte
US9955605B2 (en) * 2016-03-30 2018-04-24 Intel Corporation Hardware interface with space-efficient cell pattern
US11398415B2 (en) * 2018-09-19 2022-07-26 Intel Corporation Stacked through-silicon vias for multi-device packages
KR102254166B1 (ko) * 2019-12-27 2021-05-20 주식회사 텔레칩스 볼 그리드 어레이 인쇄회로기판

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5917229A (en) * 1994-02-08 1999-06-29 Prolinx Labs Corporation Programmable/reprogrammable printed circuit board using fuse and/or antifuse as interconnect
JPH07245343A (ja) 1994-03-03 1995-09-19 Toshiba Corp 半導体装置及びその製造方法
JP3412942B2 (ja) * 1995-01-11 2003-06-03 株式会社東芝 半導体装置
KR970053805A (ko) 1995-12-04 1997-07-31 김광호 반도체 메모리 장치의 파워라인 배치방법
JPH09199587A (ja) 1996-01-12 1997-07-31 Nec Corp 半導体装置
US5763947A (en) * 1996-01-31 1998-06-09 International Business Machines Corporation Integrated circuit chip package having configurable contacts and a removable connector
US5889326A (en) 1996-02-27 1999-03-30 Nec Corporation Structure for bonding semiconductor device to substrate
JP3504421B2 (ja) 1996-03-12 2004-03-08 株式会社ルネサステクノロジ 半導体装置
US5686764A (en) 1996-03-20 1997-11-11 Lsi Logic Corporation Flip chip package with reduced number of package layers
US6160705A (en) * 1997-05-09 2000-12-12 Texas Instruments Incorporated Ball grid array package and method using enhanced power and ground distribution circuitry
US5959348A (en) 1997-08-18 1999-09-28 International Business Machines Corporation Construction of PBGA substrate for flip chip packing
US6031258A (en) 1998-03-06 2000-02-29 S3 Incorporated High DC current stagger power/ground pad
US6323118B1 (en) 1998-07-13 2001-11-27 Taiwan Semiconductor For Manufacturing Company Borderless dual damascene contact
US6084779A (en) 1998-10-02 2000-07-04 Sigrity, Inc. Ground and power patches on printed circuit board signal planes in the areas of integrated circuit chips
US6166441A (en) 1998-11-12 2000-12-26 Intel Corporation Method of forming a via overlap
DE19908428C2 (de) 1999-02-26 2000-12-07 Siemens Ag Halbleiterspeicheranordnung mit Bitleitungs-Twist
US6140710A (en) * 1999-05-05 2000-10-31 Lucent Technologies Inc. Power and ground and signal layout for higher density integrated circuit connections with flip-chip bonding
US6177732B1 (en) 1999-05-27 2001-01-23 Intel Corporation Multi-layer organic land grid array to minimize via inductance
US6037677A (en) * 1999-05-28 2000-03-14 International Business Machines Corporation Dual-pitch perimeter flip-chip footprint for high integration asics
JP2000349191A (ja) * 1999-06-04 2000-12-15 Toshiba Corp 半導体装置および配線回路装置
US6207476B1 (en) * 1999-06-10 2001-03-27 Vlsi Technology, Inc. Methods of packaging an integrated circuit and methods of forming an integrated circuit package
US6150729A (en) * 1999-07-01 2000-11-21 Lsi Logic Corporation Routing density enhancement for semiconductor BGA packages and printed wiring boards
US6340631B1 (en) 2000-05-31 2002-01-22 Taiwan Semiconductor Manufacturing Company, Ltd Method for laying out wide metal lines with embedded contacts/vias
US6542377B1 (en) * 2000-06-28 2003-04-01 Dell Products L.P. Printed circuit assembly having conductive pad array with in-line via placement

Also Published As

Publication number Publication date
JP2003332377A (ja) 2003-11-21
EP1361612B1 (de) 2008-08-20
US6768206B2 (en) 2004-07-27
JP3730625B2 (ja) 2006-01-05
EP1361612A3 (de) 2006-05-17
EP1361612A2 (de) 2003-11-12
US20030209807A1 (en) 2003-11-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition