CN104658998A - 形成堆叠沟槽接触的方法及由此形成的结构 - Google Patents

形成堆叠沟槽接触的方法及由此形成的结构 Download PDF

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CN104658998A
CN104658998A CN201510028716.7A CN201510028716A CN104658998A CN 104658998 A CN104658998 A CN 104658998A CN 201510028716 A CN201510028716 A CN 201510028716A CN 104658998 A CN104658998 A CN 104658998A
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Prior art keywords
trench contact
contact opening
contacting metal
grid structure
layer
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B.塞尔
O.戈龙茨卡
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Intel Corp
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Intel Corp
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Abstract

描述了形成微电子器件的方法和相关的结构。那些方法可包括形成一结构，该结构包括置于基板的源/漏接触上的第一接触金属，以及置于该第一接触金属的顶表面上的第二接触金属，其中该第二接触金属设置于ILD内，该ILD置于设置在该基板上的金属栅的顶表面上。

Description

形成堆叠沟槽接触的方法及由此形成的结构
发明背景技术
对于具有缩放尺寸(scaled dimensions)的集成电路，接触至栅的短路成为越来越困难的问题。虽然通过接触孔形成自对准多晶硅化物的金属栅工艺可在减少这样的短路方面获益，但是增加接触至栅配准余量(registration margin)的接触工艺需要进一步减少该接触至栅的短路(shorts)至可制造级别。
附图概述
虽然说明书以权利要求结束，该权利要求特别地指出并清楚地要求被认为是本发明的权益，但当结合附图进行阅读时，根据本发明下面的描述，可更容易确定本发明的优点，其中附图：
图1a-1g代表根据本发明的一个实施例的结构。
发明详细说明
在下面的详细描述中，对通过示例示出可实施本发明的具体实施例的附图进行参考。充分详细地描述这些实施例以使本领域技术人员能够实施该发明。要理解，本发明的各种实施例虽有不同但未必是互斥的。例如，本文描述的与一个实施例结合的具体特征、结构或特性，在不脱离本发明的精神和范围的情况下可在其它实施例中实现。此外，要理解，在每一公开的实施例内的各个元件的位置或布置在不脱离本发明的精神和范围的情况下可修改。因此，下面的详细描述不是以限制的意义来理解，且本发明的范围仅由经适当解释的所附权利要求，连同授权的权利要求的所有等同范围来限定。在图中，类似的标号在多个视图中指代相同或相似功能性。
描述了形成微电子结构的方法和相关的结构。那些方法可包括在置于基板上的第一ILD中形成接触开口，其中暴露源/漏接触区域，在该源/漏接触区域上形成硅化物，在该接触开口中形成第一接触金属以填充该接触开口，抛光该第一接触金属以按置于基板上的栅的顶表面平坦化第一接触金属的顶表面，在该栅的顶表面上沉积第二ILD，在该第二ILD中形成第二接触开口，以及在该第二接触开口中形成第二接触金属，其中该第一和第二接触开口导电性地耦合。本发明的方法增加接触至栅的配准余量且减少接触至栅的短路。
本发明的方法在图1a-1g中描绘。图1a示出晶体管结构100的一部分的横截面，晶体管结构100包括基板102和栅104，在一些实施例中栅104可包括金属栅，且例如，可包括诸如铪、锆、钛、钽或铝，或其组合等金属栅材料。栅104可包括顶表面105。基板102可由例如，但不限于，硅、绝缘体上硅、锗、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓、锑化镓或其组合等的材料组成。
晶体管结构100可进一步包括间隙壁材料106，其可邻近且直接接触栅104。间隙壁材料106在一些情况下可包括介电材料，例如但不限于，二氧化硅和/或氮化硅材料。晶体管结构100可进一步包括氮化物刻蚀停止层(nesl)108，其可邻近且直接接触该间隙壁材料106。在一些实施例中nesl 108可充当刻蚀停止层。晶体管结构100可进一步包括第一层间介电(ILD)110，在一些实施例中其可充当隔离层，且在一些情况下可设置为邻近且直接接触nesl 108。
牺牲停止层112可形成在栅104的顶表面105上，在一些情形下其可包括氮化物和/或碳化硅材料(图1b)。采用任何合适的图案化工艺，例如光刻工艺，抗蚀剂层114可形成在该停止层112上。可形成抗蚀剂层114以便为基板100的源/漏区103定义开口116，例如沟槽接触开口115。停止层112的一部分和ILD110的一部分可设置在置于基板上的栅104、邻近间隙壁材料以及邻近nesl的顶表面上。
在一实施例中，可采用干法刻蚀工艺以形成开口116，在该开口116中停止层112和第一ILD 110的部分可被去除。在一实施例中，刻蚀工艺可包括氧化物刻蚀，其可对氮化物刻蚀停止层(nesl)108以及对间隙壁材料106具有选择性，以及可以以基本上各向异性的方式去除该第一ILD 110，而使nesl 108和间隙壁材料106基本上完整无缺(intact)。换言之，在刻蚀工艺化学中，氧化物ILD可以远高于间隙壁材料106和nesl 108的刻蚀速率进行刻蚀。在一实施例中，设置在栅104、邻近间隙壁106的顶表面上以及在邻近nesl 108上的停止层112的一部分和ILD 110的一部分可被去除以形成接触开口116。
图案化工艺可导致抗蚀剂层114的非-配准(mis-registration)，其中该抗蚀剂层114可能非-对准使得间隙壁材料106的一部分113可能在开口115的形成期间暴露，以及第一ILD 110的一部分111可保持由该抗蚀剂层114覆盖。抗蚀剂层114的非配准量可根据特定的应用而不同，但是可随着开口116的深宽比(aspect ratio)的增加而变得更重要。例如，由于抗蚀剂层114非对准，包括小几何的微电子器件将更可能在接触和栅之间形成短路。
随后，设置于基板100的源/漏区103的一部分上的氮化物刻蚀停止层108可采用例如氮化物刻蚀工艺被去除，使得源/漏接触区域107可被暴露(图1c)。可选地，氮化物刻蚀停止层108可不出现于基板102上，并因此，nesl108将不必被去除。在另一实施例中，nesl刻蚀可以是可选的，取决于ILD去除工艺的选择性，如此当ILD刻蚀对基板具有选择性时，nesl刻蚀不需要执行。
由于该抗蚀剂层114的非配准，进入间隙壁材料106的暴露部分113的深度117可通过nesl 108刻蚀和/或ILD刻蚀形成。可形成的深度117可根据特定的工艺参数而变化。在一实施例中，深度117与接触刻蚀(nesl和/或ILD刻蚀)的刻蚀时间相关/对应。抗蚀剂层114可随后被去除且自对准多晶硅化物118可使用本领域公知的任何合适的自对准多晶硅化物工艺，例如但不限于，镍自对准多晶硅化物工艺和/或其他这样的自对准多晶硅化物工艺而形成在源/漏接触区域107上/中(图1d)。
第一接触金属120可形成在自对准多晶硅化物118上且可填充开口116(图1e)。在一实施例中，第一接触金属120可采用具有良好间隙填充特性的工艺形成以保证很少空隙或没有空隙形成在接触开口116中。这样的工艺可包括例如化学气相沉积(CVD)工艺，抛光工艺123(如化学机械抛光(CMP)工艺)可接着进行，以去除第一接触金属120(图1f)和停止层112。在一些情况下，第一接触金属可包括钨、钛、氮化钛和钛钨(titanium tungsten)的至少一种，但根据特定的应用可包括任何合适的接触金属。
在一实施例中，第一接触金属120可按栅104的平坦化顶表面121进行平坦化，即，其可通过抛光工艺123被抛光，使得第一接触金属120的顶表面122可与栅104的平坦化顶表面121平齐。抛光工艺123需包括足够的过抛光时间量以使任何可能连接该接触金属120和该栅104的条(stringer)被去除。抛光工艺123额外去除由于该抗蚀剂层114的非配准导致的间隙壁材料106的暴露部分113的深度117(回见图1c)。在一实施例中，第一接触金属120可包括非-锥形(non-tapered)的第一接触金属120。
额外栅刻蚀停止层124可形成在栅104的平坦化顶表面121上以及在接触金属120的顶表面122上(图1g)。第二ILD 126可形成在额外栅刻蚀停止层124上。可形成第二开口(未示出)，其可用第二接触金属128填充，第二接触金属128可以是导电耦合的且可形成与第一接触金属120的欧姆接触，且可设置于第一接触金属的顶表面122上。可形成第二开口，使得第二接触金属128可为锥形以及第二接触金属128的底部129相比于第二接触金属128的顶部130可为非常小，因为该自对准多晶硅化物无需形成为穿过此第二开口。
在一实施例中，顶部130包括比第二接触金属128的底部129的直径132更大的直径131。相比于现有技术的单接触工艺，第二接触金属128的大锥形可大大地增加接触至栅的配准窗口。因而，可形成比栅104高的堆叠接触结构133。第一接触结构120和第二接触结构128的金属一金属接触提供在晶体管结构内的堆叠接触结构133(其可包括垂直堆叠双接触结构)的形状上的更大的灵活性，因而增加非配准误差工艺窗口的量而没有产生触摸(短路)该栅104的可能性。
本发明的实施例提供(enable)一种简单、独特的方法用于采用金属栅工艺(例如双金属栅工艺)集成堆叠沟槽接触，在自对准多晶硅化物工艺期间金属栅工艺增加接触至栅的配准余量以及减少接触的深宽比。在一实施例中，源漏沟槽接触结构由两个垂直堆叠接触组成。金属栅可在第一源/漏接触之前形成，自对准多晶硅化物可在第一源/漏接触进行开口之后且在第二源/漏接触开口形成之前形成。现有技术的接触工艺使用了单沟槽接触工艺，其可能无法缩放到非常小的技术节点。
本发明进一步的优点包括提供具有更好的接触至栅的配准余量的更大的接触的形成，采用相比于现有技术工艺相对小的工艺改变。本发明的实施例容许增加的工艺窗口用于接触非对准，其将不会导致根据本发明的方法制造的微电子器件(例如晶体管)的叠加电容的改变。
虽然之前的描述具有可在本发明的方法中使用的具体的某些步骤和材料，但本领域技术人员将明白，可作出许多变型和替代。相应地，可知所有这样的变型、变更、替代和增加均视为落入由所附权利要求限定的本发明的精神和范围内。此外，可知微电子结构的某些方面是本领域公知的。因此，可知本文所提供的图仅示出关于实施本发明的示意微电子结构的部分。因此本发明不限于本文所描述的结构。

Claims (14)

1. 一种基板上的晶体管，包括：
包括栅电极层的栅结构；
所述栅结构的第一侧上的源区；
在所述栅结构的所述第一侧上并且与所述栅结构直接接触的第一间隙壁；
所述源区的顶面上的第一硅化物层，其中，所述第一硅化物层不延伸到所述第一间隙壁下面；
所述栅结构的第二侧上的漏区；
在所述栅结构的所述第二侧上并且与所述栅结构直接接触的第二间隙壁；
所述漏区的顶面上的第二硅化物层，其中，所述第二硅化物层不延伸到所述第二间隙壁下面；
所述晶体管上方的第一ILD层；
所述第一ILD层上方的第二ILD层；
所述第一ILD层中的耦合到所述第一硅化物层的第一接触金属；
所述第二ILD层内的直接耦合到所述第一接触金属的第二接触金属，其中，所述第二接触金属包括锥形结构，所述锥形结构具有在宽度上小于所述第二接触金属的顶部的底部；
所述第一ILD层中的耦合到所述第二硅化物层的第三接触金属；以及
所述第二ILD层内的直接耦合到所述第三接触金属的第四接触金属，其中，所述第四接触金属包括锥形结构，所述锥形结构具有在宽度上小于所述第四接触金属的顶部的底部。
2. 如权利要求1所述的晶体管，其中，所述第二接触金属还包括具有在宽度上小于所述第一接触金属的顶部的底部。
3. 如权利要求1所述的晶体管，其中，所述第四接触金属还包括具有在宽度上小于所述第三接触金属的顶部的底部。
4. 如权利要求1所述的晶体管，其中，栅电极层包括铪、锆、钛、钽或铝。
5. 如权利要求1所述的晶体管，其中，所述基板包括硅、绝缘体上硅、锗、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓或锑化镓。
6. 如权利要求1所述的晶体管，其中，所述第一间隙壁和所述第二间隙壁包括二氧化硅或氮化硅。
7. 如权利要求1所述的晶体管，其中，所述第一硅化物层和所述第二硅化物层包括镍自对准多晶硅化物。
8. 一种在基板上形成晶体管的方法，包括：
在所述基板上形成包括栅电极层的栅结构；
在所述栅结构的第一侧上形成源区；
在所述栅结构的所述第一侧上形成与所述栅结构直接接触的第一间隙壁；
在所述栅结构的第二侧上形成漏区；
在所述栅结构的所述第二侧上形成与所述栅结构直接接触的第二间隙壁；
在所述晶体管上方形成第一ILD层；
在所述第一ILD层中刻蚀第一沟槽接触开口以暴露所述源区的至少一部分；
通过所述第一沟槽接触开口，在所述源区的顶面上形成第一硅化物层；
用金属填充所述第一沟槽接触开口以形成第一沟槽接触；
在所述第一ILD层中刻蚀第二沟槽接触开口，所述第二沟槽接触开口暴露所述漏区的至少一部分；
通过所述第二沟槽接触开口，在所述漏区的顶部上形成第二硅化物层；
用金属填充所述第二沟槽接触开口以形成第二沟槽接触；
在所述第一ILD层上方形成第二ILD层；
在所述第二ILD层中刻蚀第三沟槽接触开口，所述第三沟槽接触开口暴露所述第一沟槽接触的至少一部分，其中，所述第三沟槽接触开口具有锥形形状，使得所述第三沟槽接触开口的底部在宽度上小于所述第三沟槽接触开口的顶部；
用金属填充所述第三沟槽接触开口以形成第三沟槽接触；
在所述第二ILD层中刻蚀第四沟槽接触开口，所述第四沟槽接触开口暴露所述第二沟槽接触的至少一部分，其中，所述第四沟槽接触开口具有锥形形状，使得所述第四沟槽接触开口的底部在宽度上小于所述第四沟槽接触开口的顶部；以及
用金属填充所述第四沟槽接触开口以形成第四沟槽接触。
9. 如权利要求8所述的方法，其中，所述第三沟槽接触开口还具有在宽度上小于所述第一沟槽接触的顶部的底部。
10. 如权利要求8所述的方法，其中，所述第四沟槽接触开口还具有在宽度上小于所述第二沟槽接触的顶部的底部。
11. 如权利要求8所述的方法，其中，栅电极层包括铪、锆、钛、钽或铝。
12. 如权利要求8所述的方法，其中，所述基板包括硅、绝缘体上硅、锗、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓或锑化镓。
13. 如权利要求8所述的方法，其中，所述第一间隙壁和所述第二间隙壁包括二氧化硅或氮化硅。
14. 如权利要求8所述的方法，其中，所述第一硅化物层和所述第二硅化物层包括镍自对准多晶硅化物。
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