CN110085569B - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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CN110085569B
CN110085569B CN201810072080.XA CN201810072080A CN110085569B CN 110085569 B CN110085569 B CN 110085569B CN 201810072080 A CN201810072080 A CN 201810072080A CN 110085569 B CN110085569 B CN 110085569B
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layer
conductive
conductive structure
contact hole
gap
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CN110085569A (zh
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张峰溢
李甫哲
陈界得
张翊菁
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Abstract

本发明公开一种半导体结构及其制作方法，该半导体结构包含接触洞，设于层间介电层中；阻障层，内衬接触洞并覆盖层间介电层；接触插塞，位于接触洞内的阻障层上；第一导电结构，一体构成于接触插塞上；第二导电结构，设于层间介电层上；以及间隙，位于第一导电结构与第二导电结构之间。间隙包含一垂直沟槽，向下凹陷至层间介电层中，以及一断口，位于阻障层中，其中断口延伸至第二导电结构下方构成一底切结构。

Description

半导体结构及其制作方法
技术领域
本发明涉及半导体技术领域，特别是涉及一种半导体结构及其制作方法。
背景技术
随着存储器制作工艺的线宽越来越小，在周边电路或核心电路中将M0钨金属层图案化成细线路时，常遭遇细线路间的短路问题。
因此，该技术领域仍需要一种改良的半导体结构及制作方法，以解决现有技术的不足与缺点。
发明内容
本发明的主要目的在于提供一种改良的半导体元件制作方法，可以解决现有技术的不足。
本发明一实施例提供一种半导体结构，包含一基底，包含一导电区域；一层间介电层，覆盖基底；一接触洞，设于层间介电层中，其中接触洞显露出部分的导电区域；一阻障层，内衬接触洞的表面并且覆盖层间介电层的一上表面；一接触插塞，位于接触洞内的阻障层上；一第一导电结构，一体构成于接触插塞上；一第二导电结构，设于层间介电层的上表面上，其中第二导电结构邻近第一导电结构；以及一间隙，位于第一导电结构与第二导电结构之间，其中间隙包含一垂直沟槽，向下凹陷至层间介电层中，以及一断口，位于阻障层中，其中断口延伸至第二导电结构下方构成一底切结构。
本发明另一实施例提供一种制作半导体结构的方法。首先提供一基底，包含一导电区域以及一层间介电层，层间介电层覆盖基底与导电区域。在层间介电层中形成一接触洞，其中接触洞显露出部分的导电区域。顺形的于接触洞的表面内衬一阻障层，并且使阻障层覆盖层间介电层的上表面。在阻障层上沉积一导电层，其中导电层填入接触洞，形成一接触插塞。进行一光刻及各向异性蚀刻制作工艺，蚀刻导电层、阻障层与层间介电层，以形成一第一导电结构，一体构成在接触插塞上，以及一第二导电结构，设于层间介电层的上表面，其中第二导电结构邻近第一导电结构。进行一选择性蚀刻制作工艺，选择性的仅蚀刻阻障层，以于第一导电结构与第二导电结构之间形成一间隙，其中间隙包含一垂直沟槽，向下凹陷至层间介电层中，以及一断口，位于阻障层中，其中断口延伸至第二导电结构下方构成一底切结构。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施方式，并配合所附的附图，作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用，并非用来对本发明加以限制者。
附图说明
图1至图5为本发明一实施例所绘示的制作半导体结构的方法的剖面示意图；
图6为本发明另一实施例所绘示的半导体结构的剖面示意图，其中显示出于第二导电结构下方形成孔洞；
图7至图9为本发明其它不同实施例所绘示的半导体结构的剖面示意图。
主要元件符号说明
1、2、2a、3 半导体结构
10 场效晶体管
30 接触插塞
100 基底
101 导电区域
102 栅极结构
110 层间介电层
110a、110b 接触洞
120 阻障层
130 导电层
140 间隙填补材料层
141 孔洞
150 蚀刻停止层
160 介电层
210 接触洞
220 接触插塞
300 接触插塞
AR 存储器阵列
BL 位线
L1 第一导电结构
L2 第二导电结构
SP、SP1～SP4 存储节点接垫
G1～G4 间隙
V1～V4 垂直沟槽
D1 断口
U1～U4 底切结构
具体实施方式
在下文中，将参照附图说明细节，该些附图中的内容也构成说明书细节描述的一部分，并且以可实行该实施例的特例描述方式来绘示。下文实施例已描述足够的细节使该领域的一般技术人士得以具以实施。
当然，也可采行其他的实施例，或是在不悖离文中所述实施例的前提下作出任何结构性、逻辑性、及电性上的改变。因此，下文的细节描述不应被视为是限制，反之，其中所包含的实施例将由随附的权利要求来加以界定。
请参阅图1至图5，其为本发明一实施例所绘示的制作半导体结构1的方法的剖面示意图。首先，如图1所示，提供一基底100，例如，半导体基底。所述半导体基底可以包含硅基底，但不限于此。根据本发明一实施例，基底100上可以设有一场效晶体管10以及一层间介电层110。场效晶体管10可以包含一导电区域101以及一栅极结构102。层间介电层110覆盖基底100、导电区域101以及栅极结构102。导电区域101可以是场效晶体管10的源极/漏极掺杂区。
接着，在层间介电层中形成一接触洞110a，其中接触洞110a显露出部分的导电区域101。然后顺形的于接触洞110a的表面内衬一阻障层120，并且使阻障层120覆盖层间介电层110的上表面，再于阻障层120上沉积一导电层130，其中导电层130填入接触洞110a，形成一接触插塞30。
根据本发明一实施例，阻障层120可以包含钛、氮化钛、钽、氮化钽、氮化钨或以上组合。根据本发明一实施例，导电层130可以是一金属内连线层，例如为M0金属层。根据本发明一实施例，所述M0金属层包含钨。
如图2所示，接着进行一光刻制作工艺及一各向异性蚀刻制作工艺，蚀刻导电层130、阻障层120与层间介电层110，以形成一第一导电结构L1，一体构成在接触插塞30上，以及一第二导电结构L2，设于层间介电层110的上表面，其中第二导电结构L2邻近第一导电结构L1。此外，在层间介电层110上另形成有一存储节点接垫SP。第一导电结构L1及第二导电结构L2为共平面且由同一金属内连线层所构成。
根据本发明一实施例，第一导电结构L1与第二导电结构L2均为导线线路结构，例如，存储器周边电路或核心电路内的细线路，但不限于此。根据本发明一实施例，此时，第一导电结构L1与第二导电结构L2仍未彼此完全分离，可能经由位于接触洞110a的上端转角处未被蚀刻掉的阻障层120连接在一起，导致细线路间的短路。
如图3所示，为了使第一导电结构L1与第二导电结构L2彼此完全分离，进行一选择性蚀刻制作工艺，例如，选择性的仅仅各向异性蚀刻阻障层120，而几乎不蚀刻导电层130，以于第一导电结构L1与第二导电结构L2之间形成一间隙G1，其中间隙G1包含一垂直沟槽V1，向下凹陷至层间介电层110中，以及一断口D1，位于阻障层120中，其中断口D1位于接触洞110a的上端转角处，延伸至第二导电结构L2下方构成一底切结构U1。断口D1显露出接触洞110a的上端转角处的层间介电层110。
在图3中可看出，第一导电结构L1与存储节点接垫SP之间也会有一间隙G2，包含一垂直沟槽V2，向下凹陷至层间介电层110中，以及因为选择性的蚀刻阻障层120产生的底切结构U2。从剖面看，可以发现间隙G2呈现十字形轮廓。
根据本发明实施例，前述仅蚀刻阻障层120的选择性蚀刻制作工艺可以利用干蚀刻制作工艺，例如，以Cl2作为蚀刻气体，在离子轰击模式，及温度小于80℃的条件下进行。此外，可以利用软蚀刻(soft etch)制作工艺，其中蚀刻气体包含(1)如F2、XeF2或NF3等含氟气体、(2)如NH3、N2H4或N2H2等含氮及氢气体，(3)如O2、O3或H2O等含氧气体。前述软蚀刻制作工艺可以在温度约250℃的条件下进行。
如图4所示，接着于第一导电结构L1及第二导电结构L2上沉积一间隙填补材料层140，并使间隙填补材料层140填入间隙G1及间隙G2中。随后，可以进行一化学机械研磨制作工艺，研磨间隙填补材料层140，使间隙填补材料层140的上表面与第一导电结构L1及第二导电结构L2的上表面齐平。间隙填补材料层包含氮化硅，但不限于此。
根据本发明另一实施例，若间隙填补材料层140未填满底切结构U1及底切结构U2，则会于第二导电结构L2下方形成孔洞141，如图6所示。
如图5所示，在完成上述化学机械研磨制作工艺之后，可以于间隙填补材料层140的上表面与第一导电结构L1及该第二导电结构L2的上表面沉积一蚀刻停止层150，例如氮化硅层等。然后，在蚀刻停止层150上沉积一介电层160，例如硅氧层。根据本发明实施例，介电层160可以是在存储器阵列(图未示)中的电容结构完成后才沉积，故介电层160的厚度会高于存储器阵列中的电容结构的高度。随后，在介电层160及蚀刻停止层150中以光刻及蚀刻制作工艺形成一接触洞210，显露出部分的存储节点接垫SP的上表面，再于接触洞210内形成一接触插塞220。
结构上，从图4可看出，本发明半导体结构1，包含基底100，其中基底100包含导电区域101；层间介电层110，覆盖基底100；一接触洞110a，设于层间介电层110中，其中接触洞110a显露出部分的导电区域101；阻障层120，内衬接触洞110a的表面并且覆盖层间介电层110的上表面；接触插塞30，位于接触洞110a内的阻障层110a上；第一导电结构L1，一体构成于接触插塞30上；第二导电结构L2，设于层间介电层110的上表面上，其中第二导电结构L2邻近第一导电结构L1；以及间隙G1，位于第一导电结构L1与第二导电结构L2之间，其中间隙G1包含垂直沟槽V1，向下凹陷至层间介电层110及接触插塞30的上部。以及断口D1，位于阻障层120中，其中断口D1延伸至第二导电结构L2下方构成底切结构U1。间隙填补材料层140，位于间隙G1中，其中间隙填补材料层140填入垂直沟槽V1及断口D1。
请参阅图7至图9，其为依据本发明其它不同实施例所绘示的半导体结构的剖面示意图，其中相同或类似的区域、层或元件仍沿用相同的符号来表示。
根据本发明一实施例，如图7所示，半导体结构2可以是存储器阵列AR中的存储节点接垫结构，其同样包括基底100，其中基底100包含导电区域101。在基底100上的层间介电层110内形成有位线BL，在层间介电层110中设有接触洞110b，使接触洞110b显露出部分的导电区域101。阻障层120内衬接触洞110b的表面并且覆盖层间介电层110的上表面。接触插塞300位于接触洞110b内。导电结构SP1及SP2，一体构成于接触插塞300上。间隙G3，位于导电结构SP1及SP2之间，其中间隙G3包含垂直沟槽V3，向下凹陷至层间介电层110，以及导电结构SP1、SP2下方的底切结构U3。间隙填补材料层140，位于间隙G3中，其中间隙填补材料层140填入垂直沟槽V3及底切结构U3。从剖面可看出，间隙G3可以呈现十字形图案。图8显示半导体结构2a，其中断口U3未被间隙填补材料层140填满，故留下孔洞141。
根据本发明另一实施例，如图9所示，半导体结构3同样是存储器阵列AR中的存储节点接垫结构，与图7的差异在于，图9中的间隙G4并非位于导电结构SP1、SP2的对称中央位置，而是较偏向接触洞110b的一侧。半导体结构3同样包括基底100，其中基底100包含导电区域101。在基底100上的层间介电层110内形成有位线BL，在层间介电层110中设有接触洞110b，使接触洞110b显露出部分的导电区域101。阻障层120内衬接触洞110b的表面并且覆盖层间介电层110的上表面。接触插塞300位于接触洞110b内。导电结构SP3及SP4，一体构成于接触插塞300上。间隙G4，位于导电结构SP3及SP4之间，其中间隙G4包含垂直沟槽V4，向下凹陷至层间介电层110，以及导电结构SP4下方的底切结构U4。间隙填补材料层140，位于间隙G4中，其中间隙填补材料层140填入垂直沟槽V4及底切结构U4。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (23)

1.一种半导体结构，其特征在于，包含：
基底，包含一导电区域；
层间介电层，覆盖该基底；
接触洞，设于该层间介电层中，其中该接触洞显露出部分的该导电区域；
阻障层，内衬该接触洞的表面并且覆盖该层间介电层的一上表面；
接触插塞，位于该接触洞内的该阻障层上；
第一导电结构，一体构成于该接触插塞上；
第二导电结构，设于该层间介电层的该上表面上，其中该第二导电结构邻近该第一导电结构；以及
间隙，位于该第一导电结构与该第二导电结构之间，其中该间隙包含一垂直沟槽，向下凹陷至该层间介电层中，以及一断口，位于该阻障层中，其中该断口延伸至该第二导电结构下方构成一底切结构。
2.如权利要求1所述的半导体结构，其中该垂直沟槽向下凹陷至该接触插塞的上部。
3.如权利要求1所述的半导体结构，其中另包含：
间隙填补材料层，位于该间隙中，其中该间隙填补材料层填入该垂直沟槽及该断口。
4.如权利要求3所述的半导体结构，其中该底切结构未被该间隙填补材料层填满，而在该阻障层及该间隙填补材料层之间构成一孔洞。
5.如权利要求3所述的半导体结构，其中该间隙填补材料层包含氮化硅。
6.如权利要求3所述的半导体结构，其中该间隙填补材料层的顶面与该第一导电结构的顶面、该第二导电层的顶面齐平。
7.如权利要求1所述的半导体结构，其中该阻障层中的该断口位于该接触洞的上端转角处。
8.如权利要求7所述的半导体结构，其中该断口显露出该接触洞的上端转角处的该层间介电层。
9.如权利要求1所述的半导体结构，其中该第一导电结构及该第二导电结构为共平面且由同一金属内连线层所构成。
10.如权利要求9所述的半导体结构，其中该金属内连线层为M0金属层。
11.如权利要求10所述的半导体结构，其中该M0金属层包含钨。
12.如权利要求1所述的半导体结构，其中该阻障层包含钛、氮化钛、钽、氮化钽、氮化钨或以上组合。
13.如权利要求1所述的半导体结构，其中该导电区域为一场效晶体管的源极/漏极掺杂区。
14.一种制作半导体结构的方法，其特征在于，包含：
基底，包含导电区域以及层间介电层，该层间介电层覆盖该基底与该导电区域；
在该层间介电层中形成一接触洞，其中该接触洞显露出部分的该导电区域；
顺形的于该接触洞的表面内衬一阻障层，并且使该阻障层覆盖该层间介电层的上表面；
在该阻障层上沉积一导电层，其中该导电层填入该接触洞，形成一接触插塞；
进行一光刻及各向异性蚀刻制作工艺，蚀刻该导电层、该阻障层与该层间介电层，以形成一第一导电结构，一体构成在该接触插塞上，以及一第二导电结构，设于该层间介电层的上表面，其中该第二导电结构邻近该第一导电结构；以及
进行一选择性蚀刻制作工艺，选择性的蚀刻该阻障层，以于该第一导电结构与该第二导电结构之间形成一间隙，其中该间隙包含一垂直沟槽，向下凹陷至该层间介电层中，以及一断口，位于该阻障层中，其中该断口延伸至该第二导电结构下方构成一底切结构。
15.如权利要求14所述的方法，其中另包含：
在该第一导电结构及该第二导电结构上沉积一间隙填补材料层，并使该间隙填补材料层填入该间隙中；以及
研磨该间隙填补材料层，使该间隙填补材料层的上表面与该第一导电结构及该第二导电结构的上表面齐平。
16.如权利要求15所述的方法，其中该间隙填补材料层包含氮化硅。
17.如权利要求14所述的方法，其中该阻障层中的该断口位于该接触洞的上端转角处。
18.如权利要求17所述的方法，其中该断口显露出该接触洞的上端转角处的该层间介电层。
19.如权利要求14所述的方法，其中该第一导电结构及该第二导电结构为共平面且由同一金属内连线层所构成。
20.如权利要求19所述的方法，其中该金属内连线层为M0金属层。
21.如权利要求20所述的方法，其中该M0金属层包含钨。
22.如权利要求14所述的方法，其中该阻障层包含钛、氮化钛、钽、氮化钽、氮化钨或以上组合。
23.如权利要求14所述的方法，其中该导电区域为一场效晶体管的源极/漏极掺杂区。
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CN110085569A (zh) 2019-08-02

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