CN103378037A - 用于焊料连接的方法和装置 - Google Patents

用于焊料连接的方法和装置 Download PDF

Info

Publication number
CN103378037A
CN103378037A CN201210461253XA CN201210461253A CN103378037A CN 103378037 A CN103378037 A CN 103378037A CN 201210461253X A CN201210461253X A CN 201210461253XA CN 201210461253 A CN201210461253 A CN 201210461253A CN 103378037 A CN103378037 A CN 103378037A
Authority
CN
China
Prior art keywords
stud bumps
conductive terminal
substrate
layer
scolder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201210461253XA
Other languages
English (en)
Other versions
CN103378037B (zh
Inventor
余振华
蔡豪益
李建勋
刘重希
陈宪伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN103378037A publication Critical patent/CN103378037A/zh
Application granted granted Critical
Publication of CN103378037B publication Critical patent/CN103378037B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02123—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area
    • H01L2224/02125—Reinforcing structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02335—Free-standing redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0239—Material of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/024—Material of the insulating layers therebetween
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0391—Forming a passivation layer after forming the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05024—Disposition the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05171—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05562—On the entire exposed surface of the internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05664—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05669—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/13076—Plural core members being mutually engaged together, e.g. through inserts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/13078—Plural core members being disposed next to each other, e.g. side-to-side arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1405—Shape
    • H01L2224/14051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

用于焊料连接的方法和装置。一种装置包括在表面上具有导电终端的衬底；位于衬底的表面和导电终端的上方的钝化层；位于钝化层中的暴露出导电终端的一部分的开口；接合至开口中的导电终端并在垂直于衬底的表面的方向上延伸的至少一个柱形凸块；以及在开口中的导电终端上形成的并围绕所述至少一个柱形凸块的焊料连接件。本发明还公开了用于形成焊料连接的方法。

Description

用于焊料连接的方法和装置
技术领域
本发明涉及半导体封装，具体而言涉及用于焊料连接的方法和装置。
背景技术
封装和集成电路工艺中的新近发展使得安装在中介层或衬底上的封装件越来越多地应用于形成安装至印刷电路板(“PCB”)的模块从而完成系统。由于高级集成电路越来越多地应用于更小且更紧凑的器件(诸如便携式器件)中，使得对于将集成电路器件连接到PCB的更小、更薄、成本更低的技术的需求持续增加。
使用焊料凸块和焊球来连接器件也变得更加普遍。在典型的布置中，可以将焊料凸块接合(solder bumped)的集成电路管芯安装在由层压材料、硅、陶瓷、膜等形成的中介层的顶面上。该中介层的下表面则可以具有以对应于PCB上的接合盘(land)或焊盘图案的图案布置的焊球。这可以被称为“倒装芯片”封装件，因为集成电路是“面朝下”或倒装地安装在中介层上。在将集成电路安装在中介层上之后，可以将组件安装在PCB上。堆叠的管芯、或堆叠封装件(package on package)布置(包括中介层)的使用都是已知的。
中介层的应用以及随之而来的成本和制造步骤增加了制造完整系统的成本并降低了产量。一种替代方式是使用晶圆级加工(“WLP”)直接在半导体晶圆的面上形成焊料连接件，通常为焊球。可以同时在整个晶圆上实施这些步骤，实现规模经济并降低成本。另外，这种方法能够消除对昂贵的中介层以及随之而来的生产中介层所需的制造和测试工艺的需要。
在应用WLP封装中，将焊球接合至PCB表面以及接合至晶圆或集成电路管芯上的钝化后互连(“PPT”)连接件。因为在系统操作过程中由于PCB材料和半导体晶圆之间的热膨胀系数的差异而在组件上存在热应力，所以此时焊球具有增大的应力。与采用中介层的“倒装芯片”封装件相比，利用焊料连接件将管芯直接安装到PCB使得焊料连接件上的应力增大。
在测试中，由于热循环测试中的应力，焊料连接件表现出“断路”故障。焊球可能会碎裂，尤其是在PPI连接的附近。因此，需要改进的焊料连接件。
发明内容
为了解决上述技术问题，一方面，本发明提供了一种装置，包括：衬底，在表面上具有导电终端；钝化层，上覆所述衬底的表面和所述导电终端；开口，位于所述钝化层中，所述开口暴露出所述导电终端的一部分；至少一个柱形凸块，接合至所述开口中的导电终端并在垂直于所述衬底的表面的方向上延伸；以及焊料连接件，形成在所述开口中的导电终端上并包围所述至少一个柱形凸块。
在所述的装置中，所述至少一个柱形凸块包含选自基本上由铜和金所组成的组中的一种材料。
在所述的装置中，所述导电终端进一步包括上覆所述钝化层中的开口并位于所述至少一个柱形凸块下方的凸块下金属化层。
在所述的装置中，所述导电终端进一步包括上覆所述钝化层中的开口并位于所述至少一个柱形凸块下方的凸块下金属化层，其中，所述导电终端进一步包括上覆所述凸块下金属化层并位于所述至少一个柱形凸块下方的处理层。
在所述的装置中，所述导电终端进一步包括上覆所述导电终端并位于所述至少一个柱形凸块下方的处理层。
在所述的装置中，所述导电终端进一步包括上覆所述导电终端并位于所述至少一个柱形凸块下方的处理层，其中，所述处理层包含选自基本上由金、镍、钯、化学镀镍-浸金和化学镀镍-化学镀钯-浸金所组成的组中的一种材料。
在所述的装置中，所述至少一个柱形凸块进一步包括至少两个柱形凸块。
在所述的装置中，所述至少一个柱形凸块进一步包括至少两个柱形凸块，所述至少一个柱形凸块进一步包括三个或三个以上的柱形凸块。
在所述的装置中，所述焊料连接件包括焊球。
在所述的装置中，所述衬底包括半导体晶圆。
另一方面，本发明提供了一种装置，包括：半导体衬底，在所述半导体衬底中形成有多个集成电路；多个导电终端，形成在所述半导体衬底的表面上并连接到所述半导体衬底内的电路；至少一个钝化层，形成在所述半导体衬底的表面上方；开口，设置在所述钝化层中，所述开口暴露出所述多个导电终端的上表面的一部分；至少一个柱形凸块，形成在所述开口中的至少一些导电终端上，所述至少一个柱形凸块接合至所述导电终端并在垂直于所述半导体衬底的表面的方向上延伸；以及焊料连接件，形成在每一个导电终端上方并围绕位于所述至少一些导电终端上的至少一个柱形凸块。
所述的装置进一步包括凸块下金属化层，所述凸块下金属化层形成在钝化层上方，延伸到所述开口中且覆盖所述导电终端，并且所述凸块下金属化层位于所述至少一些导电终端上的至少一个柱形凸块的下方。
所述的装置进一步包括处理层，所述处理层形成在所述导电终端上方并位于所述至少一些导电终端上的至少一个柱形凸块的下方。
在所述的装置中，所述至少一个柱形凸块的每一个均包含选自基本上由铜和金所组成的组中的一种材料。
在所述的装置中，对于所述至少一些导电终端的至少一个子集，所述至少一个柱形凸块进一步包括在所述开口中的导电终端上形成的两个或两个以上的柱形凸块。
又一方面，本发明提供了一种方法，包括：提供具有表面的衬底，在所述表面上形成有多个导电终端；在所述表面上方形成钝化层；在所述钝化层中形成开口，暴露出所述导电终端；对于所述多个导电终端中的至少一些导电终端，形成接合至所述导电终端并从所述导电终端开始在垂直于所述衬底的表面的方向上延伸的至少一个柱形凸块；以及在所述导电终端上方形成焊料连接件，所述焊料连接件围绕所述多个导电终端中的所述至少一些导电终端中的每一个导电终端上的至少一个柱形凸块。
在所述的方法中，提供所述衬底包括提供其上制造集成电路的半导体晶圆。
在所述的方法中，形成所述至少一个柱形凸块进一步包括形成柱形凸块的堆叠件。
在所述的方法中，在形成接合至所述多个导电终端中的至少一些导电终端的至少一个柱形凸块之后，所述多个导电终端中的其余导电终端不具有柱形凸块。
在所述的方法中，形成所述至少一个柱形凸块包括形成两个或两个以上的柱形凸块。
附图说明
为了更加完整地理解示例性实施例及其优点，现在参考结合附图所进行的以下描述，其中：
图1示出了用于举例说明实施例的结构的横截面视图；
图2示出了实施例结构的横截面视图；
图3示出了在中间加工步骤中的实施例结构的横截面视图；
图4示出了在其他加工之后的图3的结构的横截面视图；
图5示出了在其他加工之后的图4的结构的横截面视图；
图6示出了在其他加工之后的图5的结构的横截面视图；
图7示出了在中间加工步骤中的举例说明可选实施例的结构的横截面视图；
图8示出了在其他加工之后的图7的结构的横截面视图；
图9示出了在其他加工之后的图8的结构的横截面视图；
图10示出了又一可选结构的横截面视图；
图11示出了实施例结构的俯视图；
图12示出了与实施例一起使用的结构的平面图；
图13A示出了用于图12的结构的实施例的横截面视图；图13B示出了用于图12的结构的另一实施例的横截面视图；以及图13C示出了用于图12的结构的另一实施例的横截面视图；
图14示出了方法实施例的流程图；
图15示出了可选方法实施例的流程图；以及
图16示出了另一方法实施例的另一流程图。
除非另有说明，不同附图中的相应数字和符号一般是指相应的部件。绘制附图是为了清楚地说明优选实施例的相关方面，因而不必按比例绘制。
具体实施例
在下面详细论述本发明优选实施例的制造和使用。然而，应该理解，示例性实施例提供了许多可以在各种具体环境中实现的可应用的发明构思。所论述的具体实施例仅是制造和使用实施例的示例性具体方式，并且这些实例不用于限制本说明书的范围，也不用于限制所附权利要求的范围。
本文中的实施例是示例性实例，而不用于限制本发明的范围，也不用于限制所附权利要求的范围。本发明的实施例包括用于与电终端(诸如焊盘或接合盘)形成焊料连接的方法。焊料连接包括从电终端以垂直方向延伸的至少一个柱形凸块(stud bump)，并且焊料连接件(诸如焊球)形成在柱形凸块周围并包围柱形凸块。因为柱形凸块比固体焊料连接件更好地增加强度并且附着于电终端表面上的材料，因此所得到的焊料连接具有较少的由于例如热应力引起的故障。柱形凸块和焊球可以以晶圆级工艺形成，随后可以分割(singulate)器件并将其安装至系统板或PCB。可以在具有诸如接合盘或焊盘的电终端的晶圆、管芯、或衬底上形成焊料连接。可以直接在晶圆的接合焊盘上或者在钝化后互连方案中作为再分配层(“RDL”)的一部分的焊盘上形成焊料连接。
图1示出了说明性示例结构11的横截面图以说明该实施例的使用。示出具有设置在有源表面上的焊料连接件15的衬底13，其可以是半导体晶圆或其他衬底。焊料连接件15可以是焊料凸块或焊球。在本申请中，术语“焊料”的使用包括但不限于铅基焊料和无铅焊料，诸如用于铅基焊料的Pb-Sn组分，和包括锡、铜、银或“SAC”组分的无铅焊料，以及具有共熔点并在电子应用中形成导电焊料连接的其他共晶体。对于无铅焊料，可以使用具有不同组成的SAC焊料，诸如SAC 105(Sn 98.5％，Ag 1.0％，Cu0.5％)、SAC 305、SAC 405等。无铅焊料连接件(诸如焊球)也可以由SnCu化合物形成而不使用银(Ag)。可选地，无铅焊料连接件可以包括锡和银(Sn-Ag)以及任何铜。
衬底13可以是半导体衬底，诸如硅、锗、砷化镓和其他半导体材料。该衬底可以是中介层，诸如硅、层压板、陶瓷、膜、FR4、或其他电路板材料，并且实施例也可以应用于这些衬底。在一些实施例中，衬底是硅晶圆，其包括在使用本文中的实施例之前制造的用于与系统板形成连接的许多集成电路。
图1的横截面视图示出了单行焊料连接件，通常，焊料连接件是焊球，但也可以使用其他形状，诸如柱形、立方体、正方形和圆柱形。当在栅格上形成焊球阵列时，所得到的集成电路的封装件可以被称为“球栅阵列”或“BGA”；而球可以被称为“BGA球”；然而，本文中所描述的实施例并不限于BGA封装件或BGA球。这些实施例并不限于球形或球状的焊料连接件。在实际应用中，对于集成电路可以设置数百个甚至数千个这些焊料连接件15。半导体晶圆还可以具有在其上形成的这些集成电路中的许多集成电路。
例如，在系统中使用时，利用热回流将衬底13安装到另一板或组件，诸如系统PCB板(未示出)。以与系统PCB上的导电焊盘或接合盘对准的方式设置焊料连接件15，然后将焊料连接件15设置成与该焊盘或接合盘物理接触。可以使用自动化或手工操作的拾取和自动对准工具，诸如机器手臂。然后热回流工艺使得焊料连接件15熔化和冷却从而与PCB板或组件形成物理焊料连接和电焊料连接。因此，焊料连接件15变成与系统电路板物理连接和电连接。在组装后，在测试和使用过程中，衬底13和焊料连接件15暴露于热应力。在由随后的热循环引起机械应力的过程中，焊料连接件15必须承受机械移动或机械力的应力，诸如在热循环过程中由于热膨胀系数不匹配而引起的应力。如果焊料连接件15不能承受这种应力，则可能发生焊料碎裂。如果出现碎裂，则可能会发生电气断路，导致测试或现场中的器件故障。
图2示出了焊料连接实施例12的横截面。在图2中，衬底13具有提供与衬底中的电路(未示出)的电连接的导电终端17。导电终端17可以是例如集成电路的接合焊盘。可选地，终端17可以是多层衬底中的迹线(trace)。层19为形成用于保护例如衬底13中的电路的钝化层。其可以是聚酰亚胺层、氮化硅层、聚合物或其他保护性介电材料。在本实施例12中，形成再分配层(“RDL”)并且该RDL将终端17连接至焊料连接件15。所示出的第一聚合物层21形成RDL的绝缘层。PPI迹线23为导体，诸如铜、铝、金等，PPI迹线23形成在聚合物层21上方并通过开口延伸从而在一端与终端17形成电连接和物理连接。示出设置在迹线23上方的第二聚合物层25，其是另一介电层或绝缘层。焊料连接件15形成在位于第二聚合物层25中的暴露出一部分迹线23的开口中，该部分迹线23形成焊盘或球接合盘。凸块下金属化(“UBM”)层27形成在第二聚合物层25上方并延伸至开口中，覆盖迹线23的上表面。使用UBM材料来增加焊料的粘附性，并在焊料与迹线23的球接合盘部分之间的连接中释放一些应力。用于UBM层27的金属包括但不限于：铜、铝、镍、钛、和铬中的一种或多种。UBM的关键特性在于与导体材料(在此处为迹线23)的粘附性，提供焊料扩散屏障，提供用于安装焊料连接件的可焊接性和可润湿性，与用于形成焊料连接的工艺的兼容性，以及在与导体23连接时提供低电阻。
示出了形成在UBM层27上并且在垂直方向上远离衬底13的水平上表面延伸的柱形凸块29。该柱形凸块29可以利用毛细管引线接合设备(capillary wire bonding equipment)来形成例如热压接合(“TCB”)而形成。球和针脚操作(ball and stitch operation)可以用于将引线球(wire ball)机械接合至UBM层27，然后当球接合毛细管工具在远离UBM表面的方向上向上移动时，引线接合操作通过切割接合引线的垂直部分形成柱形凸块。这种柱形凸块可以由铜、金或其他引线接合材料形成。如在下文中将进一步描述的，对于焊料连接件15，可以形成多于一个柱形凸块29。可以使用两个、三个、四个或四个以上的柱形凸块29。柱形凸块的直径可以是例如50-80微米。柱形凸块的高度可以为80-160微米。当柱形凸块是在球和针脚操作中形成时，柱形凸块具有宽基部和窄或尖顶部。在横截面中，其通常可以呈现出具有窄顶部的柱形。
然后在UBM层27上形成焊料连接件15，其可以是焊球，并且该焊料连接件15围绕并包围柱形凸块29。焊球可通过在UBM层27、球接合盘的位置处将所选的焊料材料印到(stenciling)第二聚合物层25上然后对该焊料材料进行焊料热回流工艺而形成。熔化的焊料的表面张力导致球形焊球围绕如图2所示的柱形凸块29形成。实施例的柱形凸块增加机械强度并防止在焊料连接件5与UBM层27相接的临界区域处出现球碎裂。而且，即使在焊料-UBM边界附近确实形成了一些焊料碎裂，柱形凸块提供与焊球的其余部分的额外导电连接，防止形成电气“断路”，从而不会发生电气故障。
图3示出了在中间加工步骤中的另一可选实施例10的横截面图，用于说明另一方法实施例。在图3中，示出了具有导电终端17的衬底13，导电终端17可以是集成电路接合焊盘。可选地，导电终端17可以是另一互连终端。示出了上覆衬底13和终端17的钝化层19。其可以是例如聚酰亚胺层；其他钝化材料包括例如电介质，诸如氮化硅。示出了UBM层27，该UBM层27设置在终端17上方并与该终端17接触，覆盖上表面，并部分上覆钝化层19的一部分。注意到，在该实施例中，UBM层27直接位于终端17上方，也就是说，在该实施例中没有使用再分配层RDL。
图4示出了进行其他工艺步骤之后的实施例10的横截面。在图4中，衬底13和终端17以及钝化层19和UBM层27如前文所述进行布置，因而在此不再进一步描述。提供表面处理(surface finish)作为层31。该表面处理可以是化学镀，诸如镍(Ni)、金(Au)、镍和金、钯、铂、或用于焊料连接的其他表面处理。可以使用组合镀处理，诸如“ENIG”-化学镀镍-浸金，或“ENEPIG”-化学镀镍-化学镀钯-浸金。举例来说，这些处理层有助于可焊接性以及铜柱形凸块的接合。
图5示出了进行其他加工步骤之后的图4的结构10的横截面。为了从图4过渡到图5，衬底13、终端17、钝化层19、UBM层27和处理层31均如前文所述进行布置。然后在处理层31上方形成柱形凸块29。可以例如利用毛细管球接合工具来实施球接合并且随着该工具的垂直远离移动切割接合引线以形成柱形凸块部分来形成柱形凸块29。柱形凸块机械接合到处理层31的表面并在垂直于衬底13的水平上表面的方向上延伸。柱形凸块可以是铜、金或在球接合设备中用作接合引线的其他材料。可以使用热压接合。可以使用超声能量来形成柱形凸块并且更好地将其接合至处理层31。在每个连接件中都可以形成多个柱形凸块29；或者仅形成一个，如在图5的实施例中所示。
图6示出了进行其他工艺步骤之后的图5的结构10的横截面。衬底13、终端17、钝化层19、UBM层27、处理层31和柱形凸块29均如图5中所示进行布置。在本示例性实施例中，形成焊料连接件15；其是焊球，但也可以使用其他形状。为了形成焊料连接件15，在衬底上例如通过模板扫描焊膏来设置焊料。利用热回流来回流焊料，并且由于焊料在其熔融状态下的表面张力性质，当其冷却时，如图所示，在柱形凸块29周围形成球状球，并且该球状球包围柱形凸块29并位于处理层31上方。在实施例中，处理层和UBM的直径可以为约200-240微米，而在处理层31上形成的焊球的直径因此会更大一些，例如为220-280微米。焊球之间的间距可以为例如300-400微米。柱形凸块的直径可以为例如50-80微米。柱形凸块的高度可以为80-160微米。
由于柱形凸块29与处理层31的接合良好，并且柱形凸块在垂直方向上远离衬底13朝向焊料连接件15的中心延伸，因此通过使用柱形凸块提供了额外的强度。具体地，柱形凸块在接近于焊料连接件15与处理层31之间的材料边界的区域中提供了增加的强度。在该区域中，在现有技术的焊球的热循环测试中已经观察到球碎裂。即使确实出现球碎裂，柱形凸块29(其为铜或金或其他导电材料)增加了从焊球15的中心周围向导电终端17的额外的电通路，并因此阻止由焊球碎裂引起的“断路”电连接。
上面所示的实施例示出了与使用柱形凸块一起使用UBM层。图7示出了实施例14的横截面视图，其类似于上述实施例，但是在该实施例中未使用UBM。
在图7中，描述了处于中间工艺步骤的实施例14。衬底13具有导电终端17，举例来说，其可以是电连接于衬底中的其他电路的集成电路接合焊盘或钝化后互连终端。在终端上形成表面处理层31。在一个实施例中，可以使用化学镀膜。作为实例，该表面处理层31可以是镍、金、钯、ENIG或ENEPIG。
图8示出了进行一些其他加工之后的图7的实施例14。在图8中，形成钝化层19，其可以是聚酰亚胺、聚合物、氮化物或其他电介质，并且钝化层19位于衬底13和处理层31的一部分的上方。提供位于层19中的开口作为用于接收焊料连接的球接合盘。描绘了形成在开口中的处理层31上，并在垂直方向上向上(以这种任意取向，当然，可以翻转衬底13然后使柱形凸块29在附图中向下延伸，这种取向仅是用于举例说明，而不是意在限制)延伸的一对柱形凸块29。在本实施例中，不使用上文所述的实施例中示出的UBM材料。而且，在柱形凸块为金并且导电终端17为铜的示例实施例中，可以将处理层31整体省略，并且仍可获得良好的结果，这是因为金柱形凸块与铜终端形成了极好的机械接合。
图9示出了由图8在进行其他加工之后得到的完整结构14的横截面。在位于钝化层19中的开口中的处理层31的上方形成焊料连接件15，其通常是焊球但不限于焊球。该焊料连接件围绕并包围这对柱形凸块29。如前文所述，柱形凸块提供了额外的强度和额外的电通路，防止由于焊料碎裂引起的“断路”故障，焊料碎裂可能是由与材料的热失配相关的热循环以及机械应力引起的。
图10示出了实施例18的横截面，实施例18是可选实施例。在实施例18中，对每一个柱形凸块都进行进一步堆叠以形成柱形凸块堆叠件39。使用堆叠的柱形凸块增加了柱形凸块的高度，而且通过增加焊球中的材料也增加了焊球的尺寸。而且，使用堆叠的柱形凸块使得柱形凸块更进一步地延伸至焊料连接件15中，在顶部封装件41上的焊盘38和衬底13之间加入了另外的电通路，从而使得如果在衬底13附近发生碎裂时，电连接不会被破坏。堆叠的柱形凸块39也可以利用具有毛细管的引线焊接接合工具以及在第一个柱形凸块上堆叠一个柱形凸块来形成。本实施例18的堆叠的柱形凸块39也可以用于图2的实施例中以及图6(包括UBM)和图9(没有UBM)的实施例中，并且这些可选实施例中的每一个都构成了被认为是在所附权利要求范围内的另外的实施例。
图11示出了实施例的焊料连接件的俯视图。在图11中，示出了直径大于例如240微米的连接件15。所示出的柱形凸块的数目为4，在另一示例实施例中，使用1个、2个和3个柱形凸块。在一些实施例中，使用3个或3个以上柱形凸块实现了极好的结果，但实施例并不限于任何特定数目的柱形凸块。在实例中，位于焊料连接件下方的UBM层或处理层的直径D1为约240微米，而柱形凸块的直径为50-80微米，并且从衬底延伸至焊料连接件中的高度为约80-160微米。但是，这些尺寸的范围都不是限制性的，实施例可以包括具有更大或更小直径或者更大或更小高度的柱形凸块。也可以制造更大或更小的焊料连接件。
图12示出了结合了焊料连接件的实施例的衬底43的平面图。在该非限制性实例中，示出了为13×13的焊料连接件阵列，总共169个焊料连接件15。在具有焊球连接件的衬底的热循环测试中，观察焊球中经受的应力。焊球经受的应力是不均匀的，在中心的“中性点(neutral point)”或焊料连接件阵列的中心附近的球中观察到最低的应力。通过绘制每一个球到中性点的距离(“DNP”)并观察热循环中的应力，确定最大的应力出现在四个角，诸如在图中的区域45，这些是具有最大DNP的焊球，最大DNP在此处以与中心球的半径表示并且被标记为DNP1。较接近于中性点但仍经受大量应力的球是在阵列的外侧行附近的球，其可以被说成是位于大于或等于另一距离(示出为DNP2)但小于DNP1的DNP处。较接近于中心且位于半径DNP2内部的球由于热效应而经受较低的应力。
图13A、图13B和图13C示出了供图12的布置使用的三个焊料连接件49、51和53的横截面视图。在图13A中，在横截面中可看到焊料连接件49具有两个柱形凸块；在其他可选实施例中，焊料连接件49可以包括3个、4个或4个以上的柱形凸块。在实施例方法中，识别用于阵列或集成电路图案的距中性点最远(距离DNP1)的焊料连接件可以利用该方法来实现。在图13B中，也以横截面示出的焊料连接件51具有单个柱形凸块。在方法实施例中，距中性点小于距离DNP1但大于或等于较小的距离DNP2的连接件可以利用如连接件51中的单个柱形凸块来实现。在图13C中，焊料连接件53说明了未使用柱形凸块的常规焊料连接件。对于最接近中性点的焊料连接件，其距中性点的距离小于DNP2，对这些焊料连接件可以不提供柱形凸块，因为在这些位置观察到的机械应力小于在距中性点的最大距离DNP1处或第二较小距离DNP2处观察到的机械应力。通过仅在阵列或器件的一些但不是全部的焊料连接件中使用实施例的柱形凸块，仍可获得实施例的优点，同时降低了系统成本并增加了产量。
图14示出了方法实施例的流程图。在步骤61中，提供具有导电终端的衬底。在步骤63中，在衬底上方形成钝化层，并在钝化层中提供开口，暴露出导电终端的一部分。在步骤65中，可选地实施形成UBM层的步骤。在步骤67中，在导电终端上方设置处理层。在步骤69中，在导电终端上形成一个或多个柱形凸块，并且柱形凸块在垂直方向上远离衬底表面延伸。在步骤71中，在导电终端上方形成焊料连接件。该实施例对应于例如用于形成图6的实施例的方法。
图15示出了可选方法实施例。在图15中，该方法开始于步骤73，其中在衬底上方沉积导电终端。在步骤75中，在导电终端上方沉积处理层。在步骤77中，在衬底上方形成钝化层并形成开口以暴露出导电终端和处理层。在步骤79中，在处理层上形成一个或多个柱形凸块并将其电连接到导电终端。在步骤81中，在柱形凸块上方形成焊料连接件并包围柱形凸块。该方法实施例对应于例如用于形成图9的实施例的方法。
图16示出了另一方法实施例的流程图。在步骤83中，在衬底上形成导电终端阵列。在步骤85中，对每一个导电终端测定与位于阵列中心的中性点的距离。在步骤87中，对于与中性点具有最大距离的导电终端，对每一个导电终端形成多于两个柱形凸块的多个柱形凸块。
在步骤89中，识别小于距中性点的最大距离但大于距中性点的另一较小距离的导电终端。对于这些导电终端的每一个，在其中每一个上形成至少一个柱形凸块。在阵列中的其余导电终端中没有形成柱形凸块。
然后，在步骤91中，在导电终端上方形成焊料连接件。应注意，一些导电终端不具有柱形凸块，位于大于或等于距中性点的较小距离的距离处的导电终端具有至少一个柱形凸块，位于距中性点最大距离处或位于等于该最大距离处的导电终端具有两个以上柱形凸块。替代方案包括对于那些位于最大距离处的连接件使用两个柱形凸块，对于位于中间距离的连接件使用至少一个柱形凸块，而对于较接近于中性点的连接件则不使用柱形凸块。
上文中描述的柱形凸块的数目是实例。可选实施例可以使用每个凸块更多或更少的柱形凸块。所关注的关系是到中性点的距离DNP和柱形凸块的数目。随着DNP变大，位于该距离或者更大距离处的球会表现出更大的机械应力。对于位于特定DNP或更大距离处的焊球，可以增加待使用的柱形凸块的数目。
在一些应用中，由于焊球的布置，最大DNP可以相对较低。在这种情况下，可以使用仅在观察到最大应力的焊球中使用柱形凸块的可选实施例，也就是说，最外侧角处的球可以具有单个柱形凸块。在其他情况下，在焊球阵列相当大时，一些焊球可能位于非常大的DNP处，一些焊球可能位于中间DNP处，以及一些焊球可能接近于中性点，具有相应较低的DNP。在这样的实例中，作为另一可选实施例，到中性点的距离大于或等于第一预定阈值的焊球可以具有每个焊球多达四个或四个以上的柱形凸块，到中性点的距离大于第二预定阈值但小于第一预定阈值的焊球可以具有例如每个焊球一个或两个柱形凸块，而到中性点的距离小于第一和第二阈值的焊球在每个焊球中可以没有柱形凸块。对原型的热循环测试和跌落测试(droptest)可以用于确定在特定器件中有多少焊球需要柱形凸块，以及为确保获得可靠的器件预定的DNP阈值应该是多少。在该确定中，管芯尺寸、焊球尺寸、以及球密度和球间距都是考虑的因素，它们随应用而变化，并且许多替代方式也是可以的。
使用实施例提供了在不使用中间中介层的情况下与用于在系统板上的“倒装芯片”布置(具有面向PCB板的有源表面)中安装集成电路的焊料连接相兼容的改进的晶圆级工艺。使用实施例有利地提供了较薄的组件和较少的部件，降低成本，并由于较简单的布置而减少可能的失效机制。使用设置在实施例的焊球连接件内部的柱形凸块减少了球碎裂故障并减少或消除了在利用现有技术方法形成的焊料连接(诸如焊球)中观察到的电气断路。包括实施例的焊料连接件可以在不使用倒装芯片中介层的情况下稳定地使用，从而将集成电路直接安装到PCB板。也可以实现晶圆级集成。在本方法中，在晶圆阶段(wafer stage)完成多个集成电路集成并且其中的若干集成电路作为一个组件在单次焊料回流操作中一起安装到系统板。可以以“堆叠封装件”或堆叠管芯布置的方式在晶圆的顶部上垂直地堆叠器件。然后可以使用采用柱形凸块的实施例焊料连接来将堆叠的器件安装到系统板。
在实施例中，一种装置包括在表面上具有导电终端的衬底；上覆衬底的表面和导电终端的钝化层；位于钝化层中的暴露出导电终端的一部分的开口；与开口中的导电终端接合并在垂直于衬底表面的方向上延伸的至少一个柱形凸块；以及在开口中的导电终端上形成的并包围所述至少一个柱形凸块的焊料连接件。在另一实施例中，上述装置包括选自铜和金的至少一个柱形凸块。在又一实施例中，在上述装置中，导电终端进一步包括上覆钝化层中的开口并位于所述至少一个柱形凸块下方的凸块下金属化UBM层。
在另一实施例中，如上文所述提供该装置，并且导电终端进一步包括上覆UBM层并位于所述至少一个柱形凸块下方的处理层。在另一可选实施例中，提供如上文所述的装置，并且导电终端进一步包括上覆导电终端并位于所述至少一个柱形凸块下方的处理层。在又一实施例中，处理层选自金、镍、钯、化学镀镍-浸金“ENIG”、以及化学镀镍-化学镀钯-浸金“ENEPIG”。
在其他实施例中，在上述装置中，所述至少一个柱形凸块进一步包括至少两个柱形凸块。在又一些实施例中，在上述装置中，所述至少一个柱形凸块进一步包括三个或三个以上的柱形凸块。在又一些实施例中，在上述装置中，焊料连接件包括焊球。在又一实施例中，在上述装置中，衬底包括半导体晶圆。
在另一实施例中，一种装置包括半导体晶圆，在该半导体晶圆中形成有多个集成电路；在半导体晶圆的表面上形成的并连接到半导体晶圆内的电路的多个导电终端；在半导体晶圆表面上方形成的至少一个钝化层；设置在钝化层中的开口，暴露出该多个导电终端的上表面的一部分；在开口中的至少一些导电终端上形成的至少一个柱形凸块，所述至少一个柱形凸块接合至导电终端并在垂直于半导体晶圆表面的方向上延伸；以及在每一个导电终端上方形成的并围绕位于所述至少一些导电终端上的至少一个柱形凸块的焊料连接件。
在又一实施例中，装置包括凸块下金属化(UBM)层，该UBM层形成在钝化层上方，延伸到开口中且覆盖导电终端，并且该UBM层位于所述至少一些导电终端上的至少一个柱形凸块的下方。在另一实施例中，装置包括处理层，该处理层形成在导电终端上方并位于所述至少一些导电终端上的至少一个柱形凸块的下方。在又一可选实施例中，所述至少一个柱形凸块选自铜和金。在另一实施例中，对于所述至少一些导电终端的至少一个子集，所述至少一个柱形凸块进一步包括在开口中的导电终端上形成的两个或两个以上的柱形凸块。
在又一实施例中，一种方法包括提供具有表面的衬底，在该表面上形成有多个导电终端；在表面上方形成钝化层；在钝化层中形成开口，暴露出导电终端；对于多个导电终端中的至少一些导电终端，形成接合至导电终端并从导电终端开始在垂直于衬底表面的方向上延伸的至少一个柱形凸块；以及在导电终端上方形成焊料连接件，该焊料连接件围绕多个导电终端中的所述至少一些导电终端中的每个导电终端上的至少一个柱形凸块。
在另一实施例中，实施该方法，其中，提供衬底包括提供其上制造集成电路的半导体晶圆。在另一实施例中，实施上述方法，其中，形成至少一个柱形凸块进一步包括形成柱形凸块的堆叠件。在又一实施例中，上述方法进一步包括，其中，在形成接合至多个导电终端中的至少一些导电终端的至少一个柱形凸块之后，所述多个导电终端中的其余导电终端不具有柱形凸块。在又一可选实施例中，实施上述方法，其中形成至少一个柱形凸块包括形成两个或两个以上的柱形凸块。
尽管已经详细描述了示例性实施例及其优点，但应该理解，在不背离由所附权利要求限定的本发明的精神和范围的前提下可以在其中进行各种改变、替换和修改。例如，可以实施替代性的材料、注入剂量和温度。
而且，本申请的范围并不仅限于说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明的公开内容将很容易理解，根据本发明可以利用现有的或今后开发的用于执行与本文所述相应实施例基本相同的功能或者获得基本相同的结果的工艺、机器、制造、材料组分、装置、方法或步骤。因此，所附权利要求预期在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。

Claims (10)

1.一种装置，包括：
衬底，在表面上具有导电终端；
钝化层，上覆所述衬底的表面和所述导电终端；
开口，位于所述钝化层中，所述开口暴露出所述导电终端的一部分；
至少一个柱形凸块，接合至所述开口中的导电终端并在垂直于所述衬底的表面的方向上延伸；以及
焊料连接件，形成在所述开口中的导电终端上并包围所述至少一个柱形凸块。
2.根据权利要求1所述的装置，其中，所述至少一个柱形凸块包含选自基本上由铜和金所组成的组中的一种材料。
3.根据权利要求1所述的装置，其中，所述导电终端进一步包括上覆所述钝化层中的开口并位于所述至少一个柱形凸块下方的凸块下金属化层。
4.根据权利要求1所述的装置，其中，所述导电终端进一步包括上覆所述导电终端并位于所述至少一个柱形凸块下方的处理层。
5.根据权利要求1所述的装置，其中，所述至少一个柱形凸块进一步包括至少两个柱形凸块。
6.根据权利要求1所述的装置，其中，所述焊料连接件包括焊球。
7.根据权利要求1所述的装置，其中，所述衬底包括半导体晶圆。
8.一种装置，包括：
半导体衬底，在所述半导体衬底中形成有多个集成电路；
多个导电终端，形成在所述半导体衬底的表面上并连接到所述半导体衬底内的电路；
至少一个钝化层，形成在所述半导体衬底的表面上方；
开口，设置在所述钝化层中，所述开口暴露出所述多个导电终端的上表面的一部分；
至少一个柱形凸块，形成在所述开口中的至少一些导电终端上，所述至少一个柱形凸块接合至所述导电终端并在垂直于所述半导体衬底的表面的方向上延伸；以及
焊料连接件，形成在每一个导电终端上方并围绕位于所述至少一些导电终端上的至少一个柱形凸块。
9.根据权利要求8所述的装置，进一步包括：
处理层，形成在所述导电终端上方并位于所述至少一些导电终端上的至少一个柱形凸块的下方。
10.一种方法，包括：
提供具有表面的衬底，在所述表面上形成有多个导电终端；
在所述表面上方形成钝化层；
在所述钝化层中形成开口，暴露出所述导电终端；
对于所述多个导电终端中的至少一些导电终端，形成接合至所述导电终端并从所述导电终端开始在垂直于所述衬底的表面的方向上延伸的至少一个柱形凸块；以及
在所述导电终端上方形成焊料连接件，所述焊料连接件围绕所述多个导电终端中的所述至少一些导电终端中的每一个导电终端上的至少一个柱形凸块。
CN201210461253.XA 2012-04-20 2012-11-15 用于焊料连接的方法和装置 Active CN103378037B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/452,507 2012-04-20
US13/452,507 US9515036B2 (en) 2012-04-20 2012-04-20 Methods and apparatus for solder connections

Publications (2)

Publication Number Publication Date
CN103378037A true CN103378037A (zh) 2013-10-30
CN103378037B CN103378037B (zh) 2016-07-06

Family

ID=49290110

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210461253.XA Active CN103378037B (zh) 2012-04-20 2012-11-15 用于焊料连接的方法和装置

Country Status (5)

Country Link
US (2) US9515036B2 (zh)
KR (1) KR101430830B1 (zh)
CN (1) CN103378037B (zh)
DE (1) DE102012107760B4 (zh)
TW (2) TWI565014B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117374041A (zh) * 2023-12-08 2024-01-09 英诺赛科(苏州)半导体有限公司 封装基板和制备方法、封装组件、微电子组件及电子设备

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI449141B (zh) * 2011-10-19 2014-08-11 Richtek Technology Corp 晶圓級晶片尺度封裝元件以及其製造方法
US9230932B2 (en) 2012-02-09 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect crack arrestor structure and methods
US9165875B2 (en) * 2012-04-25 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Low profile interposer with stud structure
US9768137B2 (en) * 2012-04-30 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Stud bump structure for semiconductor package assemblies
US9368461B2 (en) * 2014-05-16 2016-06-14 Intel Corporation Contact pads for integrated circuit packages
US9543259B2 (en) * 2014-10-01 2017-01-10 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure with oval shaped conductor
US9786631B2 (en) 2014-11-26 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Device package with reduced thickness and method for forming same
US20160343646A1 (en) * 2015-05-21 2016-11-24 Qualcomm Incorporated High aspect ratio interconnect for wafer level package (wlp) and integrated circuit (ic) package
US20170063005A1 (en) * 2015-08-27 2017-03-02 Tyco Electronics Corporation Array connector and method of manufacturing the same
US9627299B1 (en) * 2016-02-11 2017-04-18 Texas Instruments Incorporated Structure and method for diminishing delamination of packaged semiconductor devices
KR102462505B1 (ko) 2016-04-22 2022-11-02 삼성전자주식회사 인쇄회로기판 및 반도체 패키지
US9984987B2 (en) * 2016-08-05 2018-05-29 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
US11646286B2 (en) * 2019-12-18 2023-05-09 Micron Technology, Inc. Processes for forming self-healing solder joints and repair of same, related solder joints, and microelectronic components, assemblies and electronic systems incorporating such solder joints
US11211320B2 (en) 2019-12-31 2021-12-28 Texas Instruments Incorporated Package with shifted lead neck
US11302537B2 (en) 2020-04-01 2022-04-12 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with conductive adhesive layer and method for forming the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050090089A1 (en) * 2003-10-22 2005-04-28 Keum-Hee Ma Method for forming solder bump structure
US20070045840A1 (en) * 2005-09-01 2007-03-01 Delphi Technologies, Inc. Method of solder bumping a circuit component and circuit component formed thereby
CN101320696A (zh) * 2007-06-04 2008-12-10 矽品精密工业股份有限公司 堆叠式封装结构及其制法

Family Cites Families (120)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4811082A (en) 1986-11-12 1989-03-07 International Business Machines Corporation High performance integrated circuit packaging structure
US5075253A (en) 1989-04-12 1991-12-24 Advanced Micro Devices, Inc. Method of coplanar integration of semiconductor IC devices
US4990462A (en) 1989-04-12 1991-02-05 Advanced Micro Devices, Inc. Method for coplanar integration of semiconductor ic devices
KR940001149B1 (ko) 1991-04-16 1994-02-14 삼성전자 주식회사 반도체 장치의 칩 본딩 방법
US5380681A (en) 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
US5466635A (en) 1994-06-02 1995-11-14 Lsi Logic Corporation Process for making an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating
JPH0997791A (ja) 1995-09-27 1997-04-08 Internatl Business Mach Corp <Ibm> バンプ構造、バンプの形成方法、実装接続体
US6002177A (en) 1995-12-27 1999-12-14 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
US5736456A (en) 1996-03-07 1998-04-07 Micron Technology, Inc. Method of forming conductive bumps on die for flip chip applications
US5759910A (en) 1996-12-23 1998-06-02 Motorola, Inc. Process for fabricating a solder bump for a flip chip integrated circuit
US5962921A (en) 1997-03-31 1999-10-05 Micron Technology, Inc. Interconnect having recessed contact members with penetrating blades for testing semiconductor dice and packages with contact bumps
US6175161B1 (en) 1998-05-22 2001-01-16 Alpine Microsystems, Inc. System and method for packaging integrated circuits
US6107180A (en) 1998-01-30 2000-08-22 Motorola, Inc. Method for forming interconnect bumps on a semiconductor die
KR100352865B1 (ko) * 1998-04-07 2002-09-16 신꼬오덴기 고교 가부시키가이샤 반도체 장치 및 그 제조방법
JPH11297873A (ja) 1998-04-13 1999-10-29 Seiko Epson Corp 半導体装置およびその製造方法
US6213376B1 (en) 1998-06-17 2001-04-10 International Business Machines Corp. Stacked chip process carrier
JP3516592B2 (ja) 1998-08-18 2004-04-05 沖電気工業株式会社 半導体装置およびその製造方法
US6281042B1 (en) 1998-08-31 2001-08-28 Micron Technology, Inc. Structure and method for a high performance electronic packaging assembly
JP2000091371A (ja) 1998-09-11 2000-03-31 Seiko Epson Corp 半導体装置およびその製造方法
US6271059B1 (en) 1999-01-04 2001-08-07 International Business Machines Corporation Chip interconnection structure using stub terminals
US6461895B1 (en) 1999-01-05 2002-10-08 Intel Corporation Process for making active interposer for high performance packaging applications
US6229216B1 (en) 1999-01-11 2001-05-08 Intel Corporation Silicon interposer and multi-chip-module (MCM) with through substrate vias
TW442873B (en) 1999-01-14 2001-06-23 United Microelectronics Corp Three-dimension stack-type chip structure and its manufacturing method
JP3346320B2 (ja) 1999-02-03 2002-11-18 カシオ計算機株式会社 半導体装置及びその製造方法
US6243272B1 (en) 1999-06-18 2001-06-05 Intel Corporation Method and apparatus for interconnecting multiple devices on a circuit board
JP3239335B2 (ja) 1999-08-18 2001-12-17 インターナショナル・ビジネス・マシーンズ・コーポレーション 電気的接続用構造体の形成方法およびはんだ転写用基板
US6717245B1 (en) 2000-06-02 2004-04-06 Micron Technology, Inc. Chip scale packages performed by wafer level processing
US6355501B1 (en) 2000-09-21 2002-03-12 International Business Machines Corporation Three-dimensional chip stacking assembly
US7129575B1 (en) 2000-10-13 2006-10-31 Bridge Semiconductor Corporation Semiconductor chip assembly with bumped metal pillar
US6562665B1 (en) 2000-10-16 2003-05-13 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology
KR100364635B1 (ko) 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법
JP3767398B2 (ja) 2001-03-19 2006-04-19 カシオ計算機株式会社 半導体装置およびその製造方法
KR100394808B1 (ko) 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
US20030107137A1 (en) 2001-09-24 2003-06-12 Stierman Roger J. Micromechanical device contact terminals free of particle generation
US6762122B2 (en) 2001-09-27 2004-07-13 Unitivie International Limited Methods of forming metallurgy structures for wire and solder bonding
KR100435813B1 (ko) 2001-12-06 2004-06-12 삼성전자주식회사 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법
DE10200399B4 (de) 2002-01-08 2008-03-27 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Erzeugung einer dreidimensional integrierten Halbleitervorrichtung und dreidimensional integrierte Halbleitervorrichtung
US6756294B1 (en) 2002-01-30 2004-06-29 Taiwan Semiconductor Manufacturing Company Method for improving bump reliability for flip chip devices
US6975016B2 (en) 2002-02-06 2005-12-13 Intel Corporation Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof
US6661085B2 (en) 2002-02-06 2003-12-09 Intel Corporation Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
EP1351298B1 (de) 2002-03-28 2007-12-26 Infineon Technologies AG Method for producing a semiconductor wafer
US6803303B1 (en) 2002-07-11 2004-10-12 Micron Technology, Inc. Method of fabricating semiconductor component having encapsulated, bonded, interconnect contacts
US6600222B1 (en) 2002-07-17 2003-07-29 Intel Corporation Stacked microelectronic packages
US6987031B2 (en) 2002-08-27 2006-01-17 Micron Technology, Inc. Multiple chip semiconductor package and method of fabricating same
US7285867B2 (en) 2002-11-08 2007-10-23 Casio Computer Co., Ltd. Wiring structure on semiconductor substrate and method of fabricating the same
US6790748B2 (en) 2002-12-19 2004-09-14 Intel Corporation Thinning techniques for wafer-to-wafer vertical stacks
US6908565B2 (en) 2002-12-24 2005-06-21 Intel Corporation Etch thinning techniques for wafer-to-wafer vertical stacks
KR100553562B1 (ko) 2003-09-23 2006-02-22 삼성전자주식회사 솔더 범프 구조 및 그 제조 방법
US7015590B2 (en) 2003-01-10 2006-03-21 Samsung Electronics Co., Ltd. Reinforced solder bump structure and method for forming a reinforced solder bump
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US6946384B2 (en) 2003-06-06 2005-09-20 Intel Corporation Stacked device underfill and a method of fabrication
US7320928B2 (en) 2003-06-20 2008-01-22 Intel Corporation Method of forming a stacked device filler
US20050026416A1 (en) 2003-07-31 2005-02-03 International Business Machines Corporation Encapsulated pin structure for improved reliability of wafer
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
US7345350B2 (en) 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
JP3757971B2 (ja) 2003-10-15 2006-03-22 カシオ計算機株式会社 半導体装置の製造方法
KR100576156B1 (ko) * 2003-10-22 2006-05-03 삼성전자주식회사 댐이 형성된 반도체 장치 및 그 반도체 장치의 실장 구조
KR100621992B1 (ko) 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
JP3929966B2 (ja) 2003-11-25 2007-06-13 新光電気工業株式会社 半導体装置及びその製造方法
KR100570514B1 (ko) 2004-06-18 2006-04-13 삼성전자주식회사 웨이퍼 레벨 칩 스택 패키지 제조 방법
KR100618837B1 (ko) 2004-06-22 2006-09-01 삼성전자주식회사 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법
US7307005B2 (en) 2004-06-30 2007-12-11 Intel Corporation Wafer bonding with highly compliant plate having filler material enclosed hollow core
US7452803B2 (en) 2004-08-12 2008-11-18 Megica Corporation Method for fabricating chip structure
US7087538B2 (en) 2004-08-16 2006-08-08 Intel Corporation Method to fill the gap between coupled wafers
US20060055032A1 (en) 2004-09-14 2006-03-16 Kuo-Chin Chang Packaging with metal studs formed on solder pads
TWI252546B (en) 2004-11-03 2006-04-01 Advanced Semiconductor Eng Bumping process and structure thereof
JP4843214B2 (ja) 2004-11-16 2011-12-21 株式会社東芝 モジュール基板およびディスク装置
TWI263856B (en) 2004-11-22 2006-10-11 Au Optronics Corp IC chip, IC assembly and flat display
JP2006228837A (ja) 2005-02-15 2006-08-31 Sharp Corp 半導体装置及びその製造方法
JP4526983B2 (ja) 2005-03-15 2010-08-18 新光電気工業株式会社 配線基板の製造方法
US20060211233A1 (en) 2005-03-21 2006-09-21 Skyworks Solutions, Inc. Method for fabricating a wafer level package having through wafer vias for external package connectivity and related structure
JP2006287048A (ja) 2005-04-01 2006-10-19 Rohm Co Ltd 半導体装置
US7317256B2 (en) 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
US7557597B2 (en) 2005-06-03 2009-07-07 International Business Machines Corporation Stacked chip security
US7402515B2 (en) 2005-06-28 2008-07-22 Intel Corporation Method of forming through-silicon vias with stress buffer collars and resulting devices
JP4817892B2 (ja) 2005-06-28 2011-11-16 富士通セミコンダクター株式会社 半導体装置
JP4889974B2 (ja) 2005-08-01 2012-03-07 新光電気工業株式会社 電子部品実装構造体及びその製造方法
TWI273667B (en) 2005-08-30 2007-02-11 Via Tech Inc Chip package and bump connecting structure thereof
US7432592B2 (en) 2005-10-13 2008-10-07 Intel Corporation Integrated micro-channels for 3D through silicon architectures
US7528494B2 (en) 2005-11-03 2009-05-05 International Business Machines Corporation Accessible chip stack and process of manufacturing thereof
US7410884B2 (en) 2005-11-21 2008-08-12 Intel Corporation 3D integrated circuits using thick metal for backside connections and offset bumps
KR100660893B1 (ko) 2005-11-22 2006-12-26 삼성전자주식회사 정렬 마크막을 구비하는 반도체 소자 및 그 제조 방법
JP4458029B2 (ja) 2005-11-30 2010-04-28 カシオ計算機株式会社 半導体装置の製造方法
US7402442B2 (en) 2005-12-21 2008-07-22 International Business Machines Corporation Physically highly secure multi-chip assembly
JP4251458B2 (ja) 2005-12-21 2009-04-08 Ｔｄｋ株式会社 チップ部品の実装方法及び回路基板
US20080185705A1 (en) * 2005-12-23 2008-08-07 Tessera, Inc. Microelectronic packages and methods therefor
US7279795B2 (en) 2005-12-29 2007-10-09 Intel Corporation Stacked die semiconductor package
TWI325619B (en) 2006-09-26 2010-06-01 Powertech Technology Inc Multi-chip package to optimize mold-flow balance
US20080079150A1 (en) * 2006-09-28 2008-04-03 Juergen Simon Die arrangement and method for producing a die arrangement
TW200820406A (en) 2006-10-19 2008-05-01 Novatek Microelectronics Corp Chip structure and wafer structure
JP4922891B2 (ja) 2006-11-08 2012-04-25 株式会社テラミクロス 半導体装置およびその製造方法
US20090197114A1 (en) 2007-01-30 2009-08-06 Da-Yuan Shih Modification of pb-free solder alloy compositions to improve interlayer dielectric delamination in silicon devices and electromigration resistance in solder joints
US7576435B2 (en) 2007-04-27 2009-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Low-cost and ultra-fine integrated circuit packaging technique
US7820543B2 (en) 2007-05-29 2010-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced copper posts for wafer level chip scale packaging
US20090020869A1 (en) 2007-07-17 2009-01-22 Qing Xue Interconnect joint
KR101213175B1 (ko) 2007-08-20 2012-12-18 삼성전자주식회사 로직 칩에 층층이 쌓인 메모리장치들을 구비하는반도체패키지
JP5058714B2 (ja) * 2007-08-21 2012-10-24 スパンション エルエルシー 半導体装置及びその製造方法
US7667335B2 (en) 2007-09-20 2010-02-23 Stats Chippac, Ltd. Semiconductor package with passivation island for reducing stress on solder bumps
US8269345B2 (en) 2007-10-11 2012-09-18 Maxim Integrated Products, Inc. Bump I/O contact for semiconductor device
US8492263B2 (en) 2007-11-16 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Protected solder ball joints in wafer level chip-scale packaging
US20090174069A1 (en) 2008-01-04 2009-07-09 National Semiconductor Corporation I/o pad structure for enhancing solder joint reliability in integrated circuit devices
US20090206480A1 (en) 2008-02-20 2009-08-20 Atmel Corporation Fabricating low cost solder bumps on integrated circuit wafers
MY149251A (en) * 2008-10-23 2013-07-31 Carsem M Sdn Bhd Wafer-level package using stud bump coated with solder
US20120153444A1 (en) * 2009-06-18 2012-06-21 Rohm Co., Ltd Semiconductor device
JP2013030498A (ja) 2009-11-12 2013-02-07 Panasonic Corp 半導体装置
US8299616B2 (en) 2010-01-29 2012-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. T-shaped post for semiconductor devices
KR101176348B1 (ko) 2010-02-05 2012-08-24 앰코 테크놀로지 코리아 주식회사 반도체 장치 및 그 제조 방법
US8803319B2 (en) 2010-02-11 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar structure having a non-planar surface for semiconductor devices
US8318596B2 (en) 2010-02-11 2012-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar structure having a non-planar surface for semiconductor devices
US20110227216A1 (en) 2010-03-16 2011-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Under-Bump Metallization Structure for Semiconductor Devices
US8492891B2 (en) 2010-04-22 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with electrolytic metal sidewall protection
US8456945B2 (en) 2010-04-23 2013-06-04 Advanced Micro Devices, Inc. 10T SRAM for graphics processing
US8288849B2 (en) 2010-05-07 2012-10-16 Texas Instruments Incorporated Method for attaching wide bus memory and serial memory to a processor within a chip scale package footprint
US8241963B2 (en) 2010-07-13 2012-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Recessed pillar structure
JP6081044B2 (ja) 2010-09-16 2017-02-15 富士通株式会社 パッケージ基板ユニットの製造方法
US8669137B2 (en) * 2011-04-01 2014-03-11 International Business Machines Corporation Copper post solder bumps on substrate
US8535983B2 (en) 2011-06-02 2013-09-17 Infineon Technologies Ag Method of manufacturing a semiconductor device
US9230932B2 (en) 2012-02-09 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect crack arrestor structure and methods

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050090089A1 (en) * 2003-10-22 2005-04-28 Keum-Hee Ma Method for forming solder bump structure
US20070045840A1 (en) * 2005-09-01 2007-03-01 Delphi Technologies, Inc. Method of solder bumping a circuit component and circuit component formed thereby
CN101320696A (zh) * 2007-06-04 2008-12-10 矽品精密工业股份有限公司 堆叠式封装结构及其制法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117374041A (zh) * 2023-12-08 2024-01-09 英诺赛科(苏州)半导体有限公司 封装基板和制备方法、封装组件、微电子组件及电子设备

Also Published As

Publication number Publication date
KR101430830B1 (ko) 2014-08-18
TW201705413A (zh) 2017-02-01
US9515036B2 (en) 2016-12-06
US20170084560A1 (en) 2017-03-23
TW201349419A (zh) 2013-12-01
TWI607537B (zh) 2017-12-01
DE102012107760B4 (de) 2020-12-31
CN103378037B (zh) 2016-07-06
TWI565014B (zh) 2017-01-01
US20130277838A1 (en) 2013-10-24
KR20130118719A (ko) 2013-10-30
DE102012107760A1 (de) 2013-10-24
US10453815B2 (en) 2019-10-22

Similar Documents

Publication Publication Date Title
CN103378037B (zh) 用于焊料连接的方法和装置
US10068873B2 (en) Method and apparatus for connecting packages onto printed circuit boards
US10784223B2 (en) Elongated bump structures in package structure
JP6408986B2 (ja) Ｂｖａインタポーザ
TWI483357B (zh) 封裝結構
US9082763B2 (en) Joint structure for substrates and methods of forming
TWI502667B (zh) 半導體元件的接合結構及半導體元件的製造方法
US7868440B2 (en) Packaged microdevices and methods for manufacturing packaged microdevices
US7148086B2 (en) Semiconductor package with controlled solder bump wetting and fabrication method therefor
TWI509762B (zh) 積體電路封裝及其製造方法
US20090289360A1 (en) Workpiece contact pads with elevated ring for restricting horizontal movement of terminals of ic during pressing
US10770446B2 (en) Semiconductor packages and methods of manufacturing the same
TW201403726A (zh) 金屬柱導線直連元件、金屬柱導線直連封裝結構、金屬柱導線直連元件的製作方法
US6400034B1 (en) Semiconductor device
KR100961309B1 (ko) 반도체 패키지
KR100961310B1 (ko) 반도체 패키지
KR101037827B1 (ko) 반도체 패키지
KR100961311B1 (ko) 반도체 패키지
US20070085220A1 (en) Re-enforced ball-grid array packages for semiconductor products
KR20100000328A (ko) 조인트 신뢰성이 향상된 반도체 패키지 및 그 제조방법
KR100961308B1 (ko) 반도체 패키지
TWI483360B (zh) 封裝基板及其製法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant