TWI607537B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

Info

Publication number
TWI607537B
TWI607537B TW105134513A TW105134513A TWI607537B TW I607537 B TWI607537 B TW I607537B TW 105134513 A TW105134513 A TW 105134513A TW 105134513 A TW105134513 A TW 105134513A TW I607537 B TWI607537 B TW I607537B
Authority
TW
Taiwan
Prior art keywords
bump
plug
conductor structure
substrate
bumps
Prior art date
Application number
TW105134513A
Other languages
English (en)
Other versions
TW201705413A (zh
Inventor
余振華
蔡豪益
李建勳
劉重希
陳憲偉
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201705413A publication Critical patent/TW201705413A/zh
Application granted granted Critical
Publication of TWI607537B publication Critical patent/TWI607537B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02123Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area
    • H01L2224/02125Reinforcing structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165Reinforcing structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0233Structure of the redistribution layers
    • H01L2224/02335Free-standing redistribution layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0239Material of the redistribution layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/024Material of the insulating layers therebetween
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/034Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346Plating
    • H01L2224/03464Electroless plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/039Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0391Forming a passivation layer after forming the bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05005Structure
    • H01L2224/05008Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05024Disposition the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05026Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05171Chromium [Cr] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05562On the entire exposed surface of the internal layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05567Disposition the external layer being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05569Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05664Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05669Platinum [Pt] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132Screen printing, i.e. using a stencil
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/11848Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849Reflowing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13022Disposition the bump connector being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13026Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/13076Plural core members being mutually engaged together, e.g. through inserts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/13078Plural core members being disposed next to each other, e.g. side-to-side arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked
    • H01L2224/13082Two-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401Structure
    • H01L2224/1403Bump connectors having different sizes, e.g. different diameters, heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1405Shape
    • H01L2224/14051Bump connectors having different shapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1412Layout
    • H01L2224/1413Square or rectangular array
    • H01L2224/14131Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3512Cracking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Description

半導體裝置
本發明主要是關於一種半導體裝置,特別是關於一種用於軟銲接合的裝置。
近年來在封裝製程與積體電路(integrated circuit;IC)製程的發展,造成固定於中介層(interposer)或基板上的封裝形式的使用的增加,使用這種封裝形式而形成固定於印刷電路板(printed circuit boards;PCB)上的模組,進而完成系統的組裝。隨著愈來愈多的先進積體電路用於目前較小且較密集的裝置例如可攜式裝置,對於更小、更薄及更低成本的技術來將積體電路裝置連接於印刷電路板的需求,正持續增加。
使用軟銲凸塊與軟銲球來連接裝置的情況亦愈來愈普遍。在一一般的裝置中,可將具有軟銲凸塊的積體電路晶片安裝在一中介層的上表面,此中介層是由一層疊材料、矽、陶瓷、薄膜等形成。然後,此中介層的下表面可具有排列成一圖形的複數個軟銲球,此圖形對應於印刷電路板上的一端子區域或銲墊的圖形。此封裝形式可稱之為「覆晶封裝」(flip chip package),因為積體電路是以「面朝下」或「翻轉」的方式安裝至中介層上。將積體電路安裝於中介層上之後,可將此組裝物安裝於印刷電路板上。堆疊晶片、包含中介層的封裝體堆疊的配置,是已知技術。
中介層的使用,伴隨著其成本及相關的製造步驟,對於整個系統的製造而言,會造成成本的增加與產能的降低。另一個替代的技術是使用晶圓級製程(wafer level processing;WLP)來直接在一半導體晶圓的表面上形成軟銲接合物,其一般為軟銲球。這些步驟可在整個晶圓上一次操作,可達成所需節省的規模並降低成本。另外,此技術可排除昂貴的中介層及其伴隨而來之用以製造此中介層的製造及測試製程的需求。
在晶圓級製程的封裝的使用中,將軟銲球黏附於印刷電路板的表面,並黏附於晶圓或積體電路晶片上的後保護層內連線(post passivation interconnect;PPI)接合物。由於印刷電路板的材料與半導體晶圓的熱膨脹係數不同,在系統運作過程中會有熱應力作用在組裝物上,而會有較大的應力作用於軟銲球。與具有中介層的「覆晶」封裝相比,使用軟銲接合物直接將晶片安裝於印刷電路板會增加作用於軟銲接合物的應力。
在測試中,由於熱循環試驗(thermal cycle test;TCT)中的應力,軟銲接合物會發生如「開路」故障之故障。軟銲球會發生龜裂,特別在靠近後保護層內連線接合物之處。因此,業界需求改良的軟銲接合物。
有鑑於此,本發明的一實施例是提供一種半導體裝置,包含一基板、一鈍化層、一開口、至少一栓狀凸塊(stud bump)以及一軟銲接合物。上述基板是在其一表面具有一導體 端子。上述鈍化層是在上述基板的上述表面上及上述導體端子上。上述開口是在上述鈍化層中,並曝露上述導體端子的一部分。上述至少一栓狀凸塊是連接於上述開口中的上述導體端子,並向垂直於上述基板的上述表面的方向延伸。上述軟銲接合物是形成於上述開口中的上述導體端子上,並包覆上述至少一栓狀凸塊。
在上述之半導體裝置中,上述至少一栓狀凸塊較好為包含一材料,上述材料較好是選自主要包括銅與金的族群中的一種。
在上述之半導體裝置中,較好為:上述導體端子更包含一凸塊下金屬(under bump metallization;UBM)層,上述凸塊下金屬層在上述鈍化層中的上述開口上、並在上述至少一栓狀凸塊下。
在上述之半導體裝置中,較好為:上述導體端子更包含一表面處理層,上述表面處理層在上述凸塊下金屬層上、並在上述至少一栓狀凸塊下。
在上述之半導體裝置中,較好為:上述導體端子更包含一表面處理層,上述表面處理層在上述導體端子上、並在上述至少一栓狀凸塊下。
在上述之半導體裝置中,上述表面處理層較好為包含一材料,上述材料較好是選自主要包括金、鎳、鈀、無電鍍鎳浸金(electroless nickel-immersion gold;ENIG)及無電鍍鎳鈀浸金(electroless nickel-electroless palladium-immersion gold;ENEPIG)的族群中的一種。
在上述之半導體裝置中,較好為:上述至少一栓狀凸塊更包含至少二個栓狀凸塊。
在上述之半導體裝置中,較好為:上述至少一栓狀凸塊更包含至少三個或多於三個栓狀凸塊。
在上述之半導體裝置中,上述軟銲接合物較好為包含一軟銲球。
在上述之半導體裝置中,上述基板較好為包含一半導體晶圓。
本發明的另一實施例是提供一種半導體裝置,包含:一半導體基板、複數個導體端子、至少一鈍化層、在該鈍化層中的複數個開口、至少一栓狀凸塊以及一軟銲接合物。上述半導體基板具有形成於其內的複數個積體電路。上述導體端子是形成於上述半導體基板的一表面上,並連接於上述半導體基板中的電路系統。上述至少一鈍化層是形成於上述半導體基板的上述表面的上方。上述開口是曝露上述導體端子的上表面的一部分。上述至少一栓狀凸塊是形成於上述開口中的至少一些的上述導體端子上,上述至少一栓狀凸塊連接於上述導體端子,並向垂直於上述半導體基板的上述表面的方向延伸。上述軟銲接合物是形成於每個上述導體端子的上方,並圍繞在上述至少一些的上述導體端子上的上述至少一栓狀凸塊。
在上述之半導體裝置中,較好為更包含:一凸塊下金屬層,形成於上述鈍化層的上方,並延伸進入上述開口而覆蓋上述導體端子,且在上述至少一些的上述導體端子上的上述至少一栓狀凸塊之下。
在上述之半導體裝置中,較好為更包含:一表面處理層,形成於該些導體端子的上方,並在上述至少一些的該些導體端子上的上述至少一栓狀凸塊之下。
在上述之半導體裝置中,上述至少一栓狀凸塊較好為各包含一材料,上述材料較好是選自主要包括銅與金的族群中的一種。
在上述之半導體裝置中,較好為:關於上述至少一些的上述導體端子的至少一子集(subset),上述至少一栓狀凸塊更包含形成於上述開口中的上述導體端子上的二個或超過二個栓狀凸塊。
本發明的又另一實施例是提供一種半導體裝置的製造方法,包含下列步驟:提供一基板,在上述基板的一表面具有形成於其上的複數個導體端子;在上述表面的上方形成一鈍化層;在上述鈍化層中形成複數個開口,而曝露上述導體端子;關於上述導體端子的至少一些,形成至少一栓狀凸塊,上述至少一栓狀凸塊連接於上述導體端子,並從上述導體端子以垂直於上述基板的上述表面的方向延伸;以及在上述導體端子的上方形成複數個軟銲接合物,上述軟銲接合物圍繞上述上述導體端子的至少一些的每一個上的上述至少一栓狀凸塊。
在上述之半導體裝置的製造方法中,較好為:提供上述基板的步驟包含提供一半導體基板,該半導體基板具有製造於其上的複數個積體電路。
在上述之半導體裝置的製造方法中,較好為:形成上述至少一栓狀凸塊的步驟更包含形成複數個栓狀凸塊的 一堆疊體。
在上述之半導體裝置的製造方法中,在形成連接於上述導體端子的至少一些導體端子的至少一栓狀凸塊之後,較好使上述導體端子的一些保持不具該至少一栓狀凸塊的狀態。
在上述之半導體裝置的製造方法中,形成上述至少一栓狀凸塊的步驟較好為包含形成二個或多於二個栓狀凸塊。
10‧‧‧實施例
11‧‧‧結構
12‧‧‧實施例
13‧‧‧基板
14‧‧‧實施例
15‧‧‧軟銲接合物
17‧‧‧導體端子
18‧‧‧實施例
19‧‧‧鈍化層
21‧‧‧第一聚合物層
23‧‧‧跡線
25‧‧‧第二聚合物層
27‧‧‧凸塊下金屬層
29‧‧‧栓狀凸塊
31‧‧‧表面處理層
38‧‧‧連接墊
39‧‧‧栓狀凸塊堆疊物
41‧‧‧上封裝體
45‧‧‧區域
49‧‧‧軟銲接合構件
51‧‧‧軟銲接合構件
53‧‧‧軟銲接合構件
61‧‧‧步驟
63‧‧‧步驟
65‧‧‧步驟
67‧‧‧步驟
69‧‧‧步驟
71‧‧‧步驟
73‧‧‧步驟
75‧‧‧步驟
77‧‧‧步驟
79‧‧‧步驟
81‧‧‧步驟
83‧‧‧步驟
85‧‧‧步驟
87‧‧‧步驟
89‧‧‧步驟
91‧‧‧步驟
DNP1‧‧‧到中立點的距離(半徑)
DNP2‧‧‧到中立點的距離(半徑)
第1圖是一剖面圖,顯示用於本發明各實施例之一結構。
第2圖是一剖面圖,顯示本發明一實施例之構造。
第3圖是一剖面圖,顯示在一中間製程步驟之本發明一實施例之構造。
第4圖是一剖面圖,顯示在第3圖的構造施作後續的製程。
第5圖是一剖面圖,顯示在第4圖的構造施作後續的製程。
第6圖是一剖面圖,顯示在第5圖的構造施作後續的製程。
第7圖是一剖面圖,顯示在一中間製程步驟之本發明另一實施例之構造。
第8圖是一剖面圖,顯示在第7圖的構造施作後續的製程。
第9圖是一剖面圖,顯示在第8圖的構造施作後續的製程。
第10圖是一剖面圖,顯示本發明又另一實施例之構造。
第11圖是一俯視圖,顯示本發明一實施例之構造。
第12圖是一平面圖,顯示用於本發明各實施例之一結構。
第13A圖是一剖面圖,顯示用於第12圖之結構的本發明一實施例;第13B圖是一剖面圖,顯示用於第12圖之結構的本發明另一實施例;第13C圖是一剖面圖,顯示用於第12圖之結構的本發明另一實施例。
第14圖是一流程圖,顯示本發明之一方法實施例。
第15圖是一流程圖,顯示本發明之另一方法實施例。
第16圖是一流程圖,顯示本發明之又另一方法實施例。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂,下文特舉出較佳實施例,並配合所附圖式,作詳細說明如下:本說明書所舉實施例是以具體的例子來做示範,並非用以限定說明書的範圍,亦無用以限定申請專利範圍的請求範圍。本發明的實施例包含一方法,其用以形成連接於一電性端子例如一銲墊或一端子區域(land)的一軟銲接合構件。上述軟銲接合構件包含至少一栓狀凸塊與一軟銲接合物,上述至少一栓狀凸塊是從上述電性端子垂直延伸,上述軟銲接合物例如一軟銲球是形成為圍繞並包覆上述栓狀凸塊。因為栓狀凸塊會增加強度且黏著於上述電性端子的表面上的材料的情況優於一實心的軟銲接合物,結果減少了軟銲接合構件因例如熱應力而發生故障的情況。可在一晶圓級製程形成上述栓狀凸塊與軟銲球,然後再分切裝置後,將其安裝在一系統電路板或印刷電路板。上述軟銲接合構件可形成在具有例如銲墊或端子區域的電性端子之一晶圓、一晶片或一基板上。上述軟銲接合構件 可直接形成在一晶圓的銲墊上、或形成在身為一後保護層內連線(post passivation interconnection;PPI)架構中的一重分佈層(redistribution layer;RDL)的一部分之一連接墊上。
第1圖是一剖面圖,顯示一範例結構11,以示範本發明各個實施例的使用。第1圖是一起顯示基板13與置於基板13的一主動表面上的複數個軟銲接合物15,其中基板13可以是一半導體晶圓或其他種類的基板,軟銲接合物15可以是軟銲凸塊或軟銲球。在本說明書中的「軟銲」或「軟銲料」是包含且不限於含鉛及無鉛這二種軟銲料,例如用於含鉛軟銲料的錫-鉛成分,而無鉛軟銲料包含錫、銀、銅或所謂錫-銀-銅(Si-Ag-Cu;SAC)成分與其他共晶成分而具有固定熔點並在導電應用中形成導電性的軟銲接合構件。關於無鉛軟銲料,可使用不同種類成分的錫-銀-銅軟銲料例如SAC 105(錫98.5%、銀1.0%、銅0.5%)、SAC 305、SAC 405等等。無鉛軟銲接合物例如軟銲球也可由錫-銅成分形成而不使用銀(Ag),其亦可由包含錫與銀還有任意的銅的無鉛軟銲接合物所取代。
基板13可以是一半導體基板例如矽、鍺、砷化鎵及其他半導體材料。基板13可以是一中介層(interposer),例如矽、層疊物、陶瓷、薄膜、環氧樹脂玻璃纖維(FR4)或其他電路板材料,本發明個實施例亦可應用於這些基板。在某些實施例中,基板13是矽晶圓,其包含許多積體電路,這些積體電路是在使用本發明個實施例以形成與系統板之連接之前製造。
在第1圖的剖面圖中,顯示單列的軟銲接合物15,此軟銲接合物15一般而言是軟銲球,但亦可使用其他形狀例如 柱狀、骰子狀、方塊狀以及圓柱狀。將一批軟銲球形成在柵格圖形上時,所構成的積體電路封裝體可稱之為「球柵陣列」(ball grid array;BGA),而其軟銲球可稱之為「球柵陣列軟銲球」。然而,敘述於本說明書之本發明各實施例並不限於球柵陣列封裝體或球柵陣列軟銲球。關於軟銲接合物15,本發明各實施例中並未受限於球面或球形者。在一實際應用中,一個積體電路裝置可能會使用數百個甚至數千個軟銲接合物15,而一個半導體晶圓上可能會形成有許多這樣的積體電路裝置。
在一系統的使用中,例如使用熱迴銲的方式將基板13固定於另一個電路板或組裝體例如一系統印刷電路板(未繪示)。接下來,使軟銲接合物15與上述系統印刷電路板上的連接墊或端子區域對準,放置軟銲接合物15,使其與上述連接墊或端子區域成物理性的接觸。上述對準與放置軟銲接合物15的步驟可使用例如機械手臂等的取放(pick and place)與自動對準工具,以自動或手動的方式操作。
然後一熱迴銲製程可使軟銲接合物15熔化與冷卻,以形成軟銲接合物15與上述系統印刷電路板或組裝物的電性與物理性連接。因此,使軟銲接合物15變成物理性且電性於上述系統印刷電路板。在組裝之後,在測試與使用過程中,基板13與軟銲接合物15會曝露在熱應力中。在後續熱循環造成的機械應力中,軟銲接合物15必須承受機械性運動或機械力之應力,例如在熱循環過程中的熱膨脹係數不匹配造成的應力。若軟銲接合物15無法承受上述應力,則可能會發生軟銲料龜裂。若上述軟銲料龜裂的裂痕展開,則會發生電性開路,而在測試 或使用過程中發生裝置故障。
第2圖是一剖面圖,顯示一軟銲接合構件的實施例12。在第2圖中,基板13具有一導體端子17,導體端子17提供對基板13中的電路系統(未繪示)的電性連接。導體端子17可以是例如用於一積體電路的一銲墊,或可以是一多層基板的一跡線(trace)。鈍化層19的形成,例如是來保護基板13中的電路系統。鈍化層19可以是一聚醯亞胺(polyimide)層、一氮化矽層、一聚合物層或其他具保護性的介電材料層。在實施例12中,形成一重分佈層(redistribution layer;RDL),使此重分佈層將導體端子17連接於軟銲接合物15。第2圖顯示一第一聚合物層21,用以為上述重分佈層形成一絕緣層。後保護層內連線的一跡線23是形成於第一聚合物層21的上方,跡線23是例如銅、鋁、金等的導體,其一端延伸而經由一開口而電性且物理性連接於導體端子17。如第2圖所示,顯示另一個介電質或絕緣體,也就是一第二聚合物層25,其是置於跡線23的上方。第二聚合物層25中的一開口曝露出跡線23的一部分,形成一連接墊或端子區域,軟銲接合物15是形成在此開口中。在第二聚合物層25的上方是形成一凸塊下金屬(under bump metallization;UBM)層27,凸塊下金屬層27並延伸至上述開口中,覆蓋跡線23的上表面。凸塊下金屬層材料是用來增加軟銲料的黏著力,並在軟銲料與跡線23的軟銲料接合部分之間的連接提供某種程度的應力鬆弛。用於凸塊下金屬層27的金屬包含但不限於銅、鋁、鎳、鈦與鉻的至少一種。凸塊下金屬層27的關鍵特徵是黏著於上述導體也就是跡線23的材料,而提供一軟銲料擴散障蔽、為 軟銲接合物15的安裝提供可銲性(solderability)與潤濕性(wettability)、相容於形成軟銲接合物15的製程、且對其與跡線23的接點提供較低的電阻。
如第2圖所示,一栓狀凸塊29是形成於凸塊下金屬層27上,並以遠離基板13的水平上表面的垂直方向延伸。此栓狀凸塊29可使用銲線機的銲針工具來形成例如一熱壓銲接(thermo compression bond;TCB)。可使用一球銲與點銲(ball and stitch)操作,將一銲球機械性地連接於凸塊下金屬層27,然後此銲線操作在使銲針工具以向上而遠離凸塊下金屬層27的表面的方向移動時,藉由切斷銲線的垂直部分而形成栓狀凸塊29。此栓狀凸塊29可由銅、金或其他銲線材料形成。如後文的詳細敘述,可為一個軟銲接合物15形成超過一個栓狀凸塊29,而可在一個軟銲接合物15使用二個、三個、四個或是更多栓狀凸塊29。栓狀凸塊29的直徑例如可為50μm-80μm,栓狀凸塊29的高度可為80μm-160μm。栓狀凸塊29具有一較寬的底部與一較窄或點狀的頂部,由於栓狀凸塊29是由上述球銲與點銲操作而形成。栓狀凸塊29的剖面一般可顯示為:具有一狹窄的頂部的柱狀。
然後,將一軟銲接合物15形成於凸塊下金屬層27上,且圍繞並包覆栓狀凸塊29,此軟銲接合物15可以是一軟銲球。上述軟銲球可以下列步驟形成:以模板印刷的方式選擇在凸塊下金屬層27、軟銲球端子區域的位置之第二聚合物層25上放置軟銲料,然後使上述軟銲料經過一軟銲的熱迴銲製程。如第2圖所示,熔融的軟銲料的表面張力造成在栓狀凸塊29的周 圍形成球狀的軟銲球。本實施例的栓狀凸塊29增加了機械應力,並在軟銲接合物15接觸凸塊下金屬層27的關鍵區域避免龜裂的發生。又,即使在軟銲料-凸塊下金屬層27的交界處附近形成一些軟銲料裂縫,栓狀凸塊29提供連接於上述軟銲球的剩餘部分的額外的電性連接,而避免電路的「開路」的形成,因此不會發生電性故障。
第3圖是一剖面圖,顯示在一中間製程步驟的另一個替代性實施例10,以說明另一個方法實施例。在第3圖中,所示的基板13是具有一導體端子17,此導體端子17可以是一積體電路的銲墊或是另一個內連線端子。在第3圖中,顯示一鈍化層19是在基板13與導體端子17上,鈍化層19例如可為一聚醯亞胺層,而其他鈍化材料包含例如氮化矽等的介電質。在第3圖中,顯示一凸塊下金屬層27是在導體端子17上方並與導體端子17接觸,並覆蓋鈍化層19的一部分的上表面,且凸塊下金屬層27的一部分是在鈍化層19的一部分上。請注意在本實施例中,凸塊下金屬層27是直接在導體端子17的上方,也就是在本實施例中未使用重分佈層。
第4圖是一剖面圖,顯示在實施例10施作後續的製程。在第4圖中,基板13與導體端子17、以及鈍化層19與凸塊下金屬層27是如同前述實施例一般排列,故不再詳述。在第4圖中,提供一表面處理層31。此表面處理層31可以是化學鍍(electroless plating)層,例如鎳(Ni)、金(Au)、鎳與金、鈀、鉑或其他用於軟銲接合的其他表面處理。表面處理層31亦可使用組合式的表面處理層,例如無電鍍鎳浸金(electroless nickel -immersion gold;ENIG)及無電鍍鎳鈀浸金(electroless nickel -electroless palladium-immersion gold;ENEPIG)。這些表面處理層的作用在於連接例如銅栓狀凸塊時,增加可銲性。
第5圖是一剖面圖,顯示在第4圖的實施例10施作後續的製程。從第4圖過渡到第5圖,基板13、導體端子17、鈍化層19、凸塊下金屬層27與表面處理層31的排列照舊。然後,在表面處理層31的上方形成栓狀凸塊29。栓狀凸塊29的形成,例如可藉由使用一銲針球銲工具進行一球銲步驟並在上述工具遠離並垂直移動時切斷銲線而形成栓狀部分。栓狀凸塊29是機械性地接合於表面處理層31的表面,並以垂直於基板13的水平上表面的方向延伸。栓狀凸塊29可以是銅、金或用於銲線機台的銲線使用的其他材料。栓狀凸塊29的形成可用熱壓銲接。另外,可使用超音波能量來形成栓狀凸塊29,對表面處理層31的接合性更佳。可在每個接合物中形成多個栓狀凸塊29,亦可僅形成一個栓狀凸塊29,如第5圖的實施例所示。
第6圖是一剖面圖,顯示在第5圖的實施例10施作後續的製程。基板13、導體端子17、鈍化層19、凸塊下金屬層27、表面處理層31與栓狀凸塊29的排列都如同第5圖所示。在第6圖中,形成一軟銲接合物15。在本實施例中,軟銲接合物15是軟銲球,但亦可使用其他形狀。為了形成軟銲接合物15,將軟銲料置於基板13上,其方法可藉由例如經由一模板,將一軟銲膏印刷至基板13上。使用一熱迴銲步驟,對上述軟銲料進行回銲,且由於軟銲料在其熔融狀態的表面張力性質,在其冷卻時則形成球狀而圍繞並將栓狀凸塊29包覆,且位於表面處理 層31的上方,如第6圖所示。在一實施例中,表面處理層31與凸塊下金屬層27的直徑約為200μm-240μm,且形成於表面處理層31上的軟銲球會因此有較大的直徑,例如220μm-280μm。軟銲球之間的間距(pitch)例如可為300μm-400μm。栓狀凸塊29的直徑例如可為50μm-80μm,栓狀凸塊29的高度例如可為80μm-160μm。
由於栓狀凸塊29與表面處理層31的接合良好,且栓狀凸塊29以離開基板13的垂直方向朝向軟銲接合物15的中心延伸,藉由栓狀凸塊29的使用而提供額外的強度。特別是,栓狀凸塊29在軟銲接合物15與表面處理層31表面處理層31之間的材料交界處的鄰近區域,提供更高的強度。此區域是在習知的軟銲球的熱循環試驗中,曾經觀察到發生軟銲球龜裂的區域。即使發生軟銲球龜裂,以銅、金或另外的導體材料形成的栓狀凸塊29,會增加從軟銲接合物15的中心周圍到導體端子17的額外的導電路徑,因此避免了導電連接的「開路」的發生,此「開路」是由軟銲球龜裂造成。
前述的實施例是顯示凸塊下金屬層27與栓狀凸塊29一起使用。第7圖是一剖面圖,顯示一實施例14,其與前述的實施例類似,但在本實施例14中未使用凸塊下金屬層。
在第7圖中,是顯示在一中間製程步驟的實施例14。基板13是具有一導體端子17,此導體端子17可以是例如一積體電路的銲墊或是一後保護層內連線端子,其是電性連接於基板13中的其他電路系統。一表面處理層31是形成於導體端子17上,在一實施例中可使用一化學鍍膜。此表面處理層31例如 可為鎳、金、無電鍍鎳浸金(electroless nickel-immersion gold;ENIG)或無電鍍鎳鈀浸金(electroless nickel-electroless palladium-immersion gold;ENEPIG)。
第8圖是一剖面圖,顯示在第7圖的實施例14施作一些附加的製程。在第8圖中,形成一鈍化層19,此鈍化層19是在基板13與表面處理層31的一部分上,鈍化層19可以是聚醯亞胺、氮化物或其他介電質。鈍化層19中的一開口是用來作為軟銲球端子區域,用來接受一軟銲接合構件。如第8圖所示,一對栓狀凸塊29是形成在上述開口中的表面處理層31上,且在一法線方向(在此特定方位)向上延伸(當然,可將基板13上下翻轉,此時栓狀凸塊29則在圖中向下延伸,第8圖所使用的方位僅用於圖示,而未限定一定要使用此方位)。在本實施例中,未使用在前述各實施例所示的凸塊下金屬材料。另外,在一例示的實施例中,其中栓狀凸塊29是金且導體端子17是銅,則可以一起省略表面處理層31而仍可獲得良好的結果,這是因為金的栓狀凸塊29會與銅的導體端子17形成極佳的機械性接合。
第9圖是一剖面圖,顯示在第8圖的實施例14施作後續附加的製程之完成結構。一軟銲接合物15,通常是一軟銲球但不限於軟銲球,是形成於鈍化層19中的上述開口中的表面處理層31的上方。軟銲接合物15是圍繞這一對栓狀凸塊29並予以包覆。如前所述,栓狀凸塊29提供了附加的強度與附加的導電路徑,而避免「開路」故障的發生。此「開路」故障的原因是軟銲料龜裂,而軟銲料龜裂可能由與材料的熱膨脹係數不匹配相關的機械應力與熱循環試驗引起。
第10圖是一剖面圖,顯示一實施例18,其為一替代性的實施例。在實施例18中,栓狀凸塊是進一步堆疊而形成一栓狀凸塊堆疊物39。堆疊的栓狀凸塊的使用會增加栓狀凸塊的高度,同樣地藉由增加軟銲球中的材料而增加軟銲球的尺寸。另外,堆疊的栓狀凸塊的使用會使栓狀凸塊延伸至軟銲接合物15的更深處,而在上封裝體41上的一連接墊38與基板13之間增加額外的導電路徑。因此,若在基板13的附近產生一裂縫,仍不會中斷電性連接。栓狀凸塊堆疊物39亦可使用具有一探針的銲線銲接工具,且將一個栓狀凸塊堆疊在第一個栓狀凸塊上。本實施例18的栓狀凸塊堆疊物39亦可用於第2圖的實施例中以及第6圖的實施例(包含凸塊下金屬)與第9圖(不包含凸塊下金屬)的實施例。而且,這些替代性實施例的每一個可構成附加的實施例,其可當作後附申請專利範圍的請求範圍內的額外的實施例。
第11圖是一俯視圖,顯示本發明某些實施例的軟銲接合物15。在第11圖中,所顯示的軟銲接合物15的直徑大於例如240μm,所顯示的栓狀凸塊29的數量是4個;在其他例示的實施例中,是分別使用1、2、3個栓狀凸塊29。在某些實施例中,使用3個或更多的栓狀凸塊29會達成極佳的功效,但本發明的實施例並不限於使用某些特定數量的栓狀凸塊29。在一例子中,在軟銲接合物15下方的凸塊下金屬層或表面處理層的直徑D1約為μm,同時栓狀凸塊29的直徑為50μm-80μm,而栓狀凸塊29之延伸進入軟銲接合物15的高度為80μm-160μm。本案實施例並不限於上述尺寸的數值範圍,本案實施例的栓狀凸 塊29亦可包含比上述數值範圍更大或更小的直徑、或是更大或更小的高度。同樣地,軟銲接合物15的尺寸亦可大於或小於前述例示的範圍。
第12圖是一平面圖,顯示一基板43。基板43具有本發明實施例之軟銲接合物15。在一非限制性的範例中,如第12圖所示,軟銲接合物15的陣列是13×13,總共有169個軟銲接合物15。在具有軟銲球接合物的基板的熱循環試驗中,觀測到軟銲球會受到應力的作用。上述軟銲球所受的應力並不平均,在接近中心的「中立點」(neutral point)也就是上述軟銲接合物15的陣列的中心,是觀測到最低的應力。藉由為每個軟銲球繪出到中立點的距離(di stance to the neutral point;DNP)、並觀測熱循環中的應力,確定最大應力是在4個角落,例如第12圖所示的區域45,這些軟銲球是具有最大值的「到中立點的距離」,在第12圖是顯示為從中心的軟銲球起算的半徑,並將其標示為「DNP1」。某些較靠近中立點的軟銲球但仍受到相當大的應力,這些錫球是接近上述陣列的外圍行列,可稱之為其所在的「到中立點的距離」是大於或等於顯示為「DNP2」的距離、但小於「DNP1」。較接近中心且在半徑「DNP2」之內的軟銲球,是受到較小之來自熱效應的應力。
第13A、13B、13C圖是一系列之剖面圖,顯示用於第12圖所示裝置的三個軟銲接合構件49、51與53。在第13A圖中,在剖面圖可看到軟銲接合構件49在軟銲接合物15中具有2個栓狀凸塊29;在一替代性的實施例中,軟銲接合構件49在軟銲接合物15中可具有3、4或更多個栓狀凸塊29。在方法實施例 中,在一陣列或積體電路圖形中,距離中立點最遠也就是到中立點的距離為DNP1之軟銲接合物15,可應用繪示於第13A圖的形態。在第13B圖中,在剖面圖可看到軟銲接合構件51在軟銲接合物15中具有單個栓狀凸塊29。在方法實施例中,到中立點的距離小於距離DNP1、但大於或等於較小的到中立點的距離DNP2的軟銲接合物15,可使其成為配備單個栓狀凸塊29的軟銲接合構件51。在第13C圖中,所繪示的軟銲接合構件53是使用傳統不具栓狀凸塊的軟銲接合物。對於最靠近中立點的軟銲接合物15,其到中立點的距離小於DNP2,可使這些軟銲接合物15內不具栓狀凸塊29,因為在其所在位置觀測到的機械應力是小於位於最大的「到中立點的距離」DNP1的軟銲接合物15之處的應力,亦小於位於次大的「到中立點的距離」DNP2的軟銲接合物15之處的應力。對於上述陣列或裝置,藉由僅在某些而非全部的軟銲接合物內設置栓狀凸塊,仍可發揮本發明各實施例的優點,並降低整個系統的成本並增加產出。
第14圖是一流程圖,顯示本發明之一方法實施例。在步驟61中,提供一基板,此基板具有一導體端子。在步驟63中,一鈍化層是形成於上述基板的上方,且一開口是位於上述鈍化層中,而曝露上述導體端子的一部分。在步驟65中,執行一選用的步驟,形成一凸塊下金屬層。在步驟67中,在上述導體端子的上方提供一表面處理層。在步驟69中,在上述導體端子上形成一或多個栓狀凸塊,上述栓狀凸塊是以法線方向遠離上述基板表面而延伸。在步驟71中,在上述導體端子的上方形成一軟銲接合物。本實施例是對應於例如用以形成第6圖 的實施例的方法。
第15圖是一流程圖,顯示本發明之另一方法實施例。在第15圖中,此方法是始於步驟73,在一基板的上方沉積一導體端子。在步驟75,將一表面處理層沉積於上述導體端子的上方。在步驟77,在上述基板的上方形成一鈍化層,並形成一開口以曝露上述導體端子與上述表面處理層。在步驟79,在上述表面處理層上形成一或多個栓狀凸塊,上述一或多個栓狀凸塊電性連接於上述導體端子。在步驟81,一軟銲接合物是形成於上述栓狀凸塊的上方,並將上述栓狀凸塊包覆。本方法實施例是對應於例如用以形成第9圖的實施例的方法。
第16圖是一流程圖,顯示本發明之又另一方法實施例。在步驟83中,將排列成陣列的複數個導體端子形成於一基板上。在步驟85中,決定每個上述導體端子的「到中立點的距離」,上述中立點是上述陣列的中心。在步驟87中,對於每個具有最大的「到中立點的距離」的導體端子,形成多於2個的複數個栓狀凸塊。
在步驟89中,對於被識別為「到中立點的距離」是小於最大「到中立點的距離」但大於其他較小的「到中立點的距離」之導體端子,對於每個這些導體端子,形成至少一個栓狀凸塊。上述陣列中的其餘的導體端子,則未形成任何栓狀凸塊。
然後在步驟91中,在上述導體端子的上方形成軟銲接合物。請注意某些導體端子無任何栓狀凸塊,「到中立點的距離」大於或等於較小的「到中立點的距離」的導體端子具 有至少一個栓狀凸塊,在最大距離或具有最大「到中立點的距離」的導體端子具有超過2個栓狀凸塊。在其他實施例中,包含以下情況:對具有最大「到中立點的距離」的導體端子使用2個栓狀凸塊、對具有中間值的「到中立點的距離」的導體端子使用至少1個栓狀凸塊、對較接近中立點的導體端子則不使用栓狀凸塊。
前述的栓狀凸塊的數量僅止於舉例,在其他取代的實施例中,可在每個導體端子使用更多或更少的栓狀凸塊。具重要性意義的關係是「到中立點的距離」DNP與栓狀凸塊的數量。隨著「到中立點的距離」變大,可預見會受到較大的應力,對於大於或等於一特定的「到中立點的距離」的軟銲球就會增加栓狀凸塊的使用數量。
在某些應用中,由於軟銲球的排列方式會使最大「到中立點的距離」相對較低。在這樣的情況,可使用一替代的實施例,而僅在預見會承受最大應力的軟銲球使用栓狀凸塊,也就是最外側角落的軟銲球會使用單一的栓狀凸塊。在其他情況中,軟銲球的陣列相當大,其中某些軟銲球會具有非常大的「到中立點的距離」、某些軟銲球會具有中間值的「到中立點的距離」、某些較靠近中立點的軟銲球會具有相對低的「到中立點的距離」。在作為其他替代實施例的此一例子中,具有大於或等於一第一預設臨界值的「到中立點的距離」之軟銲球可在每個軟銲球使用4個或更多栓狀凸塊,具有大於一第二預設臨界值、但小於上述第一預設臨界值的「到中立點的距離」之軟銲球可在每個軟銲球使用例如1或2個栓狀凸塊,具有小於 上述第二預設臨界值及上述第一預設臨界值二者的「到中立點的距離」之軟銲球可在每個軟銲球不使用任何栓狀凸塊。對產品原型(prototype)作熱循環試驗及墜落試驗(drop test)可用來決定在一特定裝置中有多少軟銲球需要使用栓狀凸塊、以及用來確認應為一可靠裝置的預設「到中立點的距離」的臨界值。晶片尺寸、軟銲球尺寸、軟銲球密度以及軟銲球間距均為在上述決定過程中的變因,這些變因會隨著應用領域而改變,且可以有很多選擇方案。
使用本發明各實施例是提供一改良的晶圓級製程,此改良的晶圓級製程是相容於用在系統板上的「覆晶」佈局中的積體電路(其主動表面面朝印刷電路板)的安裝之軟銲接合,而不需要使用中間的中介層。使用本發明各實施例的優點是由於較簡單的佈局,而提供較薄的組裝體且減少所需的構件、降低成本並減少可能的失效機構。置於本發明各實施例的軟銲球接合物內側的栓狀凸塊的使用,減少軟銲球龜裂的失效的發生,並減少或消除在例如軟銲球等的以傳統方法形成之傳統的軟銲接合物看到的電路開路。包含本發明各實施例的軟銲接合物在使用上相當可靠,且不需要一覆晶中介層而直接將積體電路安裝至印刷電路板。另外,還要考慮到晶圓級整合。在此方法中,在晶圓階段一起完成多個積體電路,其中數個積體電路可在單一軟銲料迴銲的步驟中,安裝成一個組裝體而一起安裝在一系統板。在一「封裝體立體堆疊」(package on package;POP)或堆疊晶片佈局中,可在晶圓上表面垂直堆疊數個裝置,然後可使用具有栓狀凸塊之本發明各實施例的軟銲 接合物來將上述堆疊的裝置安裝至一系統板。
本發明的一實施例是提供一種裝置,包含一基板、一鈍化層、一開口、至少一栓狀凸塊(stud bump)以及一軟銲接合物。上述基板是在其一表面具有一導體端子。上述鈍化層是在上述基板的上述表面上及上述導體端子上。上述開口是在上述鈍化層中,並曝露上述導體端子的一部分。上述至少一栓狀凸塊是連接於上述開口中的上述導體端子,並向垂直於上述基板的上述表面的方向延伸。上述軟銲接合物是形成於上述開口中的上述導體端子上,並包覆上述至少一栓狀凸塊。
本發明的另一實施例是提供一種裝置,包含:一半導體基板、複數個導體端子、至少一鈍化層、在該鈍化層中的複數個開口、至少一栓狀凸塊以及一軟銲接合物。上述半導體基板具有形成於其內的複數個積體電路。上述導體端子是形成於上述半導體基板的一表面上,並連接於上述半導體基板中的電路系統。上述至少一鈍化層是形成於上述半導體基板的上述表面的上方。上述開口是曝露上述導體端子的上表面的一部分。上述至少一栓狀凸塊是形成於上述開口中的至少一些的上述導體端子上,上述至少一栓狀凸塊連接於上述導體端子,並向垂直於上述半導體基板的上述表面的方向延伸。上述軟銲接合物是形成於每個上述導體端子的上方,並圍繞在上述至少一些的上述導體端子上的上述至少一栓狀凸塊。
本發明的又另一實施例是提供一種裝置的製造方法,包含下列步驟:提供一基板,在上述基板的一表面具有形成於其上的複數個導體端子;在上述表面的上方形成一鈍化 層;在上述鈍化層中形成複數個開口,而曝露上述導體端子;關於上述導體端子的至少一些,形成至少一栓狀凸塊,上述至少一栓狀凸塊連接於上述導體端子,並從上述導體端子以垂直於上述基板的上述表面的方向延伸;以及在上述導體端子的上方形成複數個軟銲接合物,上述軟銲接合物圍繞上述上述導體端子的至少一些的每一個上的上述至少一栓狀凸塊。
雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
12‧‧‧實施例
13‧‧‧基板
15‧‧‧軟銲接合物
17‧‧‧導體端子
19‧‧‧鈍化層
21‧‧‧第一聚合物層
23‧‧‧跡線
25‧‧‧第二聚合物層
27‧‧‧凸塊下金屬層
29‧‧‧栓狀凸塊

Claims (10)

  1. 一種半導體裝置,包含:一基板,具有電路系統;一第一導體結構於該基板上,並電性連接於該電路系統;一第二導體結構於該基板上;一第一數量的第一栓狀凸塊,於該第一導體結構上,該第一數量為一或複數個;一電性連接物,形成於該第一導體結構的上方,並圍繞上述第一栓狀凸塊;一第二數量的第二栓狀凸塊,於該第二導體結構上,該第二數量大於該第一數量;以及一第三導體結構於該基板上,該第三導體結構無任何栓狀凸塊。
  2. 如申請專利範圍第1項所述之半導體裝置,其中以平面圖觀之,該第三導體結構比該第一導體結構及該第二導體結構還接近該基板的中心。
  3. 如申請專利範圍第1或2項所述之半導體裝置,其中以平面圖觀之,該第二導體結構比該第一導體結構還遠離該基板的中心。
  4. 如申請專利範圍第1或2項所述之半導體裝置,其中該第一導體結構、該第二導體結構及該第三導體結構各自更包含一凸塊下金屬(under bump metallization;UBM)層,其中一鈍化層位於各個該第一導體結構、該第二導體結構及該第三導體結構的一部分與該凸塊下金屬層之間。
  5. 如申請專利範圍第4項所述之半導體裝置,其中在該第一導體結構的該凸塊下金屬層與上述第一栓狀凸塊之間、在該第二導體結構的該凸塊下金屬層與上述第二栓狀凸塊之間、在該第三導體結構的該凸塊下金屬層上,各包含一表面處理層。
  6. 如申請專利範圍第1或2項所述之半導體裝置,其中上述第一栓狀凸塊與上述第二栓狀凸塊各包含一材料,該材料選自主要包括銅與金的族群中的一種。
  7. 如申請專利範圍第1或2項所述之半導體裝置,其中上述第一栓狀凸塊與上述第二栓狀凸塊各自具有較寬的底部與較窄或點狀的頂部。
  8. 如申請專利範圍第4項所述之半導體裝置,其中該凸塊下金屬層的材料是選自主要包括金、鎳、鈀、無電鍍鎳浸金(electroless nickel-immersion gold;ENIG)及無電鍍鎳鈀浸金(electroless nickel-electroless palladium-immersion gold;ENEPIG)的族群中的一種。
  9. 如申請專利範圍第5項所述之半導體裝置,其中該表面處理層的材料是選自鎳、金、鈀、鉑所組成之族群的至少一種。
  10. 如申請專利範圍第1或2項所述之半導體裝置,其中該電性連接物是軟銲凸塊或軟銲球。
TW105134513A 2012-04-20 2013-04-19 半導體裝置 TWI607537B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/452,507 US9515036B2 (en) 2012-04-20 2012-04-20 Methods and apparatus for solder connections

Publications (2)

Publication Number Publication Date
TW201705413A TW201705413A (zh) 2017-02-01
TWI607537B true TWI607537B (zh) 2017-12-01

Family

ID=49290110

Family Applications (2)

Application Number Title Priority Date Filing Date
TW102113899A TWI565014B (zh) 2012-04-20 2013-04-19 半導體裝置及其製造方法
TW105134513A TWI607537B (zh) 2012-04-20 2013-04-19 半導體裝置

Family Applications Before (1)

Application Number Title Priority Date Filing Date
TW102113899A TWI565014B (zh) 2012-04-20 2013-04-19 半導體裝置及其製造方法

Country Status (5)

Country Link
US (2) US9515036B2 (zh)
KR (1) KR101430830B1 (zh)
CN (1) CN103378037B (zh)
DE (1) DE102012107760B4 (zh)
TW (2) TWI565014B (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI449141B (zh) * 2011-10-19 2014-08-11 Richtek Technology Corp 晶圓級晶片尺度封裝元件以及其製造方法
US9230932B2 (en) 2012-02-09 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect crack arrestor structure and methods
US9165875B2 (en) * 2012-04-25 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Low profile interposer with stud structure
US9768137B2 (en) 2012-04-30 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Stud bump structure for semiconductor package assemblies
US9368461B2 (en) * 2014-05-16 2016-06-14 Intel Corporation Contact pads for integrated circuit packages
US9543259B2 (en) * 2014-10-01 2017-01-10 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure with oval shaped conductor
US9786631B2 (en) 2014-11-26 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Device package with reduced thickness and method for forming same
US20160343646A1 (en) * 2015-05-21 2016-11-24 Qualcomm Incorporated High aspect ratio interconnect for wafer level package (wlp) and integrated circuit (ic) package
US20170063005A1 (en) * 2015-08-27 2017-03-02 Tyco Electronics Corporation Array connector and method of manufacturing the same
US9627299B1 (en) * 2016-02-11 2017-04-18 Texas Instruments Incorporated Structure and method for diminishing delamination of packaged semiconductor devices
KR102462505B1 (ko) 2016-04-22 2022-11-02 삼성전자주식회사 인쇄회로기판 및 반도체 패키지
US9984987B2 (en) * 2016-08-05 2018-05-29 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
US11646286B2 (en) * 2019-12-18 2023-05-09 Micron Technology, Inc. Processes for forming self-healing solder joints and repair of same, related solder joints, and microelectronic components, assemblies and electronic systems incorporating such solder joints
US11211320B2 (en) 2019-12-31 2021-12-28 Texas Instruments Incorporated Package with shifted lead neck
US11302537B2 (en) 2020-04-01 2022-04-12 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with conductive adhesive layer and method for forming the same
CN117374041A (zh) * 2023-12-08 2024-01-09 英诺赛科(苏州)半导体有限公司 封装基板和制备方法、封装组件、微电子组件及电子设备

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6081038A (en) * 1998-04-07 2000-06-27 Shinko Electric Industries Co., Ltd. Semiconductor chip package structure
US20090212423A1 (en) * 2007-08-21 2009-08-27 Junji Tanaka Stacked solder balls for integrated circuit device packaging and assembly
US20100102444A1 (en) * 2008-10-23 2010-04-29 Carsem (M) Sdn. Bhd. Wafer level package using stud bump coated with solder

Family Cites Families (120)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4811082A (en) 1986-11-12 1989-03-07 International Business Machines Corporation High performance integrated circuit packaging structure
US5075253A (en) 1989-04-12 1991-12-24 Advanced Micro Devices, Inc. Method of coplanar integration of semiconductor IC devices
US4990462A (en) 1989-04-12 1991-02-05 Advanced Micro Devices, Inc. Method for coplanar integration of semiconductor ic devices
KR940001149B1 (ko) 1991-04-16 1994-02-14 삼성전자 주식회사 반도체 장치의 칩 본딩 방법
US5380681A (en) 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
US5466635A (en) 1994-06-02 1995-11-14 Lsi Logic Corporation Process for making an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating
JPH0997791A (ja) 1995-09-27 1997-04-08 Internatl Business Mach Corp <Ibm> バンプ構造、バンプの形成方法、実装接続体
US6002177A (en) 1995-12-27 1999-12-14 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
US5736456A (en) 1996-03-07 1998-04-07 Micron Technology, Inc. Method of forming conductive bumps on die for flip chip applications
US5759910A (en) 1996-12-23 1998-06-02 Motorola, Inc. Process for fabricating a solder bump for a flip chip integrated circuit
US5962921A (en) 1997-03-31 1999-10-05 Micron Technology, Inc. Interconnect having recessed contact members with penetrating blades for testing semiconductor dice and packages with contact bumps
US6175161B1 (en) 1998-05-22 2001-01-16 Alpine Microsystems, Inc. System and method for packaging integrated circuits
US6107180A (en) 1998-01-30 2000-08-22 Motorola, Inc. Method for forming interconnect bumps on a semiconductor die
JPH11297873A (ja) 1998-04-13 1999-10-29 Seiko Epson Corp 半導体装置およびその製造方法
US6213376B1 (en) 1998-06-17 2001-04-10 International Business Machines Corp. Stacked chip process carrier
JP3516592B2 (ja) 1998-08-18 2004-04-05 沖電気工業株式会社 半導体装置およびその製造方法
US6281042B1 (en) 1998-08-31 2001-08-28 Micron Technology, Inc. Structure and method for a high performance electronic packaging assembly
JP2000091371A (ja) 1998-09-11 2000-03-31 Seiko Epson Corp 半導体装置およびその製造方法
US6271059B1 (en) 1999-01-04 2001-08-07 International Business Machines Corporation Chip interconnection structure using stub terminals
US6461895B1 (en) 1999-01-05 2002-10-08 Intel Corporation Process for making active interposer for high performance packaging applications
US6229216B1 (en) 1999-01-11 2001-05-08 Intel Corporation Silicon interposer and multi-chip-module (MCM) with through substrate vias
TW442873B (en) 1999-01-14 2001-06-23 United Microelectronics Corp Three-dimension stack-type chip structure and its manufacturing method
JP3346320B2 (ja) 1999-02-03 2002-11-18 カシオ計算機株式会社 半導体装置及びその製造方法
US6243272B1 (en) 1999-06-18 2001-06-05 Intel Corporation Method and apparatus for interconnecting multiple devices on a circuit board
JP3239335B2 (ja) 1999-08-18 2001-12-17 インターナショナル・ビジネス・マシーンズ・コーポレーション 電気的接続用構造体の形成方法およびはんだ転写用基板
US6717245B1 (en) 2000-06-02 2004-04-06 Micron Technology, Inc. Chip scale packages performed by wafer level processing
US6355501B1 (en) 2000-09-21 2002-03-12 International Business Machines Corporation Three-dimensional chip stacking assembly
US7129575B1 (en) 2000-10-13 2006-10-31 Bridge Semiconductor Corporation Semiconductor chip assembly with bumped metal pillar
US6562665B1 (en) 2000-10-16 2003-05-13 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology
KR100364635B1 (ko) 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법
JP3767398B2 (ja) 2001-03-19 2006-04-19 カシオ計算機株式会社 半導体装置およびその製造方法
KR100394808B1 (ko) 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
US20030107137A1 (en) 2001-09-24 2003-06-12 Stierman Roger J. Micromechanical device contact terminals free of particle generation
US6762122B2 (en) 2001-09-27 2004-07-13 Unitivie International Limited Methods of forming metallurgy structures for wire and solder bonding
KR100435813B1 (ko) 2001-12-06 2004-06-12 삼성전자주식회사 금속 바를 이용하는 멀티 칩 패키지와 그 제조 방법
DE10200399B4 (de) 2002-01-08 2008-03-27 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Erzeugung einer dreidimensional integrierten Halbleitervorrichtung und dreidimensional integrierte Halbleitervorrichtung
US6756294B1 (en) 2002-01-30 2004-06-29 Taiwan Semiconductor Manufacturing Company Method for improving bump reliability for flip chip devices
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6975016B2 (en) 2002-02-06 2005-12-13 Intel Corporation Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof
US6661085B2 (en) 2002-02-06 2003-12-09 Intel Corporation Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
EP1351298B1 (de) 2002-03-28 2007-12-26 Infineon Technologies AG Method for producing a semiconductor wafer
US6803303B1 (en) 2002-07-11 2004-10-12 Micron Technology, Inc. Method of fabricating semiconductor component having encapsulated, bonded, interconnect contacts
US6600222B1 (en) 2002-07-17 2003-07-29 Intel Corporation Stacked microelectronic packages
US6987031B2 (en) 2002-08-27 2006-01-17 Micron Technology, Inc. Multiple chip semiconductor package and method of fabricating same
US7285867B2 (en) 2002-11-08 2007-10-23 Casio Computer Co., Ltd. Wiring structure on semiconductor substrate and method of fabricating the same
US6790748B2 (en) 2002-12-19 2004-09-14 Intel Corporation Thinning techniques for wafer-to-wafer vertical stacks
US6908565B2 (en) 2002-12-24 2005-06-21 Intel Corporation Etch thinning techniques for wafer-to-wafer vertical stacks
US7015590B2 (en) 2003-01-10 2006-03-21 Samsung Electronics Co., Ltd. Reinforced solder bump structure and method for forming a reinforced solder bump
KR100553562B1 (ko) 2003-09-23 2006-02-22 삼성전자주식회사 솔더 범프 구조 및 그 제조 방법
US6924551B2 (en) 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US6946384B2 (en) 2003-06-06 2005-09-20 Intel Corporation Stacked device underfill and a method of fabrication
US7320928B2 (en) 2003-06-20 2008-01-22 Intel Corporation Method of forming a stacked device filler
US20050026416A1 (en) 2003-07-31 2005-02-03 International Business Machines Corporation Encapsulated pin structure for improved reliability of wafer
KR100537892B1 (ko) 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
US7345350B2 (en) 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
JP3757971B2 (ja) 2003-10-15 2006-03-22 カシオ計算機株式会社 半導体装置の製造方法
KR100541396B1 (ko) * 2003-10-22 2006-01-11 삼성전자주식회사 3차원 ubm을 포함하는 솔더 범프 구조의 형성 방법
KR100576156B1 (ko) * 2003-10-22 2006-05-03 삼성전자주식회사 댐이 형성된 반도체 장치 및 그 반도체 장치의 실장 구조
KR100621992B1 (ko) 2003-11-19 2006-09-13 삼성전자주식회사 이종 소자들의 웨이퍼 레벨 적층 구조와 방법 및 이를이용한 시스템-인-패키지
JP3929966B2 (ja) 2003-11-25 2007-06-13 新光電気工業株式会社 半導体装置及びその製造方法
KR100570514B1 (ko) 2004-06-18 2006-04-13 삼성전자주식회사 웨이퍼 레벨 칩 스택 패키지 제조 방법
KR100618837B1 (ko) 2004-06-22 2006-09-01 삼성전자주식회사 웨이퍼 레벨 패키지를 위한 얇은 웨이퍼들의 스택을형성하는 방법
US7307005B2 (en) 2004-06-30 2007-12-11 Intel Corporation Wafer bonding with highly compliant plate having filler material enclosed hollow core
US7452803B2 (en) 2004-08-12 2008-11-18 Megica Corporation Method for fabricating chip structure
US7087538B2 (en) 2004-08-16 2006-08-08 Intel Corporation Method to fill the gap between coupled wafers
US20060055032A1 (en) 2004-09-14 2006-03-16 Kuo-Chin Chang Packaging with metal studs formed on solder pads
TWI252546B (en) 2004-11-03 2006-04-01 Advanced Semiconductor Eng Bumping process and structure thereof
JP4843214B2 (ja) 2004-11-16 2011-12-21 株式会社東芝 モジュール基板およびディスク装置
TWI263856B (en) 2004-11-22 2006-10-11 Au Optronics Corp IC chip, IC assembly and flat display
JP2006228837A (ja) 2005-02-15 2006-08-31 Sharp Corp 半導体装置及びその製造方法
JP4526983B2 (ja) 2005-03-15 2010-08-18 新光電気工業株式会社 配線基板の製造方法
US20060211233A1 (en) 2005-03-21 2006-09-21 Skyworks Solutions, Inc. Method for fabricating a wafer level package having through wafer vias for external package connectivity and related structure
JP2006287048A (ja) 2005-04-01 2006-10-19 Rohm Co Ltd 半導体装置
US7317256B2 (en) 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
US7557597B2 (en) 2005-06-03 2009-07-07 International Business Machines Corporation Stacked chip security
US7402515B2 (en) 2005-06-28 2008-07-22 Intel Corporation Method of forming through-silicon vias with stress buffer collars and resulting devices
JP4817892B2 (ja) 2005-06-28 2011-11-16 富士通セミコンダクター株式会社 半導体装置
JP4889974B2 (ja) 2005-08-01 2012-03-07 新光電気工業株式会社 電子部品実装構造体及びその製造方法
TWI273667B (en) 2005-08-30 2007-02-11 Via Tech Inc Chip package and bump connecting structure thereof
US20070045840A1 (en) 2005-09-01 2007-03-01 Delphi Technologies, Inc. Method of solder bumping a circuit component and circuit component formed thereby
US7432592B2 (en) 2005-10-13 2008-10-07 Intel Corporation Integrated micro-channels for 3D through silicon architectures
US7528494B2 (en) 2005-11-03 2009-05-05 International Business Machines Corporation Accessible chip stack and process of manufacturing thereof
US7410884B2 (en) 2005-11-21 2008-08-12 Intel Corporation 3D integrated circuits using thick metal for backside connections and offset bumps
KR100660893B1 (ko) 2005-11-22 2006-12-26 삼성전자주식회사 정렬 마크막을 구비하는 반도체 소자 및 그 제조 방법
JP4458029B2 (ja) 2005-11-30 2010-04-28 カシオ計算機株式会社 半導体装置の製造方法
JP4251458B2 (ja) 2005-12-21 2009-04-08 Tdk株式会社 チップ部品の実装方法及び回路基板
US7402442B2 (en) 2005-12-21 2008-07-22 International Business Machines Corporation Physically highly secure multi-chip assembly
US20080185705A1 (en) * 2005-12-23 2008-08-07 Tessera, Inc. Microelectronic packages and methods therefor
US7279795B2 (en) 2005-12-29 2007-10-09 Intel Corporation Stacked die semiconductor package
TWI325619B (en) 2006-09-26 2010-06-01 Powertech Technology Inc Multi-chip package to optimize mold-flow balance
US20080079150A1 (en) * 2006-09-28 2008-04-03 Juergen Simon Die arrangement and method for producing a die arrangement
TW200820406A (en) 2006-10-19 2008-05-01 Novatek Microelectronics Corp Chip structure and wafer structure
JP4922891B2 (ja) 2006-11-08 2012-04-25 株式会社テラミクロス 半導体装置およびその製造方法
US20090197114A1 (en) 2007-01-30 2009-08-06 Da-Yuan Shih Modification of pb-free solder alloy compositions to improve interlayer dielectric delamination in silicon devices and electromigration resistance in solder joints
US7576435B2 (en) 2007-04-27 2009-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Low-cost and ultra-fine integrated circuit packaging technique
US7820543B2 (en) 2007-05-29 2010-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced copper posts for wafer level chip scale packaging
CN101320696A (zh) * 2007-06-04 2008-12-10 矽品精密工业股份有限公司 堆叠式封装结构及其制法
US20090020869A1 (en) 2007-07-17 2009-01-22 Qing Xue Interconnect joint
KR101213175B1 (ko) 2007-08-20 2012-12-18 삼성전자주식회사 로직 칩에 층층이 쌓인 메모리장치들을 구비하는반도체패키지
US7667335B2 (en) 2007-09-20 2010-02-23 Stats Chippac, Ltd. Semiconductor package with passivation island for reducing stress on solder bumps
US8269345B2 (en) 2007-10-11 2012-09-18 Maxim Integrated Products, Inc. Bump I/O contact for semiconductor device
US8492263B2 (en) 2007-11-16 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Protected solder ball joints in wafer level chip-scale packaging
US20090174069A1 (en) 2008-01-04 2009-07-09 National Semiconductor Corporation I/o pad structure for enhancing solder joint reliability in integrated circuit devices
US20090206480A1 (en) 2008-02-20 2009-08-20 Atmel Corporation Fabricating low cost solder bumps on integrated circuit wafers
US20120153444A1 (en) * 2009-06-18 2012-06-21 Rohm Co., Ltd Semiconductor device
JP2013030498A (ja) 2009-11-12 2013-02-07 Panasonic Corp 半導体装置
US8299616B2 (en) 2010-01-29 2012-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. T-shaped post for semiconductor devices
KR101176348B1 (ko) 2010-02-05 2012-08-24 앰코 테크놀로지 코리아 주식회사 반도체 장치 및 그 제조 방법
US8803319B2 (en) 2010-02-11 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar structure having a non-planar surface for semiconductor devices
US8318596B2 (en) 2010-02-11 2012-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar structure having a non-planar surface for semiconductor devices
US20110227216A1 (en) 2010-03-16 2011-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Under-Bump Metallization Structure for Semiconductor Devices
US8492891B2 (en) 2010-04-22 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with electrolytic metal sidewall protection
US8456945B2 (en) 2010-04-23 2013-06-04 Advanced Micro Devices, Inc. 10T SRAM for graphics processing
US8288849B2 (en) 2010-05-07 2012-10-16 Texas Instruments Incorporated Method for attaching wide bus memory and serial memory to a processor within a chip scale package footprint
US8241963B2 (en) 2010-07-13 2012-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Recessed pillar structure
JP6081044B2 (ja) 2010-09-16 2017-02-15 富士通株式会社 パッケージ基板ユニットの製造方法
US8669137B2 (en) * 2011-04-01 2014-03-11 International Business Machines Corporation Copper post solder bumps on substrate
US8535983B2 (en) 2011-06-02 2013-09-17 Infineon Technologies Ag Method of manufacturing a semiconductor device
US9230932B2 (en) 2012-02-09 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect crack arrestor structure and methods

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6081038A (en) * 1998-04-07 2000-06-27 Shinko Electric Industries Co., Ltd. Semiconductor chip package structure
US20090212423A1 (en) * 2007-08-21 2009-08-27 Junji Tanaka Stacked solder balls for integrated circuit device packaging and assembly
US20100102444A1 (en) * 2008-10-23 2010-04-29 Carsem (M) Sdn. Bhd. Wafer level package using stud bump coated with solder

Also Published As

Publication number Publication date
TW201349419A (zh) 2013-12-01
DE102012107760B4 (de) 2020-12-31
US10453815B2 (en) 2019-10-22
US20130277838A1 (en) 2013-10-24
KR20130118719A (ko) 2013-10-30
KR101430830B1 (ko) 2014-08-18
CN103378037A (zh) 2013-10-30
TW201705413A (zh) 2017-02-01
US9515036B2 (en) 2016-12-06
TWI565014B (zh) 2017-01-01
US20170084560A1 (en) 2017-03-23
DE102012107760A1 (de) 2013-10-24
CN103378037B (zh) 2016-07-06

Similar Documents

Publication Publication Date Title
TWI607537B (zh) 半導體裝置
US11193953B2 (en) 3D chip testing through micro-C4 interface
TWI483357B (zh) 封裝結構
US7361990B2 (en) Reducing cracking of high-lead or lead-free bumps by matching sizes of contact pads and bump pads
US9082763B2 (en) Joint structure for substrates and methods of forming
TWI509762B (zh) 積體電路封裝及其製造方法
US9147661B1 (en) Solder bump structure with enhanced high temperature aging reliability and method for manufacturing same
US20140008786A1 (en) Bump-on-trace packaging structure and method for forming the same
US8994175B2 (en) Method of manufacturing semiconductor device and semiconductor device
US20080316721A1 (en) Electrode structure body and method of forming the same, electronic component, and mounting substrate
KR100961309B1 (ko) 반도체 패키지
US9349705B2 (en) Method of fabricating a semiconductor structure having conductive bumps with a plurality of metal layers
KR101037827B1 (ko) 반도체 패키지
KR100961310B1 (ko) 반도체 패키지
KR100961311B1 (ko) 반도체 패키지
KR20100000328A (ko) 조인트 신뢰성이 향상된 반도체 패키지 및 그 제조방법
TWI483360B (zh) 封裝基板及其製法
KR100961308B1 (ko) 반도체 패키지
US11749590B2 (en) Wiring substrate device