TWI509762B - 積體電路封裝及其製造方法 - Google Patents

積體電路封裝及其製造方法 Download PDF

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Publication number
TWI509762B
TWI509762B TW099134540A TW99134540A TWI509762B TW I509762 B TWI509762 B TW I509762B TW 099134540 A TW099134540 A TW 099134540A TW 99134540 A TW99134540 A TW 99134540A TW I509762 B TWI509762 B TW I509762B
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Taiwan
Prior art keywords
solder
integrated circuit
lead
copper
metal
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TW099134540A
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English (en)
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TW201128752A (en
Inventor
Yao Chun Chuang
Ching Wen Hsiao
Chen Cheng Kuo
Chen Shien Chen
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Taiwan Semiconductor Mfg Co Ltd
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Publication of TW201128752A publication Critical patent/TW201128752A/zh
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Publication of TWI509762B publication Critical patent/TWI509762B/zh

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    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
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Description

積體電路封裝及其製造方法
本發明係有關於一種積體電路，利用無鉛焊料凸塊、無鉛焊料球或無鉛焊料柱狀物連接至一電路板，以於該積體電路與例如一覆晶封裝積體電路的其他電路之間形成連接，本發明提供利用無鉛焊料材料製作可靠性連接的方法。併入本發明特徵的積體電路封裝及方法可與習知現存態樣及規劃的半導體製程相容。
目前，對於先進電子電路，特別是半導體製程中製作如積體電路(ICs)的電路的一般須求為使用焊料凸塊(solder bump)、焊料球(solder ball)或焊料柱狀物連接(solder column connections)。在一達成封裝與內連接(interconnections)的”覆晶(flip chip)”方法中，即使用焊料凸塊耦接單晶(monolithic)積體電路(可為一具有主動或被動電路元件的矽基板及形成於其上的連接(connections)或可使用包括砷化鎵(GaAs)、絕緣層上覆矽(SOI)及鍺化矽(SiGe)的其他基板材料)的外部終端至一封裝基板或電路板。該些積體電路元件可具有數十或數百個輸入及輸出終端，以接收、傳輸信號及/或耦接至電源供應器連接部(power supply connections)。在某些積體電路(IC)設計中，係將終端(terminals)置於積體電路周邊，遠離主動電路。而在更先進及複雜的積體電路中，可將終端置於主動區上，覆蓋主動元件。在記憶體積體電路(ICs)中，有時則使用中心墊排列(center pad arrangement)。
在一”覆晶”的應用中，有時將積體電路(IC)正面朝下(翻覆(flipped))安裝。形成終端開口於一保護絕緣層中，該保護絕緣層稱為一鈍化層，覆蓋元件表面。露出輸入/輸出終端並將焊料凸塊、焊料柱狀物或焊料球置於通常視為墊層(pads)或土地(lands)的終端上。該些終端自積體電路表面延伸，可形成如柱狀物的導電材料。之後，利用焊料球形成外部連接至積體電路。可提供焊料球利用一”晶圓級(wafer scale)”方法先形成於完整的積體電路上或可於切割元件成所謂”晶粒(dice)”的各別元件後再加入焊料球甚或設置於一基板或電路板上，之後，將積體電路對準焊料球並小心置於其上。在任一例中，通常利用一熱回焊(thermal solder reflow)製程以完成覆晶積體電路與一基板、膜、印刷電路板或甚至另一矽元件之間的焊料連接。在熱回焊的過程中，焊料凸塊、焊料球或焊料柱狀物於積體電路終端與基板之間形成一永久的機械及電性導電連接。之後，可對結合的覆晶積體電路(IC)與基板進行封裝形成一單一積體電路。而在一多重晶片模組型式中，可將覆晶選擇性地結合其他積體電路(亦可為多個覆晶或可利用焊線連接(wire bond connections))。例如有時將例如快閃(FLASH)非揮發元件的記憶體元件與用於快閃(FLASH)元件程式化或資料儲存的處理器結合於一單一封裝元件中。積體電路(IC)元件可垂直堆疊或利用一較大基板或電路板並排放置另一積體電路(IC)元件。
目前，半導體工業已推動”無鉛(Pb)”封裝及元件連接子技術。此趨勢逐漸導致無鉛焊料凸塊及無鉛焊料球的使用形成與積體電路及封裝結構的連接。該些無鉛焊料材料由錫及其合金所形成，可包括例如銀、鎳、銅及其他金屬。對環境、工廠中的工作者及消費者來說，使用無鉛焊料球較使用以鉛為主體的焊料凸塊或焊料球更為安全。然而，最終形成的焊料連接的品質及可靠度並非總是如預期所想的好。在熱循環(TC)測試的過程中，例如在完成的焊料連接中會發現裂縫。典型的熱循環測試將實施500熱循環(TC 500)，其範圍自最低特定溫度(一般為-55℃)至最高特定溫度(一般為+125℃)，之後，觀察焊料連接。通常於利用傳統無鉛焊料連接進行TC 500的測試後，會發現球裂縫。球裂縫可作為一應用中實際操作過程的指標。焊料連接將會因扯裂而失效。很清楚地，此種焊料連接並不為最終產品所接受。
此外，最近積體電路內連線技術的進展已自使用於積體電路內及延伸至終端的鋁或其合金導體轉變為以銅為主體的內連線技術。通常利用一鑲嵌或雙鑲嵌方法形成銅導體於基板上。於此種技術中，形成一溝槽或溝槽與介層窗的結合於一形成層間介電層(ILD)或金層層間介電層(IMD)的絕緣介電材料中。形成一銅或其合金的晶種層於溝槽內。利用電鍍或無電鍍化學沈積(ECD)將以銅為主體的內連線材料填入溝槽及/或介層窗開口。有時，利用一化學機械製程(CMP)機具以機械及化學的方式磨除溝槽表面上多餘的銅材料，以於溝槽或介層窗頂部形成一平坦表面。此處，於介電層中的溝槽圖案最終將決定導體的圖案。可形成多層內連線於電晶體及主動元件上，通常形成於其下半導體基板的表面。可將銅或其合金的內連線材料延伸至積體電路的終端墊、球土地或柱狀物。在此傳統例中，隨後將沈積焊料凸塊或球於此銅或其合金的材料上。
根據形成於銅墊上無鉛焊料球或凸塊的TC500測試及分析指出使用銅作為積體電路於焊料球終端的一金屬化材料及/或於接收覆晶積體電路的相對電路板的圖案上會導致球產生球裂縫。在屬於一熱製程的回焊過程中，形成一介金屬化合物(intermetallic compound,IMC)於積體電路終端(銅墊或柱狀物)與焊料材料之間的焊料球內。然而，若球於焊料與介金屬化合物(IMC)之間的介面無法有好的黏附，則球裂縫極有可能發生。
因此，用於封裝積體電路及形成至電路板間低阻的電連接，以形成穩固且高品質的電連接、機械連接，並同時使用無鉛焊料材料的方法及裝置是必要的。
於本發明之一典型實施例中，一積體電路封裝包括一積體電路，形成於一半導體基板上。該積體電路具有至少一輸入/輸出終端，包括銅，形成於該積體電路之一上半部中，以及一金屬蓋層，覆蓋該至少一輸入/輸出終端之一上表面。一基板，包括至少一導電圖案，形成於一第一表面，且具有一金屬拋光層，覆蓋一部分之該至少一導電圖案並形成一焊料墊。一無鉛焊料連接，設置於該金屬蓋層與該焊料墊之間，其中該無鉛焊料連接之銅含量低於0.5wt%(重量百分比)。
於本發明之另一典型實施例中，一積體電路封裝包括一電路板，具有複數個焊料球，設置於該電路板之一下表面。複數個導電圖案，設置於該電路板之一上表面，並電性耦接至不同之一或多個該焊料球。複數個終端，於該電路板之該上表面，耦接至不同之該導電圖案其中之一並具有一金屬拋光，包括鎳。一覆晶積體電路，具有輸入/輸出終端，包括銅，正面朝下定位，每一該輸入/輸出終端具有一下表面，面對該電路板之該上表面。一金屬蓋層，包括鎳，形成於每一該輸入/輸出終端之該下表面。複數個無鉛焊料連接子，於該金屬蓋層與該終端之該金屬拋光之間形成連接。
於本發明之另一典型實施例中，提供一積體電路封裝之製造方法，包括提供一積體電路，具有輸入/輸出終端，供形成於一表面上之外部連接子。提供複數個銅柱狀物，自該輸入/輸出終端延伸，每一該銅柱狀物具有一下表面。提供一蓋層，包括鎳，覆蓋每一該銅柱狀物之該下表面。提供一無鉛焊料連接子，於每一該蓋層上。該方法續定位該積體電路，具有該蓋層之該銅柱狀物與該無鉛焊料連接子面對一基板之一上表面，該基板具有一以鎳為主體之金屬拋光，覆蓋複數個焊料球墊，該焊料球墊對準不同該無鉛焊料連接子其中之一。放置該無鉛焊料連接子鄰近相對應之該焊料球墊。實施一熱回焊製程，以焊接該基板上之該焊料球墊至該積體電路之該輸入/輸出終端，該無鉛焊料連接子黏接至該焊料球墊與該蓋層。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說明如下：
第1圖描述一傳統球柵陣列(ball grid array,BGA)積體電路封裝10，其利用一覆晶排列(flip chip arrangement)所形成。於第1圖中，提供一積體電路(IC)1，其可為一記憶體、處理器、類比或數位電路、特定應用積體電路(ASIC)、混合信號電路或其他元件。積體電路(IC)1具有柱狀物(column)5，用來形成球墊(ball pads)或球土地(ball lands)的，以形成積體電路(IC)輸入/輸出終端。將覆晶積體電路(IC)1正面朝下安裝並面對一基板9上表面。基板9可為一印刷電路板、一矽基板、一陶瓷基板、一塑膠基板、一膜、一箔或其他電路傳輸介質(circuit carrying medium)。利用外部焊料球(external solder balls)13將完整元件安裝至一系統級電路板。球柵陣列封裝與焊料球13使用的替代為針柵陣列(pin grid array)、含鉛與無鉛陶瓷載體、塑膠載體及本領域具有通常知識者所熟知的其他積體電路(IC)封裝與模組。
於第1圖中，顯示無鉛焊料球(lead free solder balls)7，其可包括錫(Sn)、銀(Ag)及銅，例如形成所謂的SAC型焊料連接子(solder connectors)。本發明可使用其他錫合金。該等焊料球的重要特徵即是不包含傳統的鉛(Pb)材料。於第1圖中，顯示一可選擇的底部膠材(underfill)3，例如一環氧樹脂、樹脂、塑膠成型化合物(plastic molding compound)或其他材料。上述底部膠材毋須使用於所有實施例中。若使用底部膠材，於形成封裝10後，當封裝正常地經歷熱應力時，其可提供強度及熱應力補償(thermal stress compensation)。在形成封裝10的圖1中，將焊料球7對準於基板9上的金屬拋光墊(metal finish pads)11。之後，實施一熱回焊(thermal solder reflow)，以使焊料球7回焊黏接至銅柱狀物5並與電路板9上的金屬拋光墊11連接。至此，完成積體電路1與封裝基板9之間的機械與電性連接。雖圖1未顯示，然，基板9通常為一多層電路板，其包括一重分佈層(redistribution layer)。此一重分佈層可作為自積體電路柱狀物5至焊料球13的連接。此外，可使用一凸塊下金屬(under bump metallization,UBM)層於銅柱狀物5與積體電路終端之間。
第2圖為一電子顯微照相，其為一焊料球連接27的一樣品經一第一500循環熱測試的結果。於該實施例中，使用無鉛焊料27於一積體電路21上的一銅柱狀物焊料墊25。排列該焊料並連接至一基板電路板上的一墊層31。放大第2圖的電子顯微照相，其顯示自積體電路21延伸的銅柱狀物25與一電路板29，具有金屬拋光球墊(metal finish ball pad)31。於該樣品中，使用一銅或銅合金柱狀物25作為積體電路(IC)終端。電路板上的金屬拋光球墊31亦為銅或一銅合金。於完成組合與TC 500熱循環測試後，顯示出無鉛焊料球27。圖中感興趣的區域為介金屬化合物(intermetallic compound,IMC)24與其鄰近的焊料-介金屬化合物(IMC)介面。於500循環的熱循環測試後，於樣品中可清楚看出球裂縫(ball cracks)26。介金屬化合物24此處已定義為銅錫合金(Cu6 Sn5 )。
第3圖描述一無鉛焊料球27的一第二500循環熱測試樣品。於第3圖的樣品中，顯示使用無鉛焊料於一積體電路21上的一鎳或鎳合金柱狀物焊料墊35，並連接至一電路板上的一銅墊層31。再次放大第3圖的電子顯微照相，其顯示自積體電路21延伸的鎳柱狀物35與一電路板，具有一金屬拋光球墊31。於該樣品中，使用一鎳柱狀物球墊35作為積體電路(IC)終端。電路板29上的金屬拋光球墊31為銅或一銅合金。圖中感興趣的區域為介金屬化合物(intermetallic compound,IMC)34與其鄰近的焊料-介金屬化合物(IMC)介面。於500循環的熱循環測試後，於樣品中亦可清楚看出球裂縫36。介金屬化合物34此處已定義為銅鎳錫合金((Cu,Ni)6 Sn5 )。
第4圖描述一無鉛焊料球27的一第三500循環熱測試樣品。使用無鉛焊料球27於一積體電路21上的一銅或銅合金焊料墊25，並連接至一電路板上的一鎳金屬墊32。再次放大第4圖的電子顯微照相，其顯示自積體電路21延伸的銅柱狀物球土地(copper column ball land)25與一電路板29，具有一鎳金屬拋光墊32。圖中顯示出無鉛焊料球27且其感興趣的區域為介金屬化合物(intermetallic compound,IMC)34與其鄰近的焊料-介金屬化合物(IMC)介面。於500循環的熱循環測試後，於樣品中再次可清楚看出球裂縫36。介金屬化合物34此處已定義為銅鎳錫合金((Cu,Ni)6 Sn5 )。
於2、3、4圖的每一測試樣品中，將銅或銅合金直接與無鉛焊料連接，於熱循環測試後，可觀察出球裂縫(ball cracks)。此外，球裂縫總是鄰近介金屬化合物(IMC)與焊料之間的厚介面，例如銅錫(CuSn)/焊料或銅鎳錫((Cu,Ni)Sn)/焊料。
在一文獻(“Evolution of Ag3 Sn compound formation in Ni/Ag3 Sn/Cu solder joint”in Materials Letters,Vol. 62,pages 3887-3889,2008,by H.W. Tseng and C. Y. Liu)中，對焊料樣品進行分析後發現，當使用鎳與銅材料於一無鉛焊料連接(lead free solder connection)的相對側上時，會形成銀錫合金(Ag3 Sn)沈澱物，上述無鉛焊料連接包括例如一具有銀的焊料(Sn5 Ag)。此文獻亦指出銀錫合金(Ag3 Sn)沈澱物偏好存在於如下焊料/介金屬化合物(IMC)形成(solder/IMC formation)的區域內，例如銅鎳錫合金((Cu,Ni)6 Sn5 )>銅錫合金(Cu6 Sn5 )>焊料(solder)>鎳錫合金(Ni3 Sn4 )。在該文獻中，於250℃隨時間對一位於鎳與銅終端之間的樣品焊料進行分析，結果發現銀錫合金(Ag3 Sn)沈澱物，且該銀錫合金(Ag3 Sn)沈澱物聚集於銅鎳錫合金((Cu,Ni)6 Sn5 )所在的區域。上述分析亦顯示當銅原子隨時間移動穿過焊料材料朝向鎳材料時，於焊料中銅原子的移動性(mobility)。
在以錫為主體的無鉛焊料中，銀(Ag)為一必要成分元素，將其加入無鉛焊料以達到特定期望的機械性質。使用錫銀合金(SnAg)焊料結合銅墊層可導致銀錫合金(Ag3 Sn)沈澱物，其形成於介金屬化合物(IMC)與殘留焊料之間的介面。根據球裂縫TC 500樣品的分析發現，銀錫合金(Ag3 Sn)沈澱物的黏著性及機械性質均不佳，致該種材料於介金屬化合物(IMC)/焊料介面的存在增加了焊料球裂縫。此外，銅的高移動性於許多材料中會顯現出擴散現象，包括於無鉛焊料球材料中，且使用銅作為焊料球柱狀物或墊層時，銅介金屬化合物會快速形成。當一厚的銅錫合金(CuSn)材料形成於焊料連接子與一銅的墊層、柱狀物(column)或圖案(trace)之間的焊料/介金屬化合物(IMC)介面時，球裂縫較有可能發生。
對其介面區域包含或不含銀錫合金(Ag3 Sn)沈澱物的樣品進行分析後發現，當於介金屬化合物(IMC)/焊料介面無或鮮少銀錫合金(Ag3 Sn)分子時，並不產生球裂縫(ball cracks)，而其他樣品顯示，當較多銀錫合金(Ag3 Sn)分子存在時，於介金屬化合物(IMC)/焊料介面的球裂縫(ball cracks)則會增加。
根據本發明一實施例，提供新穎的方法及裝置以改善使用無鉛焊料製造的焊料連接(solder connections)的強度，以及減少或排除先前所使用傳統無鉛焊料覆晶排列中發現的球裂縫(ball cracks)。
第5圖為根據本發明之一實施例，一單一無鉛焊料連接的一剖面示意圖。於第5圖中，一積體電路51具有一銅或銅合金柱狀物或柱55，其自積體電路延伸並作為一輸入/輸出終端。在一特定應用中，有數十、數百或甚至數千個銅柱連接的須求以提升積體電路效能。在一積體電路的一典型實施例中，該些銅柱形成於一45奈米半導體製程節點，高度大約40微米。然而，柱狀物55的高度將隨元件尺寸、製程技術而變動。本發明並不限定製造者及該些柱狀物的高度或厚度。提供一金屬蓋層56於銅柱55的至少底部外表面上。在此實施例中，於銅柱側壁上並不須形成金屬蓋層，可簡化製程。本發明可藉由習知的電鍍或沈積金屬層的無電鍍製程形成蓋層56。本發明可藉由數個已知的方法，包括電鍍、無電鍍製程、例如化學氣相沈積(chemical vapor deposition,CVD)製程的任何化學沈積方法或物理氣相沈積(PVD)製程形成蓋層56。在不同可選擇的實施例中，使用包括鎳(Ni)、鎳(Ni)合金，例如鎳鈷(Ni(Co))、鎳釩(Ni(V))、鎳磷(Ni(P))、鎳鉍(Ni(Bi))、鈀(Pd)、鉑(Pt)、金(Au)、銀(Ag)、鈷(Co)的材料作為蓋層56。上述每一材料可考慮作為一額外實施例。且可結合數層形成額外實施例。
在一典型實施例中，使用一鎳蓋層。雖鎳蓋層的厚度隨著半導體製程將變動及微縮，然，在一實施例中，鎳蓋層可薄如1微米厚。只要蓋層可將銅柱材料與無鉛焊料隔離，若須要，其厚度會大體較厚。當積體電路元件尺寸微縮時，銅柱狀物將微縮，焊料凸塊亦將稍微變小，而蓋層的厚度亦會變動。重要的是，蓋層56可避免銅原子接觸無鉛焊料球。蓋層必須具備足夠厚度以在製程過程及後續熱循環過程中避免或降低多數銅原子擴散進入無鉛焊料球。形成於此實施例中58區域的介金屬化合物(IMC)為鎳錫合金(Ni3 Sn4 )。
形成一無鉛焊料連接子57於積體電路51與電路板或基板59之間。此處使用的無鉛焊料球，其介於10微米至400微米之間，可包括例如上述的錫(Sn)與銀(Ag)。一焊料球墊61顯示於具有一金屬拋光的電路板上。在一典型實施例中，金屬拋光亦為一鎳拋光。其他替代物包括以鎳為主體的拋光，例如鎳合金。本發明可使用鎳/金。亦可使用其他如無電鍍鎳金合金(electroless nickel and alloy gold,ENAG)、無電鍍鎳無電鍍鈀浸金(electroless nickel electroless palladium and immersion gold,ENEPIG)、無電鍍鎳浸金(electroless nickel immersion gold,ENIG)及其他包括鎳的金屬拋光層。金屬拋光的厚度可變動，但大體介於0.3~8微米之間。有時，若使用銅或微量銅於基板或電路板中，則金屬拋光為一覆蓋於表面上的額外層，以確保熱回焊發生前、中或後，電路板上來自電路圖案(trace)的銅不會與無鉛焊料球接觸。只要來自基板圖案的銅在一開始積體電路(IC)安裝於基板上時或於熱回焊及熱循環後不會與焊料材料接觸，則金屬拋光的厚度可相當薄且可變動。例如在目前製程中，其厚度可自0.8至8微米。重要特徵為在熱循環過程中，銅不會與無鉛焊料接觸，不會擴散進入焊料連接子。
形成於此實施例中的介金屬化合物(IMC)58將為鎳錫合金(Ni3 Sn4 )。銅將不會與無鉛焊料接觸，不會擴散進入焊料形成如傳統方法中不期望的銅錫合金(Cu6 Sn5 )或銅鎳錫合金((Cu,Ni)6 Sn5 )介金屬化合物。
出人意外地發現在回焊的過程中或完成後，當大幅度地降低或排除銅在無鉛焊料連接子中出現時，於傳統的排列中將不會產生球裂縫。較佳為積體電路柱狀物蓋層(integrated circuit column cap layers)與基板的金屬拋光(metal finish)兩者均由鎳或鎳合金所構成，而使焊料連接子以一鎳/焊料/鎳的排列方式設置。此外，銅在無鉛焊料凸塊中的含量必須減少或排除。在回焊後，焊料連接子中銅的重量必須低於0.5wt%(重量百分比)。若維持低濃度的銅，則於柱狀物/焊料球介面處形成於焊料球中的介金屬化合物(IMC)將會是上述的鎳錫合金(Ni3 Sn4 )，而銀錫合金(Ag3 Sn)沈澱物對其偏好低於焊料本身。因此，銀錫合金(Ag3 Sn)沈澱物將不會聚集在介金屬化合物與焊料之間的介面。因此，不會發生傳統方法中無鉛焊料球有關黏著性與可靠度的問題。更令人驚訝地發現，當典型實施例使用該無鉛焊料材料時，竟不會產生球裂縫(ball cracks)或已大幅減少。
上述典型實施例中，使用以鎳為主體的蓋層及以鎳為主體的金屬拋光。然而，亦可使用其他替代物以避免銅自金屬蓋層與基板圖案擴散進入無鉛焊料連接子。作為額外實施例的替代物包括蓋層與金屬拋光材料，例如鈀(Pd)、鉑(Pt)、金(Au)、銀(Ag)、鈷(Co)及其合金。由於在介金屬化合物(IMC)-焊料介面形成的介金屬化合物(IMC)將不會是銅錫合金(Cu-Sn)，因此，使用上述蓋層與金屬拋光材料亦將減少或排除傳統方法中有關球裂縫的問題。最終形成的無鉛焊料連接子在經熱測試後，將不會出現球裂縫或已大幅減少。
第6圖為根據本發明典型實施例，一覆晶封裝排列70，其納入蓋層與金屬拋光。於第6圖中，積體電路71以一覆晶方式排列，其正面向下對應基板79的上表面。焊料球13提供連接子至最終封裝。此處可使用一底部膠材3。銅或銅合金柱狀物75延伸自積體電路71並提供輸入/輸出連接至積體電路71。如上所述，形成一鎳或鎳合金的蓋層76於銅柱狀物75下表面。無鉛焊料連接子7可為凸塊、或球或焊料的柱狀物，設置於鎳蓋層76上。提供一以鎳為主體的金屬拋光78覆蓋基板79中圖案11上的焊料球墊終端(solder ball pad terminals)以及焊料連接子7，以形成積體電路71與基板79之間的電性及機械連接。由於每一焊料連接子7位於兩鎳材料表面之間，因此，於回焊後，可排除或減少焊料連接子中的銅，使其低於0.5wt%。如此，將可減少或排除球裂縫。
第7圖描述連接一積體電路至一基板或電路板的方法的一流程圖。此方法開始於步驟ST01，提供一積體電路，具有銅柱狀物供焊料連接。於步驟ST02中，形成一鎳或鎳合金或其他蓋層於該柱狀物的外表面上。此處不須將鎳蓋層設置於該銅柱狀物暴露的側壁上。於步驟ST03中，設置例如焊料凸塊、焊料球或焊料柱狀物的無鉛焊料連接於該柱狀物的該蓋層上。於步驟ST04中，提供一基板，具有以鎳為主體的金屬拋光或可選擇的金屬拋光其中之一，其設置於墊層上以接受該焊料連接。將該基板對準該焊料連接。於步驟ST05中，實施一回焊(reflow)，以完成機械及電性連接。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可作更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
1、21、51、71．．．(覆晶)積體電路
3．．．底部膠材
5．．．(積體電路)(銅)柱狀物
7、57．．．(無鉛)焊料球((無鉛)焊料連接子)
9、29、59、79．．．(封裝)基板(電路板)
10．．．(球柵陣列積體電路)封裝
11．．．金屬拋光墊、圖案
13．．．(外部)焊料球
24、34、58．．．介金屬化合物
25．．．銅柱狀物焊料墊(銅或銅合金柱狀物)(銅或銅合金焊料墊)(銅柱狀物球土地)
26、36．．．球裂縫
27．．．焊料球連接(無鉛焊料(球))
31．．．(銅)墊層(金屬拋光球墊)
32．．．鎳金屬(拋光)墊
35．．．鎳或鎳合金柱狀物焊料墊(鎳柱狀物(球墊))
55、75．．．(銅或銅合金)柱狀物(銅或銅合金柱)(銅柱)
56．．．(金屬)蓋層
61．．．焊料球墊
70．．．覆晶封裝排列
76．．．(鎳)蓋層
78．．．以鎳為主體之金屬拋光
ST01．．．提供積體電路，具有銅柱狀物供焊料連接
ST02．．．形成鎳或鎳合金蓋層
ST03．．．提供無鉛焊料於該蓋層上
ST04．．．提供基板，具有以鎳為主體的金屬拋光，設置於焊料墊上
ST05．．．實施回焊
第1圖揭露一積體電路的一傳統覆晶球柵陣列(BGA)封裝；
第2圖係根據本發明之一第一實施例，一無鉛焊料連接樣品進行一熱循環測試後，經一電子顯微照相放大的一剖面圖，圖中並顯示球裂縫；
第3圖係根據本發明之一第二實施例，一無鉛焊料連接樣品進行一熱循環測試後，經一電子顯微照相放大的一剖面圖，圖中並顯示球裂縫；
第4圖係根據本發明之一第三實施例，一無鉛焊料連接樣品進行一熱循環測試後，經一電子顯微照相放大的一剖面圖，圖中並顯示球裂縫；
第5圖係根據本發明之一第一典型實施例，一剖面示意圖；
第6圖係根據本發明之一第二典型實施例，一剖面示意圖；
第7圖係根據本發明之一方法實施例，一方法步驟的流程圖。
ST01．．．提供積體電路，具有銅柱狀物供焊料連接
ST02．．．形成鎳或鎳合金蓋層
ST03．．．提供無鉛焊料於該蓋層上
ST04．．．提供基板，具有以鎳為主體的金屬拋光，設置於焊料墊上
ST05．．．實施回焊

Claims (9)

  1. 一種積體電路封裝，包括：一積體電路，包括：至少一輸入/輸出終端，包括銅，形成於其上；一金屬蓋層，直接覆蓋該至少一輸入/輸出終端之一上表面，其中該金屬蓋層擇自由鎳、鈀、銀、鉑、金、鈷、其合金及其組合所組成之族群；一基板，包括至少一導電圖案，形成於一第一表面；一金屬拋光層，覆蓋一部分之該至少一導電圖案並形成一焊料墊，其中該金屬拋光層係以鎳為主體；一無鉛焊料連接，設置於該金屬蓋層與該焊料墊之間；以及一介金屬化合物，位於該金屬蓋層與該無鉛焊料連接之間，其中該無鉛焊料連接之銅含量低於0.5wt%，且該介金屬化合物大致上無含銅。
  2. 如申請專利範圍第1項所述之積體電路封裝，其中該無鉛焊料連接為一焊料球或一焊料凸塊，設置於該積體電路之該金屬蓋層上。
  3. 如申請專利範圍第1項所述之積體電路封裝，更包括一焊料球，設置於該基板之一第二表面。
  4. 一種積體電路封裝，包括：一電路板，具有複數個焊料球，設置於該電路板之一下表面；複數個導電圖案，設置於該電路板之一上表面，每 一該導電圖案電性耦接至不同之一或多個該焊料球；複數個終端，於該電路板之該上表面，每一該終端耦接至不同之該導電圖案其中之一並具有一金屬拋光，包括鎳；一覆晶積體電路，具有輸入/輸出終端，包括銅，每一該輸入/輸出終端具有一下表面，面對該電路板之該上表面；一金屬蓋層，包括鎳，直接形成於每一該輸入/輸出終端之該下表面；複數個無鉛焊料連接子，於該金屬蓋層與該終端之該金屬拋光之間形成連接；以及一介金屬化合物，位於該金屬蓋層與該無鉛焊料連接子之間，其中該介金屬化合物大致上無含銅。
  5. 如申請專利範圍第4項所述之積體電路封裝，其中每一該無鉛焊料連接子包括一銅含量，低於0.5wt%。
  6. 如申請專利範圍第4項所述之積體電路封裝，其中該金屬拋光更包括金、浸金(immersion gold)或無電鍍鈀浸金(electroless palladium and immersion gold)。
  7. 一種積體電路封裝之製造方法，包括：提供一積體電路，具有輸入/輸出終端，供形成於一表面上之外部連接子；形成複數個銅柱狀物，自該輸入/輸出終端延伸，每一該銅柱狀物具有一下表面；形成一蓋層，包括鎳，直接覆蓋每一該銅柱狀物之該下表面； 提供一無鉛焊料連接子，於每一該蓋層上；定位該積體電路，具有該蓋層之該銅柱狀物與該無鉛焊料連接子面對一基板之一上表面，該基板具有一以鎳為主體之金屬拋光，覆蓋複數個焊料球墊，該焊料球墊對準不同該無鉛焊料連接子其中之一；放置該無鉛焊料連接子鄰近相對應之該焊料球墊；以及實施一熱回焊製程，以焊接該基板上之該焊料球墊至該積體電路之該輸入/輸出終端，該無鉛焊料連接子黏接至該焊料球墊與該蓋層，且在該蓋層與該無鉛焊料連接子之間形成一介金屬化合物，其中該介金屬化合物大致上無含銅。
  8. 如申請專利範圍第7項所述之積體電路封裝之製造方法，其中該無鉛焊料連接子具有一銅含量，低於0.5wt%。
  9. 如申請專利範圍第7項所述之積體電路封裝之製造方法，其中提供具有以鎳為主體之該金屬拋光之該基板包括實施一無電鍍鎳無電鍍鈀浸金(electroless nickel electroless palladium and immersion gold,ENEPIG)製程或實施一無電鍍鎳浸金(electroless nickel immersion gold,ENIG)製程。
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Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010161136A (ja) * 2009-01-07 2010-07-22 Panasonic Corp 半導体装置及びその製造方法
KR101119839B1 (ko) * 2010-05-23 2012-02-28 주식회사 네패스 범프 구조물 및 그 제조 방법
US8901747B2 (en) 2010-07-29 2014-12-02 Mosys, Inc. Semiconductor chip layout
JP6076020B2 (ja) * 2012-02-29 2017-02-08 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
US9269681B2 (en) 2012-11-16 2016-02-23 Qualcomm Incorporated Surface finish on trace for a thermal compression flip chip (TCFC)
US9773724B2 (en) * 2013-01-29 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, methods of manufacture thereof, and semiconductor device packages
JP2015056641A (ja) * 2013-09-13 2015-03-23 株式会社東芝 半導体装置及びその製造方法
WO2015147844A1 (en) * 2014-03-27 2015-10-01 Intel Corporation Hybrid interconnect for low temperature attach
KR102212559B1 (ko) 2014-08-20 2021-02-08 삼성전자주식회사 반도체 발광소자 및 이를 이용한 반도체 발광소자 패키지
CN104900535B (zh) * 2015-04-07 2017-07-07 北京理工大学 太赫兹芯片倒桩焊背景下陶瓷薄膜导电过孔的焊料填充工艺
US9865565B2 (en) 2015-12-08 2018-01-09 Amkor Technology, Inc. Transient interface gradient bonding for metal bonds
US10269714B2 (en) 2016-09-06 2019-04-23 International Business Machines Corporation Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements
US10037957B2 (en) 2016-11-14 2018-07-31 Amkor Technology, Inc. Semiconductor device and method of manufacturing thereof
US10403591B2 (en) * 2017-10-31 2019-09-03 Xilinx, Inc. Chip package assembly with enhanced interconnects and method for fabricating the same
US10347602B1 (en) * 2018-07-23 2019-07-09 Mikro Mesa Technology Co., Ltd. Micro-bonding structure
US10388627B1 (en) * 2018-07-23 2019-08-20 Mikro Mesa Technology Co., Ltd. Micro-bonding structure and method of forming the same
US10763231B2 (en) 2018-07-27 2020-09-01 Texas Instruments Incorporated Bump bond structure for enhanced electromigration performance
CN109729639B (zh) * 2018-12-24 2020-11-20 奥特斯科技(重庆)有限公司 在无芯基板上包括柱体的部件承载件
CN110233110B (zh) * 2019-05-30 2021-04-27 同辉电子科技股份有限公司 一种GaN倒装芯片的焊接方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW311243B (en) * 1996-07-25 1997-07-21 Ind Tech Res Inst Method for detecting thickness polished by chemical mechanical polish and apparatus thereof
US20090090542A1 (en) * 2004-02-04 2009-04-09 Ibiden Co., Ltd. Multilayer printed wiring board
US20100015796A1 (en) * 2001-01-15 2010-01-21 Nec Corporation Semiconductor device, manufacturing method and apparatus for the same

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100687548B1 (ko) * 1999-01-27 2007-02-27 신꼬오덴기 고교 가부시키가이샤 반도체 웨이퍼 제조 방법, 반도체 장치 제조 방법 및 칩 사이즈의 반도체 웨이퍼 패키지 제조 방법
US6277669B1 (en) * 1999-09-15 2001-08-21 Industrial Technology Research Institute Wafer level packaging method and packages formed
KR100576156B1 (ko) * 2003-10-22 2006-05-03 삼성전자주식회사 댐이 형성된 반도체 장치 및 그 반도체 장치의 실장 구조
US20060275952A1 (en) * 2005-06-07 2006-12-07 General Electric Company Method for making electronic devices
DE102005055280B3 (de) * 2005-11-17 2007-04-12 Infineon Technologies Ag Verbindungselement zwischen Halbleiterchip und Schaltungsträger sowie Verfahren zur Herstellung und Verwendung des Verbindungselements
DE102006023998B4 (de) * 2006-05-22 2009-02-19 Infineon Technologies Ag Elektronische Schaltungsanordnung und Verfahren zur Herstellung einer solchen
US7964961B2 (en) * 2007-04-12 2011-06-21 Megica Corporation Chip package
JP4547411B2 (ja) * 2007-10-05 2010-09-22 富士通株式会社 半導体装置、及び半導体装置の製造方法
JPWO2010024233A1 (ja) * 2008-08-27 2012-01-26 日本電気株式会社 機能素子を内蔵可能な配線基板及びその製造方法
US8178970B2 (en) * 2009-09-18 2012-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Strong interconnection post geometry
JP5514560B2 (ja) * 2010-01-14 2014-06-04 ルネサスエレクトロニクス株式会社 半導体装置
US20110186989A1 (en) * 2010-02-04 2011-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Bump Formation Process
US8610270B2 (en) * 2010-02-09 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and semiconductor assembly with lead-free solder
US20110285013A1 (en) * 2010-05-20 2011-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Controlling Solder Bump Profiles by Increasing Heights of Solder Resists
US8901736B2 (en) * 2010-05-28 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Strength of micro-bump joints

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW311243B (en) * 1996-07-25 1997-07-21 Ind Tech Res Inst Method for detecting thickness polished by chemical mechanical polish and apparatus thereof
US20100015796A1 (en) * 2001-01-15 2010-01-21 Nec Corporation Semiconductor device, manufacturing method and apparatus for the same
US20090090542A1 (en) * 2004-02-04 2009-04-09 Ibiden Co., Ltd. Multilayer printed wiring board

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