^11243 at --- B7 五、發明説明（I ) 發明背景 (1) 發明範疇 本發明是關於化學/機械硏磨製程中，偵測沉積層被磨除的厚度的一個 方法及裝置。特別是在CMP製程中，不須將晶片自硏磨裝置上取下，就能即 時偵測硏磨所除去的厚度。 (2) 相關技術 化學/機械硏磨法(CMP)早已被發展出來，應用於硏磨沉積在半導體基 底上的沉積層，以使沉積層的表面佈局平滑。在含有元件線路的基底表面形 成金屬導線時會得到粗糖的表面佈局。這些金屬導線是用來聯結各個離散元 件，因而形成積體電路。金屬導線須進一步利用沉積的絕緣物質所形成的薄 膜與次一層的導線絕緣，而絕緣層間所形成的孔洞則提供了連續的導電層間 的電性接觸。由於很難在粗糙的表面光蝕刻圖像或圖案，因此我們希望在這 樣的佈線製程中，絕緣層的表面能有一個平整的表面佈局。CMP也可以用來 除去半導體基底上不同材質的沉積層。譬如，在介電層上形成孔洞之後，一 金屬層地毯式地沉積下來，然後即可利用CMP來平坦化金屬栓。 經濟部中央標準局負工消費合作社印裝 I-------一---Λ-- f -' - * (請先聞讀背£^注意事項再填寫本頁) 簡言之，CMP製程是在控制的化學、壓力、及溫度條件下，固定住一薄 且平的半導體晶片，使其面對一濕的硏磨表面，並加以旋轉。硏磨材料爲一 包含了礬土或矽土的化學溶液。除此之外，化學溶液還包含了一些特定的化 學物質，這些特定的化學物質在CMP製程中蝕刻晶片的表面。這種在硏磨的 製程中，結合機械及化學以除去物質的方法，使硏磨表面有絕佳的平坦性。 在這個製程裡，很重要的一點是要除去足夠的物質，以使表面平整，但卻不 會過度地除去下層的物質；因此必須在硏磨製程中偵測已磨除的厚度，或者 偵測尙留在基底上的材料厚度。 ’ 在過去，偵測硏磨厚度的方法是中斷CMP製程，將晶片自硏磨裝置取 下，實際檢驗晶片表面，以確定薄膜的厚度，或者包括檢驗晶片表面的佈 局。這種作法不僅須要額外的晶片淸潔步驟’耗費人工的檢驗及測量，還會 降低硏磨裝置的產能。如果晶片尙未達到特定規格，必須將晶片放回硏磨裝 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 A7 • B7 五、發明説明（1) 置，以便作進一步的硏磨。檢驗結果如果發現已經除去過多的物質’則晶片 亦不符合規格’落於標準之下。這種偵測端點及硏磨厚度的方法不僅費時' 成本高 '而且不可靠。因此人們發展出許多在CMP製程中偵測硏磨終點及厚 度的改良方法，如下列專利所介紹。 美國專利 5,234,868 號，專利名稱“Method for Determining Planarization Endpoint During Chemical-Mechanical Polishing”，揭露一四週以濠溝環繞的監 視結構。濠溝使硏磨除去物質的作業在監視結構區域進行速度較無濠溝環繞 的區域爲快。硏磨持續進行，直到監視結構的頂部暴露出來，並使得金屬圖 案上方的平坦化絕緣層不再爲濠溝所環繞。監視結構的頂部是否已暴露出來 是用目測來決定，或者利用電性偵測，以決定金屬監視結構的頂部與硏磨墊 間是否有電性聯結。 美國專利 5,240,552 號，專利名稱 “Chemical Mechanical Planarization (CMP) of a Semiconductor Waiter Using Acoustical Waves for In-Situ End Point Detection”，掲^^ CMP製程中對晶片發射聲波，並分析反射回來的聲波， 以控制平坦化製程。 美國專利 5,308,438 號，專利名稱 “Endpoint Detection Apparatus and Method for Chemical/Mechanical Polishing”，揭露一端點偵測的方法。該方法 監測旋轉基底馬達在一預設之轉速所須之功率。除去一難以硏磨之層後，維 持旋轉基底馬達在一固定的旋轉速度下’所須之功率會明顯下降，因此可以 測知硏磨已達端點。 美國專利 5,337,015 號，專利名稱 “In-Situ Eendpoint Detection Method and Apparatus for Chemical-Mechanical Polishing Using Low Amplitude Input Voltage ”，揭露利用硏磨墊內建之電極’ 一高頻、低壓訊號，以及一偵測裝置’以量 測硏磨中之介電層的厚度。 美國專利 5,413,941 號，專利名稱 “Optical End Point Detection Methods in Semiconductor Planarizing Polishing Processes” ’ 揭露一硏磨之端點偵測方法。 此方法用雷射光撞擊硏磨中之基底’並量測反射回來的雷射光。利用反射光 國家標準（〇!^)八4規格（210/ 297公釐） ----------装------訂------k -: i * - (請先閲讀#·面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印裝 311243 五、發明説明（3 ) 的強度來衡量硏磨表面的平坦度。 美國專利 5,1%，353 號，專利名稱 “Method for Controlling a Semiconductor (CMP) Processes by Measuring a Surface Temperature and Developing a Thermal Image of the Wafer”，揭露利用紅外輻射偵測來測量硏磨製程中半導體晶片表 面的溫度。硏磨製程中晶片表面溫度的突然變化，可用來偵測硏磨的端點。 本發明爲一創新的裝置及方法，可以在化學/機械平坦化(CMP)過程 中，不須將物件自硏磨裝置取下，就能即時地偵測出硏磨所除去的厚度。 發明簡述 本發明的目的之一是要提供一個基底表面的化學/機械平坦化（CMP)的 改良製程，藉著偵測硏磨製程的溫度與時間的相對變化，並以硏磨溫度變化 對硏磨時間曲線作積分，求得沉積層被磨除的厚度。 本發明的另外一個目的是要提供一個化學/機械平坦化（CMP)的改良製 程，藉著偵測硏磨墊溫度與時間的相對變化，並以硏磨墊溫度變化對硏磨時 間曲線作積分，即時地計算出沉積層被磨除的厚度。 本發明更進一步的目的是要提供一個在化學/機械平坦化(CMP)的製程 中，藉著偵測基底上多數個位置的溫度，並以各個位置的溫度相對於硏磨時 間的變化曲線作積分’計算出沉積層被磨除的厚度，即時地監測硏磨製程的 均勻度。 在本發明的第一個說明實施例裡，實施本發明的裝置包含了：一個晶片 承載裝置以及一個化學/機械平坦化（CMP)半導體晶片的旋轉硏磨平台，一 個旋轉硏磨墊，一個控制化學/機械硏磨溶液溫度的裝置，一個將化學/機 械硏磨溶液注入硏磨墊的裝置’一個監測硏磨墊溫度的紅外線溫度偵測裝 置，一個將硏磨墊溫度與硏磨時間的相對變化儲存於電腦記憶體恥裝置，一 個儲存CMP化學特性與金屬圖案密度的積分係數的裝置，以及一個應用上述 儲存的積分係數，求得上述溫度與時間相對變化相對於時間的積分’以計算 出沉積層已被磨除的厚度的裝置。 在本發明的第二個說明實施例裡，實施本發明的裝置包含了 ：—個晶片 適用中國國家標隼（CNS ) Λ4規格（210X 297公釐) ~ ~ -Γ- I— n I. - I----'*衣 I I -·. , (請先閱讀背^之-意事項再填寫本頁) 、ys^ 11243 at --- B7 V. Description of the invention (I) Background of the invention (1) Scope of the invention The present invention relates to a method and device for detecting the thickness of the deposited layer during the chemical / mechanical grinding process. Especially in the CMP process, the thickness removed by the polishing can be detected immediately without removing the wafer from the polishing device. (2) Related technology Chemical / mechanical grinding (CMP) has been developed for a long time, and is used to grind the deposited layer deposited on the semiconductor substrate to smooth the surface layout of the deposited layer. When metal wires are formed on the surface of the substrate containing the component wiring, a rough sugar surface layout is obtained. These metal wires are used to connect discrete components, thus forming an integrated circuit. The metal wires must be further insulated from the next layer of wires by the deposited film of insulating material, and the holes formed between the insulating layers provide electrical contact between the continuous conductive layers. Since it is difficult to photoetch images or patterns on rough surfaces, we hope that in such a wiring process, the surface of the insulating layer can have a flat surface layout. CMP can also be used to remove deposits of different materials on semiconductor substrates. For example, after forming a hole in the dielectric layer, a metal layer is deposited in a carpet, and then CMP can be used to planarize the metal plug. I ------- 一 --- Λ-- f-'-* (Please read and read the back £ ^ Notes before filling out this page) Briefly, The CMP process is to fix a thin and flat semiconductor wafer under controlled chemistry, pressure, and temperature conditions so that it faces a wet grinding surface and rotate it. The grinding material is a chemical solution containing alumina or silica. In addition, the chemical solution also contains some specific chemicals that etch the surface of the wafer during the CMP process. This method of combining mechanical and chemical to remove substances in the grinding process makes the grinding surface have excellent flatness. In this process, it is important to remove enough material to make the surface smooth, but it will not remove the underlying material excessively; therefore, the thickness of the abrasion must be detected in the grinding process, or the detection The thickness of the material left on the substrate. In the past, the method of detecting the thickness of the grinding was to interrupt the CMP process, remove the wafer from the grinding device, and actually inspect the wafer surface to determine the thickness of the film, or include the layout of the inspection wafer surface. This approach not only requires an additional wafer cleaning step, which is labor-intensive inspection and measurement, but also reduces the capacity of the grinding device. If the wafer does not meet the specific specifications, the wafer must be returned to the grinding paper. The paper standard is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). The A7 • B7 is printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. (1) Set for further grinding. As a result of the inspection, if it is found that too much material has been removed, then the wafer also does not meet the specifications and falls below the standard. This method of detecting endpoints and grinding thickness is not only time-consuming and 'costly' but also unreliable. Therefore, people have developed many improved methods for detecting the end point and thickness of the grinding in the CMP process, as described in the following patents. US Patent No. 5,234,868, patent name "Method for Determining Planarization Endpoint During Chemical-Mechanical Polishing", discloses a monitoring structure surrounded by a trench. The moat makes the grinding and removal of materials faster in the monitoring structure area than in the area without the moat. Grinding continues until the top of the monitoring structure is exposed, and the planarized insulating layer above the metal pattern is no longer surrounded by the trench. Whether the top of the monitoring structure has been exposed is determined by visual inspection, or electrical detection is used to determine whether there is an electrical connection between the top of the metal monitoring structure and the grinding pad. U.S. Patent No. 5,240,552, patent name "Chemical Mechanical Planarization (CMP) of a Semiconductor Waiter Using Acoustical Waves for In-Situ End Point Detection", ^^ The CMP process emits sound waves to the chip, and analyzes the reflected sound waves to control Flatten the process. US Patent No. 5,308,438, patent name "Endpoint Detection Apparatus and Method for Chemical / Mechanical Polishing", discloses a method of endpoint detection. This method monitors the power required for a rotating base motor at a preset speed. After removing a layer that is difficult to grind, the power required to maintain the rotating base motor at a fixed rotational speed will be significantly reduced, so it can be measured that the grinding has reached the end point. US Patent No. 5,337,015, patent name "In-Situ Eendpoint Detection Method and Apparatus for Chemical-Mechanical Polishing Using Low Amplitude Input Voltage", which discloses the use of electrodes built into the grinding pad 'a high-frequency, low-voltage signal and a detection device 'To measure the thickness of the dielectric layer in grinding. U.S. Patent No. 5,413,941, the patent name "Optical End Point Detection Methods in Semiconductor Planarizing Polishing Processes" ’discloses a polished endpoint detection method. This method uses laser light to strike the substrate under grinding and measures the reflected laser light. Use reflected light national standard (〇! ^) 84 specifications (210/297 mm) ---------- install ------ order ------ k-: i *- (Please read the notes of # · 面面 before filling out this page) Printed 311243 by the Employees Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. The strength of the invention description (3) to measure the flatness of the abraded surface. US Patent 5,1%, No. 353, patent name "Method for Controlling a Semiconductor (CMP) Processes by Measuring a Surface Temperature and Developing a Thermal Image of the Wafer", which discloses the use of infrared radiation detection to measure the semiconductor in the grinding process The temperature of the wafer surface. The sudden change of the wafer surface temperature during the grinding process can be used to detect the end point of the grinding. The present invention is an innovative device and method that can detect the thickness removed by the grinding in real time without removing the object from the grinding device during the chemical / mechanical planarization (CMP) process. SUMMARY OF THE INVENTION One of the objectives of the present invention is to provide an improved process of chemical / mechanical planarization (CMP) on the surface of a substrate. By detecting the relative change of temperature and time in the grinding process, Integrate the grinding time curve to obtain the thickness of the deposited layer. Another object of the present invention is to provide an improved chemical / mechanical planarization (CMP) process by detecting the relative change of the temperature and time of the polishing pad and integrating the temperature change of the polishing pad with the polishing time curve , Calculate the thickness of the deposited layer in real time. A further object of the present invention is to provide a chemical / mechanical planarization (CMP) process by detecting the temperature at a plurality of locations on the substrate and using the temperature at each location with respect to the grinding time Integral 'calculates the thickness of the deposited layer, and monitors the uniformity of the grinding process in real time. In the first illustrative embodiment of the present invention, the device for implementing the present invention includes: a wafer carrier and a rotating / grinding platform for chemical / mechanical planarization (CMP) semiconductor wafers, a rotating polishing pad, and a control A chemical / mechanical polishing solution temperature device, a device that injects chemical / mechanical polishing solution into the polishing pad, an infrared temperature detection device that monitors the temperature of the polishing pad, and a relative temperature between the polishing pad temperature and the polishing time The change is stored in a computer memory device, a device that stores the integration coefficient of CMP chemistry and metal pattern density, and an application of the stored integration coefficient to obtain the integral of the relative change of temperature and time with respect to time 'to calculate The thickness of the deposited layer has been removed by the device. In the second illustrative embodiment of the present invention, the device for implementing the present invention includes:-a wafer suitable for China National Standard Falcon (CNS) Λ4 specification (210X 297 mm) ~ ~ -Γ- I-n I.- I ---- '* Cloth II-·., (Please read the back ^-Issues before filling out this page), ys
五、發明説明（z/ ) 承載裝置以及一個化學/機械平坦化（CMP)半導體晶片的旋轉硏磨平台，一 個旋轉硏磨墊，一個控制化學/機械硏磨溶液溫度的裝置，一個將化學/機 械硏磨溶液注入硏磨墊的裝置，一個在半導體基底上多數個位置監測半導體 基底溫度的裝置，一個將上述每一個位置的溫度與硏磨時間的相對變化的資 料儲存於電腦記憶體的裝置，一個儲存CMP化學特性與金屬圖案密度的積分 係數的裝置，以及一個應用上述儲存的積分係數，求得上述每一個位置的溫 度與時間相對變化相對於時間的積分，以計算出沉積層已被磨除的厚度的裝 置。 圖式說明 本發明的目的及其他優點可由較佳實施例及附圖得到充份說明。附圖包 括： 圖1Λ所示爲彳艮據本發明的方法所使用的硏磨裝置的剖面圖。 圖1B爲圖1A之裝置的俯視圖。 圖2A的剖面圖顯示一晶片承載裝置上有多數個內建的溫度測量裝置。 圖2B爲圖2A的晶片承載裝置的俯視圖。 圖3 -圖4的剖面圖顯示一半導體基底上複合介電層表面的平坦化。 圖5顯示利用化學/機械硏磨法以平坦化半導體基底上一複合介電層表 面時，紅外線所偵測到相對於時間的硏磨墊溫度變化。 圖ό所示爲相對於時間，硏磨墊溫度變化的曲線，以及硏磨墊的溫度變 化與時間的積分，得到上述曲線下的區域面積。 '、圖7顯示應用儲存於電腦記憶體的各個CMP積分係數’圖案密度係 數，計算出被磨除的厚度。 圖8所示爲被磨除的厚度，這些厚度係得自硏磨墊溫度隨硏磨時間變化 的積分，並代入各別的CMP化學特性積分係數，以及圖案密度的積分係 數。 顯示利用化學/機械硏磨法以平坦化氧化政層裡之鎢聯結栓時，紅外線所偵 測到的硏磨墊溫度，相對於時間的變化，並標不出理想的端點。 本紙張又度逋用中國國家標隼（CNS ) A4規格（210x297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部t夬搮準局員工消費合作社印製 A7 A7 經濟部中央榡準局負Η消費合作社印製 五、發明説明（J ) 籃佳實施例 以下將描述利用本發明所改良的化學/機械硏磨(CMP)裝置及方法，以 平坦化一半導體基體的表面。本發明的裝置及方法可在CMP製程中即時偵測 出一沉積層已被磨除的厚度，而且不必將晶片自硏磨裝置取下。這個方法可 以應用在平坦化一半導體元件上或半導體佈線圖案上的絕緣層或絕緣層表 面。這些絕緣層可以是利用化學氣相沉積法(CVD)，低壓化學氣相沉積法 (LPCVD)，或電漿輔助化學氣相沉積法(PE-CVD)所沉積的氧化砂或氮化砂絕 緣層，也可以是利用自旋塗佈再加以回流所沉積的氧化層。 圖1A及1B爲本發明所使用的化學/機械平坦化（CMP)裝置的示意 圖。圖1A所示爲CMP裝置（10)的剖面圖。此CMP裝置（10)包括一個晶片 承載裝置（11)，用來固定住一半導體晶片（12)。晶片承載裝置（11)是由驅動 馬達（1句所驅動，以A1軸爲中心，沿箭頭〇3)所指示的方向不斷旋轉，並 依箭頭（15)所指示的方向施力於半導體晶片（12)上。CMP裝置（10)還包括 一個硏磨平台（I6)。硏磨平台（I6)是由驅動馬達（I8)所驅動，以A2軸爲中 心，沿箭頭（Π)所指示的方向不斷旋轉。硏磨平台上有一材質爲吹塑聚安酯 之類的硏磨墊（19)。硏磨溶液則爲一種硏磨劑，像是砍石或鋁氧粉硏磨粒子 懸浮於基本溶液或酸液裡。硏磨溶液存放在一有雕控制的儲存槽(21)裡。 透過導管(20),硏磨溶液注入到硏磨墊（19)上。另外架設一個紅外輻射線偵 測裝置(22) ’用來偵測由區域(23)(圖上標示爲X)所放射之紅外輻射線。圖 1B顯示區域（23)是在硏磨墊（19)上，循一環形帶狀區域（24)而成。這是因 爲硏磨墊（19)不斷地在旋轉，而區域(23)是位在半導體晶片（I2)與硏磨墊 (19)旋轉時的磨擦區域內。一個電腦記憶體(25)儲存CMP製程中，相對於硏 磨時間，硏磨墊的溫度變化9在電腦記憶體(25)裡還儲存了針對‘各別的CMP 化學特性及圖案密度的積分係數(26)。 本發明的第二個實施例揭露的裝置如圖2A、2B所示，爲一個可以偵測半 導體基底上多數個位置的溫度變化的裝置。圖2A裡的晶片承載裝置（3〇)具 有多數個內建的溫度感測器CHA) ' plB)、（31C)、（31D)、及plE)。這個實 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -7- (請先閱讀背面之注意事項再填寫本頁) 訂 A7 B7 熱能進入 的速率 — 熱能散發 的速率 + 熱能產生 的速率 五、發明説明（ 施例以5個溫度感測器爲例，加以說明。但其實溫度感測器的數量及位置可 視製程的實際需要，加以調整。溫度感測器可以是熱藕裝置，或螢光 (FLURO-OPTIC)溫度感測器，或紅外線溫度測量計等。溫度感測器(31A)〜 (31E)的位置安排必須要能在不同的位置偵測到半導體基底(32)背面的溫度。 圖2A及俯視圖2B所示爲5個溫度感測器位置安排的例子。電腦記憶體(33) 儲存了在CMP製程中，相對於硏磨時間，每一個位置的溫度變化，以及各別 的CMP化學特性及半導體基底上（32)圖案密度的積分係數(34)。 以下將詳細描述由硏磨介面所測得的溫度變化，來計算出硏磨層已被磨除 的厚度。在第一階的估算，硏磨介面的溫度變化是由硏磨介面的熱傳導所 致，如下所示： 熱傳導 ®@ ©0 溫度變化_ _ **繼咖 偏匕_ 〇 I I 裝-- - . (請先閱讀背νέ·之决意事項再填寫本頁) 經濟部中夬榡準局員工消費合作枉印製 Q = ΛΔΤ1，其中 △卜溫度變化 Λ =熱容量 Q =機械熱通量+化學熱通量，因此Q = Qm + Qc 如果 QM + Qc = (1 + δ) Qc Qc = R χ Hc，其中 R =硏磨溶液與硏磨層的反應速率，而 Hc =化學反應的潛熱. R =化學反應速率=，而 dt k爲反應速率常數 #爲在&時間內反應的硏磨厚度 訂 泉 f本 >張尺度適用中國國家樣準（CNS) μ規格（2]0>< 297公釐） 一 一 311243 A7 B7 五、發明説明（7) Q = (1 + 6) Qc = (1 + δ) k— Ξ ΜΓ dt 因此 =々△Τ'，並且 S = M77 d，而 dt dt 乂爲比例常數，所以 t 1 t L = j(hAT/ A)dt = ^-jATdt 0 ^ 0 因此磨除的厚度與溫度變化對時間的積分成一比例。 以下將以一個利用CMP來平坦化沉積於一半導體基底上的複合介電層 的爲例，說明本發明即時偵測已磨除的厚度的方法。圖3、4的剖面圖顯示一 半導體晶片的化學/機械平坦化(CMP)。該半導體晶片包含了一個金屬化的 MOSFET 元件。MOSFET 元件上並沉積了一 PE-TEOS/SOG/PE-TEOS 複合介 電層。PE-TEOS爲利用電漿輔助沉積法沉積四乙氧基矽甲烷所形成的氧化 砂，爲半導體業常用的絕緣物質。SOG爲自旋塗佈氧化層，也是半導體業常 用的材料。一個如圖3所示典型的NFET (N型場效電晶體）元件，包含了— 經濟部中央標準局員工消費合作社印製 1^. I · 装 II 訂 ** · (請先閱讀背面之注意事項再填寫本頁)V. Description of the invention (z /) Carrier and a rotating / grinding platform for chemical / mechanical planarization (CMP) semiconductor wafers, a rotating polishing pad, a device for controlling the temperature of the chemical / mechanical polishing solution, a chemical / mechanical polishing solution A device for injecting a mechanical polishing solution into the polishing pad, a device for monitoring the temperature of the semiconductor substrate at a plurality of positions on the semiconductor substrate, and a device for storing the data of the relative change of the temperature at each position and the polishing time in the computer memory , An apparatus for storing the integration coefficient of CMP chemical characteristics and metal pattern density, and an application of the stored integration coefficient to obtain the integral of the relative change of temperature and time with respect to time at each of the above positions to calculate the deposited layer has been Thickness of the device. BRIEF DESCRIPTION OF THE DRAWINGS The objects and other advantages of the present invention can be fully explained by the preferred embodiments and the accompanying drawings. The drawings include: FIG. 1Λ shows a cross-sectional view of the grinding device used by the method according to the invention. FIG. 1B is a top view of the device of FIG. 1A. The cross-sectional view of FIG. 2A shows that there are many built-in temperature measuring devices on a chip carrier. 2B is a top view of the wafer carrier of FIG. 2A. 3 to 4 are cross-sectional views showing the planarization of the surface of the composite dielectric layer on a semiconductor substrate. Fig. 5 shows the temperature change of the polishing pad with respect to time detected by infrared rays when using a chemical / mechanical polishing method to planarize the surface of a composite dielectric layer on a semiconductor substrate. Fig. 6 shows the curve of the temperature change of the grinding pad with respect to time, and the integral of the temperature change of the grinding pad and time to obtain the area under the above curve. 'Figure 7 shows the pattern density coefficient using each CMP integral coefficient stored in computer memory to calculate the thickness to be abraded. Figure 8 shows the thicknesses that are removed. These thicknesses are derived from the integral of the polishing pad temperature as a function of the polishing time, and are substituted into the individual CMP chemical characteristic integration coefficients and the pattern density integration coefficients. It shows that when using chemical / mechanical grinding method to flatten the tungsten coupling bolt in the oxide layer, the temperature of the grinding pad detected by infrared light changes with time, and the ideal endpoint cannot be marked. This paper also uses the Chinese National Standard Falcon (CNS) A4 specification (210x297mm) (please read the precautions on the back before filling out this page). Printed by the Ministry of Economic Affairs and the Ministry of Economy and Technology Co., Ltd. A7 A7 Printed by the Central Government Bureau of Consumer Affairs Co., Ltd. V. Description of the Invention (J) Preferred Embodiments of the Basket The following describes the chemical / mechanical polishing (CMP) device and method improved by the present invention to planarize the surface of a semiconductor substrate . The device and method of the present invention can instantly detect the thickness of a deposited layer that has been removed during the CMP process, and it is not necessary to remove the wafer from the polishing device. This method can be applied to planarize an insulating layer or a surface of an insulating layer on a semiconductor element or a semiconductor wiring pattern. These insulating layers may be oxide sand or nitride sand insulating layers deposited by chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), or plasma assisted chemical vapor deposition (PE-CVD) Or it can be an oxide layer deposited by spin coating followed by reflow. 1A and 1B are schematic views of chemical / mechanical planarization (CMP) devices used in the present invention. FIG. 1A shows a cross-sectional view of the CMP device (10). The CMP device (10) includes a wafer carrier (11) for holding a semiconductor wafer (12). The wafer carrying device (11) is driven by a drive motor (1 sentence, centered on the A1 axis, and continuously rotates in the direction indicated by arrow 〇3), and applies force to the semiconductor wafer in the direction indicated by arrow (15) ( 12) On. The CMP device (10) also includes an abrasion platform (I6). The grinding platform (I6) is driven by the drive motor (I8), with the A2 axis as the center, continuously rotating in the direction indicated by the arrow (Π). There is a grinding pad (19) made of blown polyurethane on the grinding platform. Grinding solution is a kind of grinding agent, such as stone or aluminum oxide grinding particles suspended in the basic solution or acid. The grinding solution is stored in a storage tank (21) with carving control. Through the catheter (20), the grinding solution is injected onto the grinding pad (19). In addition, an infrared radiation detection device (22) is installed to detect the infrared radiation emitted by the area (23) (marked as X in the figure). Fig. 1B shows that the area (23) is formed on the grinding pad (19), following an annular band-shaped area (24). This is because the polishing pad (19) is continuously rotating, and the area (23) is located in the friction area when the semiconductor wafer (I2) and the polishing pad (19) rotate. A computer memory (25) stores the temperature change of the polishing pad relative to the polishing time during the CMP process. 9 The computer memory (25) also stores the integral coefficients for each CMP chemical characteristic and pattern density. (26). The device disclosed in the second embodiment of the present invention, as shown in FIGS. 2A and 2B, is a device that can detect temperature changes at a plurality of positions on a semiconductor substrate. The wafer carrier device (30) in FIG. 2A has a plurality of built-in temperature sensors (CHA), (PLB), (31C), (31D), and plE). This real paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X 297mm) -7- (please read the precautions on the back before filling in this page) Order A7 B7 The rate of heat energy entry-the rate of heat dissipation + heat energy Production rate V. Description of the invention (The embodiment takes five temperature sensors as an example to illustrate. However, the number and position of temperature sensors can be adjusted according to the actual needs of the manufacturing process. The temperature sensor can be a thermal lotus Device, or fluorescent (FLURO-OPTIC) temperature sensor, or infrared temperature gauge, etc. The location of the temperature sensors (31A) ~ (31E) must be able to detect the semiconductor substrate (32 ) The temperature on the back. Figure 2A and top view 2B show an example of the arrangement of the five temperature sensors. The computer memory (33) stores the temperature change of each position in the CMP process, relative to the grinding time, As well as the individual CMP chemical properties and the integral coefficient (34) of the pattern density on the semiconductor substrate (32). The temperature change measured by the grinding interface will be described in detail below to calculate the thickness of the grinding layer that has been removed . In the first-order estimation, the temperature change of the grinding interface is caused by the heat conduction of the grinding interface, as shown below: Heat Conduction @@ 0 Temperature Change_ _ ** Following Coffee Bi__ 〇II Installation--. (Please read the decision matters before filling in this page) The Ministry of Economic Affairs of the Ministry of Economic Affairs of the People's Republic of China Employee Consumption Cooperation Printing Q = ΔΔΤ1, where △ Bu temperature change Λ = heat capacity Q = mechanical heat flux + chemical heat flux Q = Qm + Qc If QM + Qc = (1 + δ) Qc Qc = R χ Hc, where R = the reaction rate of the grinding solution and the grinding layer, and Hc = latent heat of the chemical reaction. R = chemical Reaction rate =, and dt k is the reaction rate constant. # Is the thickness of the grinding mill reacted within the & time. The scale is applied to the Zhang scale. The Chinese National Standard (CNS) μ specification (2) 0> < 297 (11) 311243 A7 B7 V. Description of the invention (7) Q = (1 + 6) Qc = (1 + δ) k— Ξ ΜΓ dt Therefore = 々 △ Τ ', and S = M77 d, and dt dt 乂Is a proportional constant, so t 1 t L = j (hAT / A) dt = ^ -jATdt 0 ^ 0 Therefore, the thickness of the abrasion is proportional to the integral of the temperature change with time. The following will take a An example of using CMP to planarize a composite dielectric layer deposited on a semiconductor substrate illustrates the method of real-time detection of the abraded thickness of the invention. The cross-sectional views of FIGS. 3 and 4 show the chemical / mechanical flatness of a semiconductor wafer CMP. The semiconductor wafer contains a metalized MOSFET element. A PE-TEOS / SOG / PE-TEOS composite dielectric layer was deposited on the MOSFET element. PE-TEOS is an oxide sand formed by depositing tetraethoxysilyl methane using plasma-assisted deposition method, and is an insulating substance commonly used in the semiconductor industry. SOG is a spin-coated oxide layer and is also a commonly used material in the semiconductor industry. A typical NFET (N-type field effect transistor) device as shown in Fig. 3, contains-printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 1 ^. I · Pack II Order ** · (Please read the note on the back first (Fill in this page again)
P型，晶格排列方式爲<1〇〇>之單晶矽半導體晶片（I2)，一厚的場氧化區域 (40)(圖2上標示爲FOX)，一複晶矽閘(41)，氧化閘(42)，源極/汲極區 (43)，側壁隔離區（44)，利用LPCVD (低壓化學氣相沉積法）沉積的氧化砂 層(45),及氮化矽層(46)，層與層間之聯結栓(47) ’導通聯結圖案(48)，第一 PE-TE0S 層(49)，S0G 層(50)，以及第二 ΙΈ-TEOS 層（51)。第一 pe-TEOS 層(49)是利用電漿輔助沉積法所沉積的四乙氧基矽甲烷，沉積溫度設定在大 約200 ~ 400 °C間，沉積厚度約介於2,000 ~ 5,0〇〇A間。S0G層（50)包含了 塗佈2 ~ 4層的自旋氧化層，接著再在250 ~ 450 °C的溫度下回流，使s〇G 層的厚度約達2,〇〇〇〜1〇,〇〇〇Α。第二PE-TE0S層（51)是利用電漿輔助沉積法 沉積的四乙氧基矽甲烷’沉積溫度設定在大約200 ~ 400°C間，沉積厚度約介 本紙張尺度適用中國國家標準（CNS > Λ4規格（210X297公釐） 一f 一 B7 五、發明説明（《） 於2,000 ~ 5,000A間。圖3所顯示的表面佈局（52)的平坦化是用圖1A及圖 1B所示的裝置，利用化學/機械硏磨法(CMP)所達成。圖4顯示硏磨後的介 電層的表面（53)相當平坦。 以下將詳細說明如何即時偵測出圖3裡的表面佈局（52)，在化學/機械 平坦化（CMP)製程中被磨除的厚度的方法。請參考圖1Λ及圖1B，溶液儲存 槽（21)裡硏磨溶液爲砂及NH4OH的水溶液。硏磨溶液溫度控制在大約10〜 3〇°C間，並透過導管(2〇)，注入硏磨墊（I9)之上，使硏磨墊（I9)達到飽合。 紅外輻射線偵測裝置(22)測量硏磨墊（19)之上區域(23)的溫度。半導體晶片 (12)是放置在硏磨裝置（1〇)上，以第二PE-TEOS層（51)面向硏磨墊（19)。 硏磨平台馬達（I8)的速度設定在大約1〇〜7〇 rpm。晶片承載裝置的驅動馬達 (I4)轉速也設定在大約10 ~ 7〇 rpm。晶片承載裝置（11)會施一1 ~ 10 psi的 壓力（I5)於晶片與硏磨墊間。在CMP的製程中，電腦記憶體(25)儲存硏磨 墊溫度隨著時間的變化資料。譬如，溫度測量裝置的電壓輸出透過一個標準 的IEEE-488介面及類比/數位轉換器與上述的電腦記憶體藕合。這個裝置可 以將市售的時間相對於電壓的資料庫內的資料轉換成溫度資料。電腦記憶體 (25)裡還儲存了針對各別的CMP化學特性及半導體基底（I2)上的圖案密度的 積分係數㈤。 經濟部中央標準局員工消費合作社印製 圖5顯示利用化學/機械硏磨法平坦化半導體晶片表面（52)時，紅外線 所偵測到的硏磨墊溫度隨時間所產生的變化。請參考圖3及圖5 ,由於硏磨墊 的纖維與硏磨溶液裡的硏磨粒子，以及PE-TEOS層，三者間的磨擦，開始硏 磨第二PE-TEOS層(51)時，硏磨墊的溫度上昇，如區段(60)所示。區段(61) 顯示硏磨PE-TEOS層時，硏磨墊的溫度相當穩定。當硏磨墊與SOG層（50) 接觸時，由於SOG層屬較不易硏磨的材料，硏磨墊的纖維與硏磨溶液裡的硏 磨粒子，以及硏磨表面三者間的磨擦增加，硏磨墊的溫度也因此而上昇，如 段（《)所示。最後硏磨墊的溫度上昇至一較高値後，平穩下來，如區段 (64)所示。這是由於硏磨墊的纖維與硏磨溶液裡的硏磨粒子，以及SOG層 本紙乐尺度適用中國國家標準（CNS ) Λ4規格（210 X 297公釐） -7勺一 A7 ' B7 五、發明説明（q ) (50) 間的磨擦較大所致。 在第一階的估算，相對於時間的變化，沉積層被磨除的厚度是利用電腦 求出硏磨墊溫度變化在硏磨時間區間內的積分，如圖6所示。陰影區域（70) 爲硏磨墊溫度變化在硏磨時間區間內的積分。在第一階的估算，區域（7〇)， 即硏磨墊溫度隨時間的變化曲線下的區域，也就是在時間Ρτ (71)時被磨除的 厚度。P-type, single crystal silicon semiconductor wafer (I2) with lattice arrangement of < 100〇 >, a thick field oxide region (40) (marked as FOX in FIG. 2), and a polycrystalline silicon gate (41 ), Oxide gate (42), source / drain region (43), sidewall isolation region (44), oxide sand layer (45) deposited by LPCVD (low pressure chemical vapor deposition), and silicon nitride layer (46 ), The layer-to-layer connection plug (47) 'conductive connection pattern (48), the first PE-TEOS layer (49), the SOG layer (50), and the second ΙΈ-TEOS layer (51). The first pe-TEOS layer (49) is tetraethoxysilyl methane deposited by plasma-assisted deposition. The deposition temperature is set at about 200 ~ 400 ° C, and the deposition thickness is about 2,000 ~ 5,000. Room A. The SOG layer (50) contains 2 to 4 spin oxide layers, followed by reflow at a temperature of 250 to 450 ° C, so that the thickness of the SOG layer is about 2,000 to 10,000. 〇〇〇Α. The second PE-TEOS layer (51) is tetraethoxysilyl methane deposited by plasma-assisted deposition method. The deposition temperature is set at about 200 ~ 400 ° C, and the deposition thickness is about the paper size. The Chinese national standard (CNS > Λ4 specification (210X297 mm) One f One B7 5. Description of the invention (<) Between 2,000 and 5,000 A. The flattening of the surface layout (52) shown in FIG. 3 is shown in FIGS. 1A and 1B The device is achieved by chemical / mechanical grinding (CMP). Figure 4 shows that the surface (53) of the dielectric layer after grinding is quite flat. The following will explain in detail how to detect the surface layout (52) in Figure 3 in real time ), The thickness of the grinding method in the chemical / mechanical planarization (CMP) process. Please refer to Figure 1Λ and Figure 1B, the grinding solution in the solution storage tank (21) is an aqueous solution of sand and NH4OH. Controlled at about 10 ~ 30 ° C, and injected into the polishing pad (I9) through the catheter (20) to make the polishing pad (I9) saturated. Measurement by infrared radiation detection device (22) The temperature of the region (23) above the polishing pad (19). The semiconductor wafer (12) is placed on the polishing device (10), Face the polishing pad (19) with the second PE-TEOS layer (51). The speed of the polishing table motor (I8) is set at about 10 to 70 rpm. The speed of the drive motor (I4) of the wafer carrier is also set at About 10 ~ 70 rpm. The wafer carrier (11) will apply a pressure of 1 ~ 10 psi (I5) between the wafer and the polishing pad. During the CMP process, the computer memory (25) stores the polishing pad temperature Data changes with time. For example, the voltage output of the temperature measurement device is coupled to the above-mentioned computer memory through a standard IEEE-488 interface and analog / digital converter. This device can compare the time of the market with the voltage. The data in the database is converted into temperature data. The computer memory (25) also stores the integration coefficient for each CMP chemical characteristic and the pattern density on the semiconductor substrate (I2). Employee Consumer Cooperative of the Central Bureau of Standards Printed Figure 5 shows the change of the temperature of the polishing pad detected by infrared rays with time when the surface of the semiconductor wafer (52) is flattened by chemical / mechanical polishing. Please refer to Figures 3 and 5 because of the polishing Mat Fiber and Grinding The grinding particles in the liquid, and the friction between the three layers of PE-TEOS, when the grinding of the second PE-TEOS layer (51) starts, the temperature of the grinding pad rises, as shown in section (60). Paragraph (61) shows that when grinding the PE-TEOS layer, the temperature of the grinding pad is quite stable. When the grinding pad is in contact with the SOG layer (50), since the SOG layer is a material that is not easy to wear, the fibers of the grinding pad The friction between the grinding particles in the grinding solution and the grinding surface increases, and the temperature of the grinding pad also rises as shown in paragraph (《). Finally, after the temperature of the grinding pad rises to a higher value, it stabilizes, as shown in section (64). This is due to the fibers of the grinding pad and the grinding particles in the grinding solution, and the SOG layer of the original paper music scale is applicable to the Chinese National Standard (CNS) Λ4 specifications (210 X 297 mm) -7 spoons A7 'B7 V. Invention Description (q) (50) due to greater friction. In the first-order estimation, the thickness of the deposited layer removed with respect to the change in time is calculated using a computer to integrate the temperature change of the polishing pad within the polishing time interval, as shown in Figure 6. The shaded area (70) is the integral of the temperature change of the grinding pad over the grinding time interval. In the first-order estimation, the area (70), that is, the area under the curve of the temperature of the polishing pad with time, that is, the thickness removed at time τ (71).
圖7顯示應用儲存在電腦記憶體裡，針對各別的CMP化特性及基底上的 圖案密度的積分係數，求出第二階的估算（8〇)被磨除的厚度。積分區域A (51) 須乘上係數αΐ。ίΠ是針對PE-TOS的硏磨化學特性。積分區域B (82)須 乘上係數ε及α2。ε是針對元件結構的圖案密度，而扣是針對SOG的硏 磨化學特性。積分區域C (82)須乘上係數α2。α2是針對SOO的硏磨化學特 性。沉積層磨除的厚度爲積分區域乘以積分係數的加總，如圖7的數學式 80，磨除厚度= Aai + Beai + C〇：2所示。 以下將討論4個包含複合介電層於聯結圖 上的半導體基底的硏磨實驗結果藉以進一步說 明本發明的方法。表1所列爲實驗參數： ------_---枯衣------ΐτ------i -· i . ---'-·-(請先閱讀背^之^-意事項再填寫本頁) 經濟部中央標準局員工消費合作社印裝 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） -((一 311243 Μ Β7 五、發明説明（丨心） 表ι 基底] W23 W19 W21 W20 ai 0.71 1 1 1.43 ε 0.5 1 1 1 α2 0.71 1 1 1.50 硏磨溶液- SS-12 SC112 SC112 SS-12 硏磨墊 堆疊式 堆疊式 堆疊式 堆疊式 底層 PE-SiH4 PE-TEOS PE-SiH4 PE-TE0S 第二層 SOG-4x S0G-2x S0G-2x SOG-2x 圖案 T50021 T50021 T50021 T50021 經濟部中央標準局員工消費合作社印裝 係數αΐ是針對硏磨溶液的化學特性、最底下的介電層、以及初始的佈局 或基底的平滑度。係數ε是針對圖案密度以及下層元件結構的表面佈局。係 數α2是針對硏磨溶液的硏磨化學特性、SOG第二層 '以及初始的佈局或 SOG第二層的平滑度。 基底W19爲一般nonninal的狀況，因此所有的係數爲1。基底W23與 其他基底相較，由於已塗佈4層S0G作爲第二層，因此初始的佈局較少。因 爲這樣，基底WM的ε係數=5，較其他基底的爲低。由於基底W21、W20 與基底W19有一樣的初始佈局，因此ε係數=1。由於基底W21與基底 W19有同樣的初始佈局，並且都是用硏磨溶液SC112，因此基底WW的 係數=1 ,扣係數=1。對氧化矽來說，由於硏磨溶液SS-12的CMP的硏磨 速率較硏磨溶液SCI 12爲高，同時考慮初始的佈局對CMP的硏磨速率的影 響，因此基底W20及W23的α係數必須反應上述因素。基底W20與基底 W19有同樣的初始佈局，；α係數則爲對氧化矽具較高CMP硏磨速率的硏 磨溶液SS-12，因此αΐ = 1.43，扣=1.50。基底W23與基底W19相較’其 初始的佈局較少，因此調整其基底W23的α係數，使W =0.71 ’ = (m。 圖8顯示上述實驗裡4個基底所磨除的介電層厚度。這些値是對硏磨墊 溫度的變化在時間區間內的積分，並針對各別的CMP硏磨化學特性及各個基 本紙乐尺度適用中國國家標準（CNS ) Λ4規格（2IOX 297公釐） (請先閲讀背面之注意事項再填寫本頁) 一 A7 B7 五、發明説明（丨I ) 底的圖案密度，代入適當的積分係數而得來。 上述說明僅爲範例，而非發明範圍。揭露本發明之較佳實施例，目的在 協助本行技藝之人實施本發明。任何變化或修改，如不悖離本發明之範疇及 精神，仍屬本發明之申請專利範圍。 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 一 1〕一Figure 7 shows that the application is stored in the computer memory, and the second-order estimate (80) of the thickness removed is obtained for each CMP characteristic and the integral coefficient of the pattern density on the substrate. The integral area A (51) must be multiplied by the coefficient α1. ίΠ is for the grinding chemistry of PE-TOS. The integral area B (82) must be multiplied by the coefficient ε and α2. ε refers to the pattern density of the element structure, and buckle refers to the grinding chemistry of SOG. The integral area C (82) must be multiplied by the coefficient α2. α2 is the grinding chemistry characteristic for SOO. The thickness of the deposited layer is the sum of the integral area multiplied by the integral coefficient, as shown in the mathematical formula 80 in Figure 7, the thickness of the removed layer = Aai + Beai + C〇: 2. In the following, the results of four grinding experiments on a semiconductor substrate including a composite dielectric layer on a connection pattern will be discussed to further illustrate the method of the present invention. Table 1 lists the experimental parameters: ------_--- Qiyi ------ lτ ------ i-· i. ---'- ·-(Please read the back first ^ 之 ^ -Please fill in this page again) The paper standard printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297mm)-((一 311243 Μ Β7 V. Invention description丨 Heart) Table ι Base] W23 W19 W21 W20 ai 0.71 1 1 1.43 ε 0.5 1 1 1 α2 0.71 1 1 1.50 Grinding Solution-SS-12 SC112 SC112 SS-12 Grinding Pad Stacked Stacked Stacked Stacked Bottom Layer PE-SiH4 PE-TEOS PE-SiH4 PE-TE0S second layer SOG-4x S0G-2x S0G-2x SOG-2x pattern T50021 T50021 T50021 T50021 printing coefficient αl of the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs is for the grinding solution Chemical properties, the lowest dielectric layer, and the initial layout or the smoothness of the substrate. The coefficient ε is for the pattern density and the surface layout of the underlying component structure. The coefficient α2 is for the grinding chemical properties of the grinding solution, SOG second Layer 'and the smoothness of the initial layout or the second layer of SOG. The substrate W19 is generally a nonninal condition, All the coefficients are 1. Compared with other substrates, the substrate W23 has 4 layers of SOG as the second layer, so the initial layout is less. Because of this, the ε coefficient of the substrate WM = 5, which is higher than that of other substrates. Low. Since the substrates W21 and W20 have the same initial layout as the substrate W19, the ε coefficient = 1. Since the substrates W21 and W19 have the same initial layout and both use the grinding solution SC112, the coefficient of the substrate WW = 1 , Buckling factor = 1. For silicon oxide, the polishing rate of the CMP of the polishing solution SS-12 is higher than that of the SCI 12 of the polishing solution, and the effect of the initial layout on the polishing rate of the CMP is considered, so the substrate The alpha coefficients of W20 and W23 must reflect the above factors. Substrate W20 has the same initial layout as substrate W19; the alpha coefficient is the polishing solution SS-12 with a higher CMP polishing rate for silicon oxide, so α1 = 1.43, Buckle = 1.50. Compared with the substrate W19, the initial layout of the substrate W23 is less, so adjust the α coefficient of the substrate W23, so that W = 0.71 '= (m. Figure 8 shows the four substrates in the above experiment. The thickness of the dielectric layer. These values are for the temperature of the polishing pad Change the integral in the time interval, and apply the Chinese National Standard (CNS) Λ4 specification (2IOX 297mm) for each CMP grinding chemical characteristic and each basic paper music standard (please read the notes on the back before filling in this Page) A7 B7 V. Description of the invention (丨 I) The bottom pattern density is obtained by substituting the appropriate integral coefficient. The above description is only an example, not the scope of the invention. The preferred embodiments of the present invention are disclosed to assist those skilled in the art to implement the present invention. Any changes or modifications that do not deviate from the scope and spirit of the present invention still belong to the scope of the present invention. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. This paper scale applies the Chinese National Standard (CNS) A4 specification (210X297mm).