CN103098206A - 具有偏移裸片叠层的多芯片封装及其制造方法 - Google Patents

具有偏移裸片叠层的多芯片封装及其制造方法 Download PDF

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Publication number
CN103098206A
CN103098206A CN2011800143724A CN201180014372A CN103098206A CN 103098206 A CN103098206 A CN 103098206A CN 2011800143724 A CN2011800143724 A CN 2011800143724A CN 201180014372 A CN201180014372 A CN 201180014372A CN 103098206 A CN103098206 A CN 103098206A
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nude film
group
substrate
pad
nude
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Chinese (zh)
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P·吉利厄姆
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Mosaid Technologies Inc
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Mosaid Technologies Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07554—Controlling the environment, e.g. atmosphere composition or temperature changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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  • Wire Bonding (AREA)
  • Semiconductor Memories (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
CN2011800143724A 2010-03-18 2011-03-08 具有偏移裸片叠层的多芯片封装及其制造方法 Pending CN103098206A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US31511110P 2010-03-18 2010-03-18
US61/315111 2010-03-18
PCT/CA2011/000253 WO2011113136A1 (en) 2010-03-18 2011-03-08 Multi-chip package with offset die stacking and method of making same

Publications (1)

Publication Number Publication Date
CN103098206A true CN103098206A (zh) 2013-05-08

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Country Link
US (2) US8502368B2 (https=)
EP (1) EP2548226A4 (https=)
JP (1) JP5579879B2 (https=)
KR (1) KR20130007602A (https=)
CN (1) CN103098206A (https=)
WO (1) WO2011113136A1 (https=)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108389849A (zh) * 2018-02-05 2018-08-10 奥肯思（北京）科技有限公司 一种交错堆叠存储器封装
CN110880493A (zh) * 2018-09-06 2020-03-13 爱思开海力士有限公司 半导体封装件
CN113394200A (zh) * 2020-03-13 2021-09-14 铠侠股份有限公司 半导体装置
CN119208284A (zh) * 2023-06-14 2024-12-27 长鑫存储技术有限公司 一种半导体封装结构

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101909203B1 (ko) * 2011-07-21 2018-10-17 삼성전자 주식회사 멀티-채널 패키지 및 그 패키지를 포함한 전자 시스템
US20150333041A1 (en) * 2012-12-25 2015-11-19 Ps5 Luxco S.A.R.L. Semiconductor device and manufacturing method therefor
JP2014138035A (ja) * 2013-01-15 2014-07-28 Toshiba Corp 半導体装置
KR102110984B1 (ko) 2013-03-04 2020-05-14 삼성전자주식회사 적층형 반도체 패키지
KR102001880B1 (ko) * 2013-06-11 2019-07-19 에스케이하이닉스 주식회사 적층 패키지 및 제조 방법
GB2518476B (en) 2013-09-20 2015-11-04 Silicon Lab Inc Multi-chip modules having stacked television demodulators
WO2017095401A1 (en) 2015-12-02 2017-06-08 Intel Corporation Die stack with cascade and vertical connections
KR102579877B1 (ko) * 2016-11-22 2023-09-18 삼성전자주식회사 반도체 패키지 및 그 제조 방법
JP6761180B2 (ja) * 2016-12-28 2020-09-23 株式会社バッファロー 半導体装置
US11139283B2 (en) * 2018-12-22 2021-10-05 Xcelsis Corporation Abstracted NAND logic in stacks
JP2021064780A (ja) * 2019-10-11 2021-04-22 メレキシス テクノロジーズ エス エーＭｅｌｅｘｉｓ Ｔｅｃｈｎｏｌｏｇｉｅｓ ＳＡ 積層ダイアセンブリ
CN112038280B (zh) * 2020-07-24 2022-07-29 华为技术有限公司 一种芯片转移方法、电子设备
KR102847506B1 (ko) * 2020-07-29 2025-08-20 에스케이하이닉스 주식회사 다이 위치 검사부들을 포함하는 반도체 패키지
US12136607B2 (en) * 2021-09-01 2024-11-05 Micron Technology, Inc. Semiconductor devices including stacked dies with interleaved wire bonds and associated systems and methods
KR20230106410A (ko) * 2022-01-06 2023-07-13 삼성전자주식회사 반도체 패키지
KR20230143497A (ko) * 2022-04-05 2023-10-12 삼성전자주식회사 반도체 패키지 및 그의 제조 방법

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030183917A1 (en) * 2002-02-07 2003-10-02 Macronix International Co., Ltd. Stacked semiconductor packaging device
US20070117266A1 (en) * 1996-02-20 2007-05-24 Ball Michael B Method of fabricating a multi-die semiconductor package assembly
US20080171405A1 (en) * 2007-01-15 2008-07-17 Jae Hak Yee Integrated circuit package system with leads having multiple sides exposed
CN101364593A (zh) * 2007-08-09 2009-02-11 南茂科技股份有限公司 导线架中具有多段式汇流条的交错偏移堆叠封装结构
US20090096075A1 (en) * 2007-10-16 2009-04-16 Joh Cheol Ho Stacked semiconductor package that prevents damage to semiconductor chip when wire-bonding and method for manufacturing the same

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5886412A (en) * 1995-08-16 1999-03-23 Micron Technology, Inc. Angularly offset and recessed stacked die multichip device
US6369448B1 (en) 2000-01-21 2002-04-09 Lsi Logic Corporation Vertically integrated flip chip semiconductor package
JP3768761B2 (ja) 2000-01-31 2006-04-19 株式会社日立製作所 半導体装置およびその製造方法
US6900528B2 (en) * 2001-06-21 2005-05-31 Micron Technology, Inc. Stacked mass storage flash memory package
JP4387076B2 (ja) * 2001-10-18 2009-12-16 株式会社ルネサステクノロジ 半導体装置
US20040021230A1 (en) * 2002-08-05 2004-02-05 Macronix International Co., Ltd. Ultra thin stacking packaging device
JP3908146B2 (ja) * 2002-10-28 2007-04-25 シャープ株式会社 半導体装置及び積層型半導体装置
JP2004158536A (ja) * 2002-11-05 2004-06-03 Fujitsu Ltd 半導体装置及び半導体装置の製造方法
US6930378B1 (en) * 2003-11-10 2005-08-16 Amkor Technology, Inc. Stacked semiconductor die assembly having at least one support
DE102004049356B4 (de) * 2004-10-08 2006-06-29 Infineon Technologies Ag Halbleitermodul mit einem internen Halbleiterchipstapel und Verfahren zur Herstellung desselben
US20060087013A1 (en) * 2004-10-21 2006-04-27 Etron Technology, Inc. Stacked multiple integrated circuit die package assembly
US8710675B2 (en) * 2006-02-21 2014-04-29 Stats Chippac Ltd. Integrated circuit package system with bonding lands
US7498667B2 (en) * 2006-04-18 2009-03-03 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
US7420269B2 (en) * 2006-04-18 2008-09-02 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
JP5207336B2 (ja) * 2006-06-05 2013-06-12 ルネサスエレクトロニクス株式会社 半導体装置
US8138591B2 (en) * 2006-09-23 2012-03-20 Stats Chippac Ltd Integrated circuit package system with stacked die
JP4921937B2 (ja) 2006-11-24 2012-04-25 株式会社東芝 半導体集積回路
US8242607B2 (en) * 2006-12-20 2012-08-14 Stats Chippac Ltd. Integrated circuit package system with offset stacked die and method of manufacture thereof
JP4913640B2 (ja) * 2007-03-19 2012-04-11 ルネサスエレクトロニクス株式会社 半導体装置
US8299626B2 (en) * 2007-08-16 2012-10-30 Tessera, Inc. Microelectronic package
US7906853B2 (en) 2007-09-06 2011-03-15 Micron Technology, Inc. Package structure for multiple die stack
JP5529371B2 (ja) * 2007-10-16 2014-06-25 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びその製造方法
US7952183B2 (en) * 2007-10-29 2011-05-31 Kabushiki Kaisha Toshiba High capacity memory with stacked layers
JP5150242B2 (ja) * 2007-12-27 2013-02-20 株式会社東芝 半導体記憶装置
JP5150243B2 (ja) * 2007-12-27 2013-02-20 株式会社東芝 半導体記憶装置
US8004071B2 (en) 2007-12-27 2011-08-23 Kabushiki Kaisha Toshiba Semiconductor memory device
KR20100049283A (ko) * 2008-11-03 2010-05-12 삼성전자주식회사 반도체 패키지 및 그 제조 방법
JP5126002B2 (ja) * 2008-11-11 2013-01-23 セイコーエプソン株式会社 半導体装置及び半導体装置の製造方法
KR101013563B1 (ko) * 2009-02-25 2011-02-14 주식회사 하이닉스반도체 스택 패키지
US8106498B2 (en) * 2009-03-05 2012-01-31 Stats Chippac Ltd. Integrated circuit packaging system with a dual board-on-chip structure and method of manufacture thereof
JP2010245412A (ja) * 2009-04-09 2010-10-28 Renesas Electronics Corp 半導体集積回路装置の製造方法
KR20100121231A (ko) * 2009-05-08 2010-11-17 삼성전자주식회사 회로패턴 들뜸 현상을 억제하는 패키지 온 패키지 및 그 제조방법
JP5426966B2 (ja) * 2009-08-28 2014-02-26 学校法人慶應義塾 半導体集積回路装置
JP5635759B2 (ja) * 2009-10-15 2014-12-03 学校法人慶應義塾 積層半導体集積回路装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070117266A1 (en) * 1996-02-20 2007-05-24 Ball Michael B Method of fabricating a multi-die semiconductor package assembly
US20030183917A1 (en) * 2002-02-07 2003-10-02 Macronix International Co., Ltd. Stacked semiconductor packaging device
US20080171405A1 (en) * 2007-01-15 2008-07-17 Jae Hak Yee Integrated circuit package system with leads having multiple sides exposed
CN101364593A (zh) * 2007-08-09 2009-02-11 南茂科技股份有限公司 导线架中具有多段式汇流条的交错偏移堆叠封装结构
US20090096075A1 (en) * 2007-10-16 2009-04-16 Joh Cheol Ho Stacked semiconductor package that prevents damage to semiconductor chip when wire-bonding and method for manufacturing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108389849A (zh) * 2018-02-05 2018-08-10 奥肯思（北京）科技有限公司 一种交错堆叠存储器封装
CN110880493A (zh) * 2018-09-06 2020-03-13 爱思开海力士有限公司 半导体封装件
CN113394200A (zh) * 2020-03-13 2021-09-14 铠侠股份有限公司 半导体装置
CN119208284A (zh) * 2023-06-14 2024-12-27 长鑫存储技术有限公司 一种半导体封装结构

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JP5579879B2 (ja) 2014-08-27
US8502368B2 (en) 2013-08-06
US20120056335A1 (en) 2012-03-08
JP2013522887A (ja) 2013-06-13
KR20130007602A (ko) 2013-01-18
WO2011113136A1 (en) 2011-09-22
EP2548226A1 (en) 2013-01-23
US9177863B2 (en) 2015-11-03
EP2548226A4 (en) 2013-11-20
US20130309810A1 (en) 2013-11-21

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