CN101322246B - 层叠式微电子封装 - Google Patents

层叠式微电子封装 Download PDF

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Publication number
CN101322246B
CN101322246B CN2006800452483A CN200680045248A CN101322246B CN 101322246 B CN101322246 B CN 101322246B CN 2006800452483 A CN2006800452483 A CN 2006800452483A CN 200680045248 A CN200680045248 A CN 200680045248A CN 101322246 B CN101322246 B CN 101322246B
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microelectronic element
substrate
contact
edge
micromodule
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CN101322246A (zh
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I·穆罕默德
B·哈巴
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Adeia Semiconductor Solutions LLC
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Tessera LLC
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Abstract

一种微电子组件包括第一微电子元件和第二微电子元件(12，14)。每一个微电子元件(12，14)具有相对的第一表面(14，22)和第二表面(18，24)以及作为该表面的边界的边缘。第一微电子元件(12)置于在第二微电子元件(14)上，且第一微电子元件(12)的所述第二表面(18)面向第二微电子元件(14)的第一表面(22)。第一微电子元件(12)较佳地延伸超过第二微电子元件(14)的至少一个边缘，且第二微电子元件(14)较佳地延伸超过第一微电子元件(12)的至少一个边缘。

Description

层叠式微电子封装
交叉引用
本申请要求2005年12月1日提交的美国专利申请第11/291,398号的优先权，其内容通过引用结合于此。
发明背景
本发明涉及微电子封装，尤其涉及诸如其中多个半导体元件中一个层叠在另一个的顶部的半导体芯片封装之类的微电子封装。
半导体芯片通常作为单个、经预先封装的单元来提供。在某些单元设计中，半导体芯片被安装在衬底或芯片载体上，它们又被安装在诸如印刷线路板之类的电路板上。线路板通常具有沿平行于线路板的表面的水平方向延伸、一般被称为迹线的电导体以及连接到迹线的端子或其它导电元件。封装的芯片被安装成使得设置在每一个单元上的端子电连接至线路板的触点焊盘或端子。在该常规的配置中，理论上的最小线路板面积必需至少等于各个预先封装的单元的所有端子支撑表面的合计面积。然而，在实践中，电路板必需多少大于该面积。因此，通常会产生各种空间问题。另外，这些构造中的迹线必需具有相当大的长度和阻抗，使得需要明显的时间用于信号沿迹线传播，且电路的运算速度受到限制。
为了消除这些缺点，通常采用在一个共用的封装中相互“层叠”的单元。本质上，在这种类型的设计中，封装自身具有连接到线路板的端子的垂直延伸的导体。封装中的各个芯片又连接到这些垂直延伸的导体上。因为芯片的厚度显著小于其水平尺寸，所以内部导体可比在线路板上以常规配置连接相同数量的芯片所需的迹线要短。这种层叠式封装设计的例子在美国专利第5,861,666号，第5,198,888号，第4,956,694号，第6,072,233号和第6,268,649号以及美国专利公开第2003/010711801号中进行了教示，这些专利的内容通过引用结合于此。通常垂直延伸的导体是实心球等形式，它们将预先封装的单元互相连接并连接至线路板。
尽管在层叠式封装的开发的技术中作出了相当大的努力，但仍期望进一步的改进。
发明内容
本发明涉及具有第一微电子元件和第二微电子元件的微电子组件。每一个微电子元件具有相对的第一表面和第二表面以及作为该表面的边界的边缘。第一微电子元件叠加在第二微电子元件上，且第一微电子元件的第二表面面向第二微电子元件的第一表面。第一微电子元件可延伸超过第二微电子元件的至少一个边缘，且第二微电子元件可延伸超过第一微电子元件的至少一个边缘。
第一微电子元件和第二微电子元件可各自具有长度和宽度，长度大于所述宽度。第一微电子元件可叠加在第二微电子元件上使得第一微电子元件的长度与第二微电子元件的长度交叉。这两个微电子元件还可沿第三轴排列。第三轴垂直于前两个轴。第一微电子元件的至少一个边缘和第二微电子元件的至少一个边缘沿所述第三轴的方向相互平行。
一种微电子半导体封装还可包括具有第一表面和相对的第二表面的衬底。该衬底被置于第一微电子元件和第二微电子元件之间，使得衬底的第一表面面向第一微电子元件的第二表面，且衬底的第二表面面向第二微电子元件的第一表面。该衬底可包括接合触点和端子，其中接合触点和端子中的至少某些暴露在衬底的表面上。第一微电子元件和第二微电子元件还可具有设置在相应表面上的触点。且这些触点中的至少某些可电连接到衬底的接合触点中的至少某些。
衬底可包括至少一个边缘，引线中的至少某些从触点中的至少一个越过边缘延伸至接合触点中的至少某些。迹线中的至少某些与衬底的边缘相邻延伸，使得迹线中的至少某些被设置在接合触点的至少某些和边缘之间。
附图简述
图1是根据本发明的一个实施例的组件的立体图；
图2是根据本发明的一个实施例的封装的立体图；
图3是图2的实施例的示意性俯视图；
图4是附连到电路板的图2的实施例的横截面图；
图5是根据本发明的一个实施例的层叠式封装的横截面图；
图6是根据本发明的另外实施例的组件的立体图；
图7是根据本发明的另外实施例的封装的横截面图；
图8是根据本发明的层叠式封装的替换实施例的横截面图；
图9是沿第一轴截取的根据本发明的替换实施例的封装的横截面图；
图10是沿垂直于第一轴的第二轴截取的图9的实施例的横截面图；
图11是根据本发明的替换实施例的封装的横截面图；
图12是根据本发明的另外实施例的封装的横截面图；以及
图13是根据本发明的另外实施例的封装的横截面图。
详细描述
如图1所示，根据本发明的一个实施例的微电子组件10包括第一微电子元件12和第二微电子元件14。第一微电子元件12和第二微电子元件14可以是半导体芯片、内插板、电路板、模块、芯片上的集成无源元件(IPOC)或各种其它的无源和有源元件。
第一微电子元件12包括第一表面16、相对的第二表面18以及与第一表面16和第二表面18相邻的边缘20、21。边缘20、21是第一微电子元件12周围延伸的周边23的一部分。第二微电子元件14包括第一表面22、相对的第二表面24和与第一表面和第二表面相邻的边缘26、27。边缘26、27是第二微电子元件14周围延伸的周边28的一部分。
第一微电子元件12位于第二微电子元件14上，使得第一微电子元件12的第二表面18面向第二微电子元件14的第一表面22。
如图1所示，第一微电子元件12的边缘20和21在外部延伸过第二微电子元件12的周边28，而第二微电子元件14的周边26和27在外部延伸过第一微电子元件12的周边23。
第一微电子元件12具有长度L和宽度W，第二微电子元件14具有长度L′和宽度W′。长度L和L′的尺寸大于宽度W和W′的尺寸，尽管这并不是必须的。同样，如图1所示，第一微电子元件12的长度L与第二微电子元件14的长度L′横向交叉，更佳的是两个长度L和L′互相垂直。为了便于说明，依照长度L′沿Y轴方向对齐且长度L沿垂直Y轴的X轴方向对齐的坐标系统安排图1。两个微电子元件12、14沿Z轴方向相互层叠。仅为了便于说明而使用本文所述的坐标系统，且不涉及任何重力定位。诸如“顶部”、“底部”、“上部”和“下部”之类的描述性词语类似地仅用于说明的目的。
图1还示出可包括在微电子组件10中的各特征中的一些的例子。第一微电子元件12可包括暴露在其第一表面16上的多个触点32。触点32可在第一表面16上凸起、凹入第一表面或与第一微电子元件12的表面齐平。第二微电子元件14还包括包括暴露在第二微电子元件14的第一表面22上的多个触点34。类似于第一微电子元件12的触点32，第二微电子元件14的触点34实现了第二微电子元件14和另一个微电子元件之间的电连接。
同样，如图1所示，可通过密封剂材料或底充胶36将第一微电子元件12连接到第二微电子元件14。密封材料36可包括环氧树脂、硅酮或其它粘合材料。底充胶36还可以是允许热量从微电子元件12、14扩散的导热材料。尽管图中未示出，但可通过本领域中已知的任何方法—包括但不限于使元件能相互搭扣配合甚至整体地形成在一起的特征，将第一微电子元件12连接或附连到第二微电子元件14。微电子元件12、14还可通过各种台钳、模具等临时相互附连，同时本文所述的各特征被添加到该组件。在添加这些特征之后，可去除台钳，且从而涂覆到组件的密封剂材料可向微电子组件10提供稳定性和结构。
第一微电子元件12还可包括边缘20和21，以及边缘37和38。而第二微电子元件14还可包括边缘26和27以及边缘39和40。在图1所示的实施例中，第一微电子元件的边缘20在X方向上平行于第二微电子元件14的边缘39。且边缘21也平行于第二微电子元件14的边缘39。此外，第一微电子元件12的边缘37和38中的任一个或两者可在Y方向上平行于微电子元件14的边缘26和27。
如图2所示，微电子元件组件10可包括具有顶面42和相对底面44的衬底40。衬底可包括聚酰亚胺层或其它的电介质材料。衬底还可由本领域的技术人员已知的任何已知的组合物来形成。可将焊料掩模层(未示出)设置在单金属层上。
如图2所示，根据本发明的实施例的封装41可包括与衬底40相连接的图1的组件。衬底40被设置成覆盖在第一微电子元件12上使得衬底的底面面向第一微电子元件12的第一表面16。粘合材料46或底充胶可用于将第一微电子元件12连接到衬底40的底面44。密封剂材料可由粘合剂或导热层或执行两种功能的元件来替换。
衬底40包括暴露在顶面42且通过孔49暴露在底面44的多个端子48，在图4中极好地示出。尽管不是必需的，但可沿衬底的周边P放置端子48，更佳的是可将端子置于衬底的拐角处。
如图3所示，衬底40可包括暴露于衬底的顶面42的接合触点50。接合触点50中的至少某些可通过设置在衬底40之上或之中的迹线52电连接到端子48中的至少某些。诸如衬底40的端子48、接合触点50和迹线52之类的电互连元件可形成于两层或三层之中。在图2和3的实施例中，互连元件是利用单层金属形成的。
衬底40还包括从顶面42延伸至底面44的多个开口54。在本发明的一个较佳实施例中，开口54分别与第一微电子元件和第二微电子元件的触点32和34对齐。因此，开口叠加，并允许对相应的微电子元件的接入。诸开口54各自可由边缘56部分地限定。
为了将微电子元件12和14电互连至衬底40，可将电互连元件包括在触点32、34和接合触点50之间的微电子组件41中。互连元件可以是从触点32、34开始，穿过开口54，越过边缘56至接合触点50延伸的引线55的形式。引线55将第一微电子元件12和第二微电子元件14的触点32、34连接至衬底40的接合触点50。
接合触点50通过迹线52连接至衬底的端子48。迹线52包括各种部分、角、转弯以及由平行于限定一个槽的衬底边缘56的箭头E所指示的沿边缘方向延伸的线路53。
接合触点50中的至少某些被设置在开口54附近的多个行51中。接合触点中的每一行可在平行于槽的相邻边缘56的沿边缘方向上延伸。例如，与槽54A相邻的接合触点的行51A沿与开口54A的边缘56相邻的边缘方向E延伸，而行51B中的接合触点沿平行于槽54B的边缘56的边缘方向延伸。
行51A的接合触点被连接在本文中称为“紧邻迹线”配置的配置中，且迹线52的线路53中的至少某些连接至在接合触点和相邻开口54A的边缘56之间延伸的接合触点50。行51A的接合触点连接至接近开口一端的一组端子48A。最接近该组端子的接合触点50Aa连接至离边缘56最远的线路53Aa，线路53Aa又连接至端子48Aa。离该组端子最远的接合触点50Ac连接至最接近边缘56的线路53Ac，线路53Ac又连接至端子48Ac。以同一方式，其它的接合触点连接至迹线线路，从而连接至组48A中的端子。连接至端子的顺序对应于沿边缘方向EA的接触位置的顺序，即，沿远离端子组48A的边缘56A的沿边缘方向。
行51B的接合触点和迹线被连接在本文中称为“远离迹线”配置的相反配置中。在远离迹线配置中，连接至行的接合触点的迹线52的线路53中的至少某些位于连接至这些触点的线路和相邻开口54B的边缘56之间。行51B的接合触点也连接至同一组端子48A。在行51B中，离该组端子48A最远的接合触点50Ba连接至离边缘56B最远的线路53Ba，线路53Ba又连接至端子48Aa。最接近该组端子48A的接合触点50Bc连接至最接近边缘56B的线路53Bc，线路53Bc又连接至端子48Ac。此外，行51B中的其它接合触点连接至迹线线路，从而以根据其触点位置的顺序连接至组48A中的端子。连接至端子的顺序对应于沿边缘方向EB的接触位置的顺序，即，沿朝向端子组48A的边缘56B的沿边缘方向。
该配置提供了具有相同的至端子的连接顺序的两行接合端子，但以两种不同的沿边缘方向行进，而没有交叉，使得所有的迹线可形成于单金属层中。接合端子的相同连接的行使得对相同芯片共用连接能够形成。例如，芯片12上标号为“IO7”的触点连接至接合触点50Ba，从而连接至端子48a，而芯片14上标号为“IO7”的相同触点34连接至接合触点50Aa，从而连接至同一端子48a。
行51C中的大多数接合触点以紧邻迹线配置连接至端子组48B，而行51D中的大多数接合触点以远离迹线配置连接至同一端子组48B。此外，远离迹线配置和紧邻迹线配置的使用使得行51D中至组48B的端子的连接顺序与行51C中至同一端子的连接顺序相同，而没有交叉。多组芯片启动接合触点50′分布在行51C和51D中。芯片启动接合触点由附加迹线连接至组48C中的端子。注意，这些附加迹线中的某些具有在行51D的接合触点和开口54D的相邻边缘之间延伸的线路53′。
通过引线接合工艺形成的引线55将接合触点连接至芯片的触点32和34。与接合触点的每一行相关联的引线接合在相邻的边缘56上延伸，并延伸穿过相邻孔径54至诸芯片之一。例如，如图3和4所示，与行51A和51C的接合触点相关联的引线接合延伸穿过槽54A和54C。某些引线接合越过某些迹线的线路53延伸。例如，具有紧邻迹线配置的与行51A和51C的接合触点相关联的引线接合55越过相关联的线路延伸。如图4中极好的看到的，引线接合环绕在迹线上。类似地，与行51D(图3)中的某些触点相关联的引线接合跨越在与芯片启动触点相关联的线路53′上。引线接合基本上以零成本提供交叉；因为在任何情况下都必须提供引线接合以形成芯片上的触点和接合触点之间的连接。在形成引线接合55时几乎不或不涉及附加成本，且具有略微的上升以使引线接合能跨越迹线52。一般，一个引线接合55连接至每一个芯片触点32、34。图3将芯片启动触点(标号为“CE”)描述为连接至所有的芯片启动接合触点50′；在实际中，每一个芯片启动触点被连接至仅一个芯片启动接合触点，从而仅连接至组48C中的一个端子。不同的芯片连接至组48C中的不同端子。
如图4所示，微电子组件41可包括粘附至衬底40的顶面42的密封剂材料60。密封剂材料60保护并维持将接合触点50互连至微电子元件12、14的触点32、34的引线55的完整。同样，如图4所示，端子48使微电子组件41能电连接至诸如电路板62之类的微电子元件。电路板62包括暴露于电路板的表面上的端子64。诸如焊料块66之类的电互连可用于将衬底42的端子48电连接至电路板62的端子64。
由于微电子组件41相当薄，封装和电路板62之间的电互连可被形成为不妨碍第一微电子元件12和第二微电子元件14的放置。可将另外的密封剂70设置在第一微电子元件12和第二微电子元件14周围，不仅用于将微电子元件连接至衬底40还可维持穿过衬底的开口54延伸的引线55的整体性。
如图5所示，可设置微电子组件41，且第二微电子组件141覆盖在该组件上。第二微电子组件141可充分地类似于带有类似特征和元件的第一微电子组件41。第二微电子组件141较佳地具有暴露于衬底140的顶面142上且暴露于底面144上的端子148。端子148可通过例如焊料块166电连接至第一微电子组件41的端子48。尽管仅示出了两个半导体封装在顶部相互层叠，但本发明构想了任何数量的封装在顶部相互层叠。在另一个变形中，如果不需要的话，端子48、148可不暴露在相应的顶面42、142上。可将密封剂粘附至衬底140的顶面142上以保护并维持引线155完整。
如图6所示，第一微电子元件212可覆盖在第二微电子元件214上，且第一微电子元件212的边缘238沿X方向平行于第二微电子元件214的边缘227。第一微电子元件212的边缘220、221可分别向外延伸过第二微电子元件214的边缘239和240。尽管示出两个边缘220和221都向外延伸过第二微电子元件的相应边缘，但这并不是必须的，且微电子元件中的仅一个边缘可向外延伸过第二微电子元件的边缘。图6中所示的微电子封装210可包括本文讨论的先前实施例中包括的各种特征和元件。例如，可包括类似于衬底40的带有微电子封装210以形成一组件的衬底。
本发明在附图中示出了具有矩形形状的微电子元件。在替换实施例中，微电子元件可具有任何形状，包括但不限于正方形、三角形、椭圆形和圆形。
在图7中所示的又一个替换实施例中，引线355可越过衬底340的边缘341延伸，从而将暴露于第一微电子元件312和第二微电子元件314上的触点332、334电连接到暴露于衬底340上的接合触点350。可将密封剂材料置于微电子半导体封装310的周围以维持封装的刚性和稳定性。
如图8所示，图3的微电子组件41可按面对关系层叠到第二微电子组件441。第二微电子组件441可包括很多参考本文所讨论的先前实施例中所示的相同的特征和元件。为了便于说明，附图中未示出这些特征中的某些。在两个微电子组件互相面对时，第一微电子组件41的端子48和第二微电子组件441的端子448还可互相面对。可将电连接466设置在端子48、448之间，以便连接它们并形成层叠的微电子封装。例如，可将接触焊盘(未示出)置于衬底40上，以便将封装连接至电路板。
在又一个替换实施例中，如图9和10所示微电子组件541可包括第一微电子元件512和第二微电子元件514。第一微电子元件512包括第一表面516和相对的第二表面518。第二微电子元件514也包括第一表面520和相对的第二表面522。微电子组件541还包括具有第一表面542和第二表面544的衬底540。第一微电子元件512被设置成覆盖在衬底540上使得第一微电子元件的第二表面518面对衬底540的顶面542。且，第二微电子元件514被设置在衬底540下，使得微电子元件的第二表面522面对衬底的底面544。
可通过底充胶或密封剂560将微电子元件512、514附连至衬底540。两个微电子元件512、514类似于本文所讨论的先前实施例设置，但将衬底540置于元件之间除外。因此，在最佳实施例中，第一微电子元件512的边缘520、521中的至少一个向外延伸过第二微电子元件514的边缘539、540中的一个。且，第二微电子元件514的边缘526、527中的至少一个向外延伸过第二微电子元件514的边缘537、538中的一个。因此，在最佳实施例中，两个微电子元件被设置成十字形关系，且衬底置于其间。
第一微电子元件512和第二微电子元件514还较佳地包括暴露于其相应第二表面518、522上的触点532、534。触点532、534较佳地与从衬底540的顶面542延伸至底面544的开口对齐。衬底540还包括暴露于顶面542或底面544中的任一个或两者上的端子548以及暴露于顶面和底面上的接合触点50。接合触点550中的至少某些通过图10所示的迹线552与端子548中的至少某些电连接。为了便于说明，仅示出了将接合触点550连接至端子548的迹线中的某些。如图10所示，可将金属层设置在衬底540的底面544上，且接合触点550暴露于衬底的顶面542和底面544上。
在将微电子元件512、514电连接至衬底540的方法中，电互连，即，引线555被附连至触点532、534。引线555从触点532、534延伸穿过衬底的开口554直到附连至接合触点550。因此，引线555从微电子元件512或514开始从衬底540的一个表面—第一微电子元件的顶面542和第二微电子元件514的底面544—延伸至衬底相反的一面。例如，引线555中的某些附连至与顶面542相邻的第一微电子元件512的触点332，并穿过开口554跨过边缘556延伸到衬底540的底面544，具体的是设置在底面上的接合触点550。相反，连接至第二微电子元件的引线555从与衬底的底面544相邻的触点534延伸至顶面542。具体的是至暴露在衬底的顶面542上的接合触点550。可将密封材料561设置在引线555上以保护它们。类似于前面讨论的实施例，微电子组件541可层叠到类似的组件或各种其它组件以形成层叠式封装。
在图11所示的替换实施例中，微电子组件641可包括类似于图9和10的第一微电子元件和衬底形成的衬底640和第一微电子元件612。但是，第二微电子元件614与图9和10所示元件的不同之处在于它在衬底的底面644上电互连到衬底640。第二微电子元件614可较佳地包括沿第二微电子元件的第二表面622暴露的触点634。这些触点可通过球栅阵列、双头凸起、引线或另外的电连接机构电连接至衬底540。衬底640包括暴露在其可与第二微电子元件的触点634互连的第二表面644上的接合触点50。
在图12所示的又一个替换实施例中，除衬底740包括两个金属层结构外，微电子组件741可被类似地构造成前面的实施例，其中第一金属层790暴露在衬底740的顶面742，而第二金属层791被设置在衬底的底面744。
微电子组件741如同先前的实施例一样包括第一微电子元件712和第二微电子元件714，可将每一个微电子元件以本文中已经讨论的方法附连至衬底740。具有两个金属层的一个优点是：连接暴露在相应的微电子元件712、714的第一表面上的触点的接合线755不必延伸穿过衬底740然后返回并再次穿过衬底740，以便接合至衬底740的接合触点750。
尽管图中未示出，但如参考本文的先前实施例所讨论的，第一金属层742和第二金属层745可各自包括多个端子、迹线和接合触点。
尽管本文讨论了各种单金属层实施例和两个金属层的实施例，其中金属层暴露在衬底的表面上，但本发明还构想了其中单金属层或两个金属层暴露在衬底中的情形。一个或多个金属层可根据特定要求暴露在衬底的一个或两个表面上。
在本发明的另一个替换实施例中，微电子组件841可类似于本文的任意实施例来构造，但还包括代替端子或与端子结合的导电柱或支柱898。在图13所示的一个具体实施例中，支柱898从衬底840向下延伸。与迹线852结合的支柱和接合触点850可如共同受让的美国专利申请第10/985,119号、第10/985,126号以及第11/014,439号所公开的来构造，其内容通过引用结合于此。
在附图中未示出的又一个替换实施例中，图11的第二微电子元件614可具有沿第二微电子元件的第一表面620设置的触点。可利用引线将触点附连到暴露于衬底640的底面644上的接合触点。衬底可任选地包括附加的迹线层。此外，尽管将开口54示出为细长的槽，但它们可具有任何构造。
工业实用性
本发明可用于电子器件的制造。
尽管本文中参考具体实施例描述了本发明，但应理解，这些实施例仅仅是本发明的原理和应用的说明。因此将理解可对说明性实施例进行各种修改且可设计出其它的配置，而不背离由所附权利要求定义的本发明的精神和范围。

Claims (21)

1.一种微电子组件，包括：第一微电子元件和第二微电子元件，每一个所述微电子元件具有相对的第一表面和第二表面以及作为所述第一表面和第二表面的边界的边缘，所述第一微电子元件叠加在所述第二微电子元件上，且所述第一微电子元件的所述第二表面面向所述第二微电子元件的所述第一表面，所述第一微电子元件延伸超过所述第二微电子元件的至少一个边缘，且所述第二微电子元件延伸超过与所述第二微电子元件的所述至少一个边缘交叉的所述第一微电子元件的至少一个边缘，
所述微电子组件还包括覆盖所述第一微电子元件和第二微电子元件的衬底，所述衬底具有第一表面和相对的第二表面，所述衬底具有接合触点和端子，所述接合触点中的至少某些通过迹线与所述端子中的至少某些互连，
所述第一微电子元件具有暴露于所述第一微电子元件的所述第一和第二表面中面向所述衬底的表面上的触点，并且所述触点中的至少某些电连接到所述衬底的所述接合触点中的至少某些，
所述第二微电子元件具有暴露于所述第二微电子元件的所述第一和第二表面中面向所述衬底的表面上的触点，所述第二微电子元件的所述触点中的至少某些通过引线电连接到所述衬底的所述接合触点中的至少某些，
其中所述衬底包括至少一个边缘，所述迹线中的至少某些与所述衬底的所述边缘相邻延伸，使得所述迹线中的至少某些被设置在所述接合触点的至少某些和所述边缘之间，
并且其中所述引线中的至少某些从暴露于所述衬底的第一表面上的所述接合触点中的至少某些越过所述迹线中的某些延伸且不与所述迹线中的至少某些电连接，且所述引线越过所述衬底的所述边缘延伸至所述衬底的第二表面下的所述第二微电子元件的所述触点。
2.如权利要求1所述的微电子组件，其特征在于，所述第一微电子元件和所述第二微电子元件各自具有长度和宽度，所述长度大于所述宽度，其中所述第一微电子元件叠加在所述第二微电子元件上使得所述第一微电子元件的所述长度与所述第二微电子元件的所述长度交叉。
3.如权利要求1所述的微电子组件，其特征在于，所述第一微电子元件和所述第二微电子元件沿第一轴和第二轴排列，其中所述第一微电子元件和所述第二微电子元件具有第一边缘和第二边缘，且其中所述第一微电子元件和所述第二微电子元件的所述第一边缘沿所述第一轴的方向相互平行，所述第一微电子元件和所述第二微电子元件的所述第二边缘沿所述第二轴的方向相互平行。
4.如权利要求3所述的微电子组件，其特征在于，所述第一微电子元件和所述第二微电子元件沿第三轴排列，所述第三轴在Z方向上，第三轴使得所述第一微电子元件的至少一个边缘和所述第二微电子元件的至少一个边缘沿所述第三轴的方向相互平行。
5.如权利要求1所述的微电子组件，其特征在于，所述第一微电子元件的所述第二表面通过密封剂材料附连至所述第二微电子元件的所述第一表面。
6.如权利要求1所述的微电子组件，其特征在于，所述第一和所述第二微电子元件包括若干触点。
7.如权利要求1所述的微电子组件，其特征在于，所述接合触点中的至少某些暴露在所述衬底的所述第一表面，且所述端子中的至少某些暴露于所述衬底的所述第二表面。
8.如权利要求1所述的微电子组件，其特征在于，所述衬底具有周边，且所述边缘置于所述周边内。
9.如权利要求8所述的微电子组件，其特征在于，将所述触点连接到所述接合触点并在所述衬底的所述边缘附近延伸的所述引线中的至少某些覆盖在与所述边缘相邻的所述迹线中的至少某些上。
10.如权利要求1所述的微电子组件，其特征在于，还包括具有焊盘的第三微电子元件，其中所述衬底的所述端子中的至少某些电连接到所述第三微电子元件的所述焊盘中的至少某些。
11.如权利要求7所述的微电子组件，其特征在于，还包括具有焊盘的第三微电子元件，其中所述第一微电子元件和所述第二微电子元件的所述端子中的至少某些电连接到所述第三微电子元件的所述焊盘中的至少某些。
12.如权利要求1所述的微电子组件，其特征在于，所述衬底覆盖在所述第一微电子元件上使得所述衬底的所述第二表面面向所述第一微电子元件的所述第一表面，其中所述衬底及所述第一微电子元件和所述第二微电子元件限定第一封装，还包括第二封装，所述第二封装具有类似于所述第一封装的元件，其中所述第二封装覆盖在所述第一封装上。
13.一种微电子半导体封装，包括：如权利要求1所述的组件，所述衬底覆盖在所述第一微电子元件上使得所述衬底的所述第二表面面向所述第一微电子元件的所述第一表面。
14.一种微电子半导体封装，包括：如权利要求1所述的组件，所述衬底被置于所述第一微电子元件和所述第二微电子元件之间使得所述衬底的所述第一表面面向所述第一微电子元件的所述第二表面，且所述衬底的所述第二表面面向所述第二微电子元件的所述第一表面。
15.一种微电子组件，包括：
具有顶面、底面和第一边缘的衬底，所述衬底具有暴露于所述顶面上的多个接合触点和多个端子，所述衬底还具有将所述接合触点中的某些连接到所述多个端子中的至少某些的多个迹线，所述迹线中的至少某些与所述衬底的第一边缘相邻延伸，使得所述迹线中的至少某些被设置在所述接合触点中的至少某些和所述第一边缘之间；以及
在所述衬底之下的第一微电子元件，使得所述衬底的所述底面面向所述第一微电子元件，所述第一微电子元件具有触点，所述触点中的至少某些通过引线连接至所述多个接合触点中的至少某些，其中所述引线中的至少某些从所述接合触点中的至少某些延伸横越所述多个迹线中的至少某些并越过所述第一边缘至所述触点。
16.如权利要求15所述的微电子组件，其特征在于，还包括具有第一表面和第二表面的第二微电子元件，其中所述第一微电子元件包括第一表面和第二表面，所述第二微电子元件位于所述第一微电子元件之下，使得所述第一微电子元件的所述第二表面面向所述第二微电子元件的所述第一表面。
17.如权利要求16所述的微电子组件，其特征在于，所述第二微电子元件具有触点，所述第二微电子元件的所述触点中的至少某些通过引线连接至所述衬底的所述多个接合触点中的至少某些。
18.如权利要求17所述的微电子组件，其特征在于，所述衬底具有第二边缘，且其中所述衬底的所述迹线中的至少某些与所述第二边缘相邻，且在所述第二边缘和所述多个接合触点中的至少某些之间，其中连接所述第二微电子元件的所述触点的所述引线从所述第二微电子元件的所述触点延伸越过所述第二边缘并横越与所述第二边缘相邻的所述迹线至所述多个接合触点。
19.如权利要求18所述的微电子组件，其特征在于，所述衬底具有周边，且所述第一边缘和所述第二边缘被设置在所述周边内。
20.如权利要求15所述的微电子组件，其特征在于，所述第一微电子元件的所述触点中的单个触点连接至所述衬底的一个以上的接合触点。
21.如权利要求15所述的微电子组件，其特征在于，所述衬底的所述多个接合触点中的至少某些所述接合触点沿第一部分排列，且所述衬底的所述多个端子中的至少某些所述端子沿第二部分排列，其中将所述第一部分的所述接合触点连接到所述第二部分的所述端子的所述迹线中的至少某些包括线路，其中所述引线中的至少某些越过所述迹线的所述线路中的某些延伸。
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