JPH04155954A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH04155954A
JPH04155954A JP2282507A JP28250790A JPH04155954A JP H04155954 A JPH04155954 A JP H04155954A JP 2282507 A JP2282507 A JP 2282507A JP 28250790 A JP28250790 A JP 28250790A JP H04155954 A JPH04155954 A JP H04155954A
Authority
JP
Japan
Prior art keywords
semiconductor memory
island
pads
semiconductor
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2282507A
Other languages
English (en)
Inventor
Naoto Kimura
直人 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP2282507A priority Critical patent/JPH04155954A/ja
Publication of JPH04155954A publication Critical patent/JPH04155954A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明の半導体装置に関する。
〔従来の技術〕
従来の半導体記憶装置は第３図に示す様な構造をしてお
り、半導体記憶素子１の端部に集中して配置されたバッ
ド１０よりインナリード６へワイヤ５にて配線接続され
ていた。
〔発明が解決しようとする課題〕
上述した従来の半導体記憶装置は、第２図に示す様にパ
ッド１０を半導体記憶素子１の端部に集中して配置せざ
るをえない構造となっているために、アウタリード７へ
の接続は、インナリード６を複雑な形状に加工して行な
っていた。従って。
パッケージにおけるインナリード６が占有する面積が広
くなることによりパッケージ本体が大きくなるという欠
点を有していた。
〔課題を解決するための手段〕
本発明の半導体装置は、アイランド上面に搭載された第
１の半導体素子および前記第１の半導体素子上又は前記
アイランド下面に絶縁材を介して搭載された第２の半導
体素子を有し、前記第１゜第２の半導体素子はそれぞれ
の長手方向が直交しているというものである。
〔実施例〕
次に本発明について図面を参照して説明する。
第１図（ａ）は本発明の一実施例の一部破砕平面図、第
１図（ｂ）は第１図＜ａ＞のＸ−Ｘ線断面図である。
第１の半導体記憶素子１ａはアイランド３の上面より接
着材２ａを介して搭載されている。一方アイランド３の
下面には、表面に絶縁材４がコーティングされた第２の
半導体記憶素子１ｂが第１の半導体記憶素子１ａと直交
して接着材２ｂにより接着されている。上下２個の半導
体記憶素子はそれぞれのパッド１０よりワイヤ５にて接
続されパッケージ樹脂８により封止されている。アウタ
リード７はＱＦＰ製品同様に形成されている。なお、吊
りピン９は封止時までは外部と連絡されているがリード
成形時に切断される。
この実施例では、アイランドの上面と下面にそれぞ半導
体記憶素子を搭載したが、第２図に示すように、第１の
半導体記憶素子１ａの表面に絶縁材をコーディングし第
２の半導体記憶素子１ｂを貼り付けてもよい。
〔発明の効果〕
以上説明したように本発明は、アイランドに互いに直交
させて２つの半導体記憶素子を搭載することで半導体素
子の端部に集中するパッドからのインナリードへの配線
引き廻しを容易にするとともに、占有面積のわずかな増
大のみで半導体装置の集積度をほぼ２倍に向上すること
ができる。
【図面の簡単な説明】
第１図（ａ）は本発明の一実施例の一部破砕平面図、第
１図（ｂ）は第１図（ａ）のＸ−Ｘ線断面図、第２図は
一実施例の変形を示す断面図、第３図（ａ）は従来例の
一部破砕平面図、第３図（ｂ）は従来例の正面図である
。 １ａ・・・第１の半導体記憶素子、１ｂ・・・第２の半
導体記憶素子、２ａ、２ｂ・・・接着材、３・・・アイ
ランド、４・・・絶縁材、５・・・ワイヤ、６・・・イ
ンナリード、７・・・アウタリード、８・・・パッケー
ジ樹脂、９・・・吊りリード、１０・・・パッド。

Claims (1)

    【特許請求の範囲】
  1. 　アイランド上面に搭載された第１の半導体素子および
    前記第１の半導体素子上又は前記アイランド下面に絶縁
    材を介して搭載された第２の半導体素子を有し、前記第
    １、第２の半導体素子はそれぞれの長手方向が直交して
    いることを特徴とする半導体装置。
JP2282507A 1990-10-19 1990-10-19 半導体装置 Pending JPH04155954A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2282507A JPH04155954A (ja) 1990-10-19 1990-10-19 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2282507A JPH04155954A (ja) 1990-10-19 1990-10-19 半導体装置

Publications (1)

Publication Number Publication Date
JPH04155954A true JPH04155954A (ja) 1992-05-28

Family

ID=17653344

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2282507A Pending JPH04155954A (ja) 1990-10-19 1990-10-19 半導体装置

Country Status (1)

Country Link
JP (1) JPH04155954A (ja)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0680086A3 (en) * 1994-04-15 1997-05-02 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method for this semiconductor device.
US5689135A (en) * 1995-12-19 1997-11-18 Micron Technology, Inc. Multi-chip device and method of fabrication employing leads over and under processes
US5793108A (en) * 1995-05-30 1998-08-11 Sharp Kabushiki Kaisha Semiconductor integrated circuit having a plurality of semiconductor chips
US5818114A (en) * 1995-05-26 1998-10-06 Hewlett-Packard Company Radially staggered bond pad arrangements for integrated circuit pad circuitry
KR100277308B1 (ko) * 1997-04-17 2001-02-01 마찌다 가쯔히꼬 반도체장치
WO2001043193A3 (en) * 1999-12-09 2002-03-28 Atmel Corp Dual-die integrated circuit package
JP2009518825A (ja) * 2005-12-01 2009-05-07 テッセラ，インコーポレイテッド 積層型マイクロエレクトロニクスパッケージ

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5326867B2 (ja) * 1974-11-11 1978-08-04
JPH0425166A (ja) * 1990-05-21 1992-01-28 Matsushita Electric Ind Co Ltd 半導体装置および半導体装置の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5326867B2 (ja) * 1974-11-11 1978-08-04
JPH0425166A (ja) * 1990-05-21 1992-01-28 Matsushita Electric Ind Co Ltd 半導体装置および半導体装置の製造方法

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0680086A3 (en) * 1994-04-15 1997-05-02 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method for this semiconductor device.
US5640044A (en) * 1994-04-15 1997-06-17 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of producing said semiconductor device
US5818114A (en) * 1995-05-26 1998-10-06 Hewlett-Packard Company Radially staggered bond pad arrangements for integrated circuit pad circuitry
US5793108A (en) * 1995-05-30 1998-08-11 Sharp Kabushiki Kaisha Semiconductor integrated circuit having a plurality of semiconductor chips
US5689135A (en) * 1995-12-19 1997-11-18 Micron Technology, Inc. Multi-chip device and method of fabrication employing leads over and under processes
US5898220A (en) * 1995-12-19 1999-04-27 Micron Technology, Inc. Multi-chip device and method of fabrication employing leads over and under processes
KR100277308B1 (ko) * 1997-04-17 2001-02-01 마찌다 가쯔히꼬 반도체장치
WO2001043193A3 (en) * 1999-12-09 2002-03-28 Atmel Corp Dual-die integrated circuit package
US6376914B2 (en) 1999-12-09 2002-04-23 Atmel Corporation Dual-die integrated circuit package
JP2009518825A (ja) * 2005-12-01 2009-05-07 テッセラ，インコーポレイテッド 積層型マイクロエレクトロニクスパッケージ
US8890327B2 (en) 2005-12-01 2014-11-18 Tessera, Inc. Stacked microelectronic packages having at least two stacked microelectronic elements adjacent one another
KR101479440B1 (ko) * 2005-12-01 2015-01-06 테세라, 인코포레이티드 적층형 마이크로전자 패키지
US9627366B2 (en) 2005-12-01 2017-04-18 Tessera, Inc. Stacked microelectronic packages having at least two stacked microelectronic elements adjacent one another

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