CN103035641B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN103035641B
CN103035641B CN201210313561.8A CN201210313561A CN103035641B CN 103035641 B CN103035641 B CN 103035641B CN 201210313561 A CN201210313561 A CN 201210313561A CN 103035641 B CN103035641 B CN 103035641B
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semiconductor layer
diode
semiconductor
electrode
layer
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CN103035641A (zh
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斋藤涉
小野升太郎
仲敏行
谷内俊治
山下浩明
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Toshiba Corp
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Toshiba Corp
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Abstract

本发明提供一种半导体装置，具有场效应型晶体管、第5半导体层、第1二极管和第2二极管，该场效应型晶体管具有：半导体基板、设在所述半导体基板内的多个第2半导体层、以及设在所述第1半导体层的另一方的表面的第6半导体层，该第5半导体层设在所述半导体基板的一方的表面侧，该第1二极管与所述第5半导体层连接，该第2二极管以与所述第1二极管逆串联的方式连接。

Description

半导体装置
相关申请的交叉引用
本申请基于2011年9月29日提交的在先日本专利申请2011－215726并享受其优先权，后者的全部内容以引用的方式并入于此。
技术领域
实施方式涉及半导体装置。
背景技术
纵型功率MOSFET（Metal-Oxide-SemiconductorFieldEffectTransistor）例如用于电源管理电路或锂离子电池的安全电路，因此要求低导通电阻化、高耐压化、低电压驱动化以及开关损失的减轻化等。
纵型功率MOSFET除了在高电压施加状态下进行开关的功能以外，还具有如下功能：在被施加了过电压的情况下，引起雪崩击穿而流过电流，同时对电压进行钳位（clamp）。通过该功能，能够防止周围的元件的绝缘损坏。
将雪崩状态下流过的电流的大小或能量的大小称为雪崩耐量，为了增大雪崩耐量，预先较低地设计耐压是有效的。但是，如果较低地设计耐压，则产生导通电阻变高的问题。
发明内容
本发明的实施方式提供一种兼顾雪崩耐量的增大和导通电阻的降低的半导体装置。
总体而言，根据一个实施方式，一种半导体装置，具有场效应型晶体管、第1二极管和第2二极管，所述场效应型晶体管具有：半导体基板，包括第1导电型的第1半导体层；多个第2导电型的第2半导体层，从所述半导体基板的一方的表面侧向深度方向延伸，而且相互隔开间隔地设在所述半导体基板内；多个第2导电型的第3半导体层，设为在所述半导体基板的一方的表面侧与一部分所述第2半导体层相接；第1导电型的第4半导体层，选择性地形成在所述第3半导体层的表面；控制电极，隔着绝缘膜设在所述第1半导体层、所述第3半导体层以及所述第4半导体层的表面侧；第1主电极，与所述第3半导体层及所述第4半导体层连接；第1导电型的第6半导体层，设在所述第1半导体层的另一方的表面；以及第2主电极，与所述第6半导体层电连接；所述第1二极管包括第2导电型的第5半导体层、所述第1半导体层、所述第2半导体层和所述第6半导体层而构成，该第2导电型的第5半导体层设为在所述半导体基板的一方的表面侧与一部分所述第2半导体层相接，该第1二极管与钳位电极连接，该钳位电极与所述第5半导体层连接；所述第2二极管包括与所述控制电极连接的第7半导体层而构成，以与所述第1二极管逆串联的方式与所述钳位电极连接。
根据本发明的实施方式，提供一种能够兼顾雪崩耐量的增大和导通电阻的降低的半导体装置。
附图说明
图1是表示第1实施方式的半导体装置1的要部截面图。
图2是表示第1实施方式的半导体装置1的等价电路图。
图3是表示在第1实施方式中使用肖特基势垒二极管的情况的半导体装置1的要部截面图。
图4是表示第2实施方式的半导体装置1的要部截面图。
图5是表示第3实施方式的半导体装置1的要部俯视图。
图6是表示图5的X‐A‐X’线的截面的要部截面图。
图7是表示第3实施方式的变形例的半导体装置1的要部截面图。
图8A是表示第4实施方式的半导体装置1的要部截面图。
图8B是表示图8A所示的部分的纵向（深度方向）的杂质浓度特性的图表。
图9A是表示第5实施方式的半导体装置1的要部截面图。
图9B是表示图9A所示的部分的横向的杂质浓度特性的图表。
图10A是表示第5实施方式的变形例的半导体装置1的要部截面图。
图10B是表示图10A所示的部分的横向的杂质浓度特性的图表。
图11是表示第6实施方式的半导体装置1的要部截面图。
图12是表示第6实施方式的变形例的半导体装置1的要部截面图。
具体实施方式
以下，参照附图说明本发明的实施方式。其中，在本实施方式中，将第1导电型作为n型且将第2导电型作为p型进行说明，但将第1导电型作为p型且将第2导电型作为n型也能够实施本发明。
（第1实施方式）
图1示出表示第1实施方式的半导体装置1的要部截面图，图2示出该半导体装置1的等价电路图。
第1实施方式的半导体装置1由MOS2（场效应型晶体管）、第1二极管3及第2二极管4构成。另外，该半导体装置1是在半导体基板上适当地使用离子注入法和外延法的双方来制作的。在本实施方式中，该半导体基板以作为第1半导体层的n-型漂移层20示出。另外，成为第2半导体层的多个p型柱层21从n-型漂移层20的一方的表面侧向深度方向延伸，而且相互具有间隔地设置。结果，p型柱层21和n-型漂移层20周期性地邻接（pn结）设置而成，构成所谓的“超结（superjunction）构造”。超结构造通过使p型柱层21与n-型漂移层20的电荷（charge）量（杂质量）相同，来虚拟地制造出无杂质(non-dope)层，保持高耐压并且通过n-型漂移层20流过电流，从而能够实现超越材料极限的导通电阻的降低。
在n-型漂移层20的一方的表面侧，以与一部分p型柱层21相接的方式，设有作为第3半导体层的p型基极层22。进而，在p型基极层22的表面侧，选择性地设有作为第4半导体层的n型源极层23。
在n-型漂移层20的一方的表面侧，以与未设有p型基极层22的一部分p型柱层21相接的方式，设有作为第5半导体层的p型钳位层30。
另外，栅极绝缘膜24设在从一方的n型源极层23经由n-型漂移层20到达邻接的另一方的n型源极层23的区域上。栅极绝缘膜24例如使用硅氧化膜等。隔着该栅极绝缘膜24，设有作为控制电极的栅极电极25。栅极电极25例如使用多晶硅等。另外，在p型基极层22和n型源极层23之上，设有作为第1主电极的源极电极50。
在此，在n-型漂移层20的另一方的表面侧，设有成为第6半导体层的n+型漏极层26。进而，在该n+型漏极层26的表面侧，设有成为第2主电极的漏极电极51，n+型漏极层26与漏极电极51电连接。
通过该漏极电极51与源极电极50之间的n-型漂移层20和p型柱层21、p型基极层22、n型源极层23、栅极绝缘膜24、栅极电极25以及n+型漏极层26构成MOS2。另外，通过p型钳位层30、设在该p型钳位层30之下的n-型漂移层20、p型柱层21、n+型漏极层26构成第1二极管3。
进而，利用形成栅极电极25的例如多晶硅等，第2二极管4设在p型钳位层30的上部。在图1中，第2二极管4作为一例，以与栅极电极25电连接的栅极电极25a作为阴极，通过形成作为第7半导体层的低浓度半导体层40和作为第8半导体层的p型半导体层41，构成为pin二极管。
另外，与第2二极管4的p型半导体层41连接的钳位电极52与第1二极管3电连接。此时，该第1二极管3和第2二极管4逆串联地连接在MOS2的栅极电极25与漏极电极51之间。另外，通过调整第1二极管3的杂质浓度和厚度等，将第1二极管3的耐压设为比MOS2的耐压低。
在如上构成的半导体装置1中，若对栅极电极25施加阈值电压以上的规定电压，则在MOS2的正下方的p型基极层22的表层部形成沟道，n型源极层23和n-型漂移层20通电。结果，经由n型源极层23、n-型漂移层20以及n+型漏极层26，在源极电极50与漏极电极51之间流过电流，该半导体装置1成为导通状态。
图2示出表示第1实施方式的半导体装置1的等价电路图。首先，在向栅极电极25a的引出端子即输入端子60输入了截止状态的信号（0V）的状态下，在源极电极50与漏极电极51之间施加高电压。此时，在设为耐压比MOS2低的第1二极管3中，比MOS2先发生雪崩击穿。
由此，从第1二极管3经由第2二极管4、栅极电阻61向输入端子60流过电流。由于流过电流，产生由栅极电阻61引起的电压下降，如果对栅极电极25施加的电压成为阈值电压以上，则MOS2成为导通状态，从漏极电极51向源极电极50流过电流。
像这样，在源极电极50与漏极电极51之间，通过由第1二极管3的耐压决定的电压进行钳位，在第1二极管3中流过由雪崩击穿引起的电流，但即使在MOS2中未流过由雪崩击穿引起的电流，也能够在源极电极50与漏极电极51之间流过电流。
在第1二极管3中，未形成寄生双极晶体管，因此比MOS2容易得到雪崩耐量。另外，产生使MOS2成为导通状态的电压下降即可，因此雪崩电流较小。进而，在MOS2中流过的电流不是像雪崩击穿那样的双极动作，而是单极动作，因此不容易损坏。由此，作为半导体装置1整体，能够实现高雪崩耐量。
另外，插入第2二极管4的理由是，防止如下状况：在向输入端子60输入了导通状态的信号（例如10V）的情况下，第1二极管3成为导通状态，而在输入端子60与漏极电极51之间流过电流。因此，第2二极管4的耐压优选具有动作上必须保证的输入电压以上（例如30V以上）的耐压。
像这样，在半导体装置1内，构成与耐压比MOS2低的第1二极管3逆串联连接的第2二极管4，即使MOS2的雪崩耐量较低，也能够在整体上实现高雪崩耐量。因此，能够在MOS2的n-型漂移层20的设计中具有裕度，改善导通电阻与耐压的平衡，实现导通电阻的降低。
另外，作为更进一步的效果，通过在源极电极50与漏极电极51之间连接第1二极管3，源极电极50与漏极电极51之间的电容变大，还能够期待开关速度的控制性提高。
在图2中，示出了栅极电阻61与MOS2及第2二极管4分别设置且与外部连接，但即使作为MOS2的内部栅极电阻，设置内部栅极电阻和外部栅极电阻双方，也能够实施。
图3示出表示使用肖特基势垒二极管的情况的第1实施方式的半导体装置1的要部截面图。在图1中，作为一例将第2二极管4作为pin二极管示出，但如图3所示，不形成p型半导体层41而使用在低浓度半导体层40与钳位电极52的界面形成肖特基结42的肖特基势垒二极管，也能够实施。
在本实施方式中，将第2二极管4设在p型钳位层30的上部，但第2二极管4只要通过钳位电极52与p型钳位层30电连接即可，其形成位置不特别限定。
（第2实施方式）
图4示出表示第2实施方式的半导体装置1的要部截面图。针对该第2实施方式的各部，与图1所示的第1实施方式的半导体装置1的各部相同的部分以相同的附图标记表示。
第2实施方式的半导体装置1与第1实施方式不同之处在于，在第2二极管4的上部设置的源极电极50的一部分，设置引出栅极电极25a的栅极电极25b，并在其下设置第1二极管3和第2二极管4。
第1二极管3和第2二极管4在半导体装置1（MOS2）的导通状态下是不流过电流的无效区域。通常，设有第1二极管3及第2二极管4的区域是无效区域，因此如本实施方式所述，通过将第1二极管3和第2二极管4设在本来就作为无效区域的栅极电极25b之下，能够减少无效区域的面积，能够减小芯片面积。
在第2实施方式中，也与第1实施方式相同，通过在半导体装置1内构成与耐压比MOS2低的第1二极管3逆串联连接的第2二极管4，即使MOS2单体的雪崩耐量较低，也能够在整体上实现高雪崩耐量。因此，能够在MOS2的n-型漂移层20设计中具有裕度，改善导通电阻与耐压的平衡，能够实现导通电阻的降低。
另外，作为更进一步的效果，通过在源极电极50与漏极电极51之间连接第1二极管3，源极电极50与漏极电极51之间的电容增大，还能够期待开关速度的控制性提高。
（第3实施方式）
图5示出表示第3实施方式的半导体装置1的要部俯视图，图6示出表示图5的X‐A‐X’线的截面的要部截面图，图7示出表示第3实施方式的变形例的半导体装置1的要部截面图。针对该第3实施方式以及第3实施方式的变形例的各部，与图1所示的第1实施方式的半导体装置1的各部相同的部分以相同的附图标记表示。
第3实施方式的半导体装置1与第1实施方式以及第2实施方式不同之处在于，将p型钳位层30彼此的间隔设置得比p型基极层22彼此的间隔大。通过采用这种构造，能够产生向p型钳位层30的下端部（p型柱层21的上端部）的电场集中，并使第1二极管3的耐压下降。
例如，如图5所示，使形成低浓度半导体层40和p型半导体层41的多晶硅等的长度y比栅极电极25的长度x长。结果，如图6所示，形成在与多晶硅等之间的p型钳位层30彼此的间隔能够比形成在与栅极电极25之间的p型基极层22彼此的间隔大。
另外，如图7所示，增大p型钳位层30下的p型柱层21彼此的形成周期，也能够产生朝向p型柱层21的上端部的电场集中，并使第1二极管3的耐压下降。
在第3实施方式中，也与第1实施方式或第2实施方式相同，通过在半导体装置1内构成与耐压比MOS2低的第1二极管3逆串联连接的第2二极管4，即使MOS2单体的雪崩耐量较低，也能够在整体上实现高雪崩耐量。因此，能够在MOS2的n-型漂移层20设计中具有裕度，改善导通电阻与耐压的平衡，能够实现导通电阻的降低。
另外，作为更进一步的效果，通过在源极电极50与漏极电极51之间连接第1二极管3，源极电极50与漏极电极51之间的电容增大，还能够期待开关速度的控制性提高。
（第4实施方式）
图8A示出表示第4实施方式的半导体装置1的要部截面图，图8B示出表示图8A所示的部分的纵向（深度方向）的杂质浓度特性的图表。在图8B中，长划线示出表示n-型漂移层20的浓度特性的图表，实线示出表示p型基极层22下的p型柱层21的浓度特性的图表，虚线示出表示p型钳位层30下的p型柱层21的浓度特性的图表。
另外，图9、图10A、图10B示出第4实施方式的变形例，图9或图10A示出半导体装置1的要部截面图，图10B示出表示图10A所示的部分的横向的杂质浓度特性的图表。针对该第4实施方式的各部，与图1所示的第1实施方式的半导体装置1的各部相同的部分以相同的附图标记表示。
第4实施方式的半导体装置1与第1～3的实施方式不同之处在于，调整了n-型漂移层20和p型柱层21的杂质浓度。
如图8所示，p型柱层21的杂质浓度具有以下特征：源极电极50侧比漏极电极51侧高。通过设为这种特性，超结构造的上下端、即p型柱层21的上下端的电场变小，能够实现雪崩耐量的增大。
进而，在本实施方式所示的构造中，使p型钳位层30下的p型柱层21的纵向（深度方向）的杂质浓度的变化比p型基极层22下的p型柱层21的纵向（深度方向）的杂质浓度的变化大。结果，能够使第1二极管3的耐压可靠地小于MOS2的漏极-源极间耐压，并提高第1二极管3的雪崩耐量。
另外，通过像这样对杂质浓度的变化赋予差异，在不需要高雪崩耐量的MOS2中，浓度变化变小。由此，有效的n-型漂移层20的杂质浓度变高，能够得到导通电阻降低的结果。另外，由于n-型漂移层20的有效的杂质浓度变高，MOS2的栅极·漏极间电容相对于漏极电压的变化变缓，能够得到不容易产生开关噪声的效果。
在图8中举例示出p型柱层21的杂质浓度的变化，但在n-型漂移层20的杂质浓度变化的情况下也能够实施。如果在漏极电极51侧n-型漂移层20的杂质浓度比p型柱层21高，且在源极电极50侧n-型漂移层20的杂质浓度比p型柱层21低，则能够得到同样的效果。
另外，如图9所示，在改变n-型漂移层20与p型柱层21的浓度差的情况下也能够实施。通常，为了增大雪崩耐量，稍微提高p型柱层21的杂质浓度是有效的。因此，优选在p型钳位层30下使p型柱层21的杂质浓度比n-型漂移层20高，在雪崩耐量较小也无妨的p型基极层22下，使p型柱层21的杂质浓度比n-型漂移层20低。
由此，能够降低MOS2的导通电阻。进而，通过在p型基极层22下提高n-型漂移层20的杂质浓度，MOS2的栅极·漏极间电容相对于漏极电压的变化变缓，能够得到不容易产生开关噪声的效果。
另外，如果只是赋予MOS2与第1二极管3的耐压差，则也可以如图10所示，使p型钳位层30下的n-型漂移层20和p型柱层21的杂质浓度比p型基极层22下的n-型漂移层20和p型柱层21的杂质浓度高。通过设置这种杂质浓度，能够使第1二极管3的耐压可靠地小于源极电极50与漏极电极51之间的MOS2的耐压。
像这样，在第4实施方式中，也与第1～3的实施方式相同，通过在半导体装置1内构成与耐量比MOS2低的第1二极管3逆串联连接的第2二极管4，即使MOS2单体的雪崩耐量较小，也能够在整体上实现雪崩耐量的增大。因此，能够在MOS2的n-型漂移层20的设计中具有裕度，改善导通电阻与耐压的平衡，能够实现导通电阻的降低。
另外，通过调整n-型漂移层20和p型柱层21的杂质浓度，能够使第1二极管3的耐压可靠地小于源极电极50与漏极电极51之间的MOS2的耐压，使MOS2的导通电阻降低，使第1二极管3的雪崩耐量增大，缓和开关噪声等。
（第5实施方式）
图11示出表示第5实施方式的半导体装置1的要部截面图，图12示出表示第5实施方式的变形例的半导体装置1的要部截面图。针对该第5实施方式以及第5实施方式的变形例的各部，与图1所示的第1实施方式的半导体装置1的各部相同的部分以相同的附图标记表示。
第5实施方式的半导体装置1与第1～4的实施方式不同之处在于，是沟槽栅极构造，且在栅极电极25之下设有埋入电极53。
如图11所示，在n-型漂移层20中设置沟槽54，在其中隔着栅极绝缘膜24设有埋入电极53。结果，能够提高n-型漂移层20的杂质浓度，能够实现导通电阻的降低。
在这种形成有埋入电极53的半导体装置1中，作为等价电路也设为与第1实施方式的图2所示的结构相同，由此能够实现雪崩耐量的增大。
埋入电极53无论与源极电极50或栅极电极25中的哪个连接都能够实施。另外，以与p型钳位层30邻接的方式形成沟槽54，隔着栅极绝缘膜24在上部设有埋入电极53a，在下部设有埋入电极53b。埋入电极53a和埋入电极53b无论与源极电极50或栅极电极25、钳位电极52中的哪个连接都能够实施。
另外，如图12所示的变形例那样，通过使与p型钳位层30邻接的沟槽54的间隔比与p型基极层22邻接的沟槽54的间隔大，能够使第1二极管3的耐压比MOS2的耐压低。结果，能够实现稳定的雪崩耐量。
另外，提高p型钳位层30下的n-型漂移层20的杂质浓度，也同样能够使第1二极管3的耐压下降。
元件终端部的构造不特别记述，在场板构造、RESURF（ReducedSURfaceField）构造、保护环构造等各种终端构造中都不受影响而能够实施。
另外，不限定于超结构造的形成工艺，无论利用反复进行离子注入和埋入结晶成长的工艺、改变加速电压而进行多次离子注入的工艺、在形成沟槽后进行埋入结晶成长的工艺等各种工艺都能够实施。
作为半导体例如能够使用硅（Si），但不限于此，使用碳化硅（SiC）、氮化镓（GaN）等化合物半导体或金刚石等宽禁带半导体也能够实施。
进而，本实施方式主要通过利用离子注入法和外延法双方的方法来制作，但仅以离子注入法或仅以外延法等也能够制作。
以上说明了几个实施方式，但这些实施方式只是举例说明，不意味着对发明的范围进行限定。这些新的实施方式能够通过其他各种方式实施。另外，在不脱离发明的主旨的范围内，能够进行各种省略、置换、变更。这些实施方式及其变形都包含在发明的范围和主旨中，并且包含在权利要求的范围所记载的发明及与其均等的范围中。

Claims (16)

1.一种半导体装置，具有场效应型晶体管、第1二极管、第2二极管和引出电极，
所述场效应型晶体管具有：
半导体基板，包括第1导电型的第1半导体层；
多个第2导电型的第2半导体层，从所述半导体基板的一方的表面侧向深度方向延伸，而且相互隔开间隔地设在所述半导体基板内；
多个第2导电型的第3半导体层，设为在所述半导体基板的一方的表面侧与一部分所述第2半导体层相接；
第1导电型的第4半导体层，选择性地形成在所述第3半导体层的表面；
控制电极，隔着绝缘膜设在所述第1半导体层、所述第3半导体层以及所述第4半导体层的表面侧；
第1主电极，与所述第3半导体层及所述第4半导体层连接；
第1导电型的第6半导体层，设在所述第1半导体层的另一方的表面；以及
第2主电极，与所述第6半导体层电连接；
所述第1二极管包括第2导电型的第5半导体层、所述第1半导体层、所述第2半导体层和所述第6半导体层而构成，该第2导电型的第5半导体层设为在所述半导体基板的一方的表面侧与一部分所述第2半导体层相接，该第1二极管与钳位电极连接，该钳位电极与所述第5半导体层连接；
所述第2二极管包括与所述控制电极连接的第7半导体层而构成，以与所述第1二极管逆串联的方式与所述钳位电极连接，以位于所述第1二极管的正上方的方式设置在所述半导体基板的一方的表面侧，
所述引出电极位于所述第2二极管的正上方，将所述控制电极和所述第7半导体层电连接。
2.如权利要求1所述的半导体装置，
所述第1二极管的耐压比所述场效应型晶体管的耐压低。
3.如权利要求1所述的半导体装置，
所述第5半导体层彼此的间隔比所述第3半导体层彼此的间隔大。
4.如权利要求1所述的半导体装置，
所述第2半导体层彼此的间隔在所述第1二极管侧比在所述场效应型晶体管侧大。
5.如权利要求1所述的半导体装置，
所述第2半导体层的杂质浓度随着从所述第2主电极侧向所述第1主电极侧靠近而变高。
6.如权利要求1所述的半导体装置，
从所述第2主电极侧向所述第1主电极侧靠近时的所述第2半导体层的杂质浓度的变化，在所述第1二极管侧比在所述场效应型晶体管侧大。
7.如权利要求1所述的半导体装置，
在所述第1二极管侧，所述第2半导体层的杂质浓度比所述第1半导体层高，在所述场效应型晶体管侧，所述第2半导体层的杂质浓度比所述第1半导体层低。
8.如权利要求1所述的半导体装置，
所述第1半导体层和所述第2半导体层的杂质浓度在所述第1二极管侧比在所述场效应型晶体管侧高。
9.如权利要求1所述的半导体装置，
所述第2二极管是肖特基势垒二极管。
10.如权利要求1所述的半导体装置，
所述第2二极管是pin二极管。
11.如权利要求1所述的半导体装置，
所述第2二极管由多晶硅构成。
12.如权利要求1所述的半导体装置，
所述钳位电极与所述第1主电极之间的耐压比所述第2主电极与所述第1主电极之间的耐压低。
13.如权利要求1所述的半导体装置，
所述第2二极管耐压比所述控制电极与所述第2主电极之间的施加保证电压高。
14.如权利要求1所述的半导体装置，
在向所述第1主电极与所述第2主电极之间施加电压时，在所述第1二极管中比所述场效应型晶体管先发生雪崩击穿，在由于栅极电阻所产生的电压下降而对所述控制电极施加的电压成为阈值电压以上时，从所述第2主电极向所述第1主电极流过电流而进行动作。
15.一种半导体装置，具有场效应型晶体管、第1二极管、第2二极管和引出电极，
所述场效应型晶体管具有：
半导体基板，包括第1导电型的第1半导体层；
多个沟槽，从所述半导体基板的一方的表面侧向深度方向延伸，而且相互隔开间隔地设在所述半导体基板内；
埋入电极，隔着栅极绝缘膜设在所述沟槽内的第2主电极侧；
控制电极，隔着所述栅极绝缘膜设在所述沟槽内的第1主电极侧；
第2导电型的第3半导体层，设在所述半导体基板的一方的表面侧；
第1导电型的第4半导体层，与所述沟槽相接，选择性地形成在所述第3半导体层的表面；
第1主电极，与所述第3半导体层和所述第4半导体层连接；
第1导电型的第6半导体层，设在所述第1半导体层的另一方的表面；以及
第2主电极，与所述第6半导体层电连接；
所述第1二极管在所述半导体基板的一方的表面侧设有第2导电型的第5半导体层，包括所述第1半导体层和所述第6半导体层而构成，与钳位电极连接，该钳位电极与所述第5半导体层连接；
所述第2二极管包括与所述控制电极连接的第7半导体层而构成，以与所述第1二极管逆串联的方式与所述钳位电极连接，以位于所述第1二极管的正上方的方式设置在所述半导体基板的一方的表面侧，
所述引出电极位于所述第2二极管的正上方，将所述控制电极和所述第7半导体层电连接。
16.如权利要求15所述的半导体装置，
所述沟槽彼此的间隔在所述第1二极管侧比在所述场效应型晶体管侧大。
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