CN104465656A - 半导体器件以及其制造方法 - Google Patents
半导体器件以及其制造方法 Download PDFInfo
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Abstract
本发明涉及半导体器件以及其制造方法。一种半导体器件包含半导体基体,该半导体基体具有第一表面和相对于第一表面的第二表面。该半导体器件进一步包含第一和第二槽,该第一和第二槽从第一表面延伸到该半导体基体中。该半导体器件进一步包含至少一个横向IGFET,该横向IGFET包含在第一表面处的第一负载端子、在第一表面处的第二负载端子和第一槽内的栅电极。该半导体器件进一步包含至少一个垂直IGFET,该垂直IGFET包括在第一表面处的第一负载端子、在第二表面处的第二负载端子和第二槽内的栅电极。
Description
背景技术
半导体技术的一种应用是具有各种传感器和保护功能的功率开关。NMOSFET(n沟道金属氧化物半导体场效应晶体管),例如常开型NMOSFET,可以被有利地集成来实现模拟电路内任何地方的电流源而不必使用电流反射镜。有利的NMOS(NMOSFET的简称)的集成对工艺变化和工艺复杂性具有影响。改进半导体技术的工艺变化和工艺复杂性是所希望的。
发明内容
根据半导体器件的实施例,该半导体器件包括半导体基体,该半导体基体具有第一表面和相对于第一表面的第二表面。该半导体器件进一步包含第一和第二槽,该第一和第二槽从第一表面延伸到该半导体基体中。该半导体器件进一步包含至少一个横向IGFET,该横向IGFET包括在第一表面处的第一负载端子、在第一表面处的第二负载端子和第一槽内的栅电极。该半导体器件进一步包含至少一个垂直IGFET(绝缘栅场效应晶体管),该垂直IGFET包括在第一表面处的第一负载端子、在第二表面处的第二负载端子和第二槽内的栅电极。
根据半导体器件的另一个实施例,该半导体器件包括半导体基体,该半导体基体具有第一表面和相对于第一表面的第二表面。该半导体器件进一步包含第一表面处的源区和漏区、在源区与漏区之间形成的沟道区和被配置为将该沟道区与邻接第二表面的区域电绝缘的绝缘区。该半导体器件进一步包含从第一表面比沟道区更深地延伸到半导体基体中并且限制沟道区的第一槽。该第一槽包括装衬第一槽的侧墙的栅电介质并且邻接栅电介质的栅电极。
根据制造半导体器件的方法的实施例,该方法包括:在半导体基体的第一部分中形成第一槽,该半导体基体具有第一表面和相对于第一表面的第二表面;并且在半导体基体的第二部分中形成第二槽。该第一和第二槽从第一表面延伸到半导体基体中。该方法进一步包含在第一部分中形成至少一个横向IGFET,该横向IGFET包括在第一表面处的第一负载端子、在第一表面处的第二负载端子和第一槽内的栅电极。该方法进一步包含在第二部分中形成至少一个垂直IGFET,该垂直IGFET包括在第一表面处的第一负载端子、在第二表面处的第二负载端子和第二槽内的栅电极。
通过阅读下面的详细描述以及通过观看附图,本领域技术人员将认识到附加的特征和优点。
附图说明
附图被包含以提供对在这里所讨论的本发明的实施例的进一步理解并且被合并到本说明书中并且构成本说明书的部分。附图图示本发明的实施例并且与描述一起用于解释本发明的原理。本发明的其它实施例和许多优点将被容易地意识到,因为它们通过参考下面的详细描述而变得更好理解。附图中的元件不必相对彼此按比例。同样的参考数字指定相应类似的部分。
图1是半导体器件的实施例的示意性平面视图。
图2是沿着剖面A-A’得到的图1中的半导体器件的横截面视图。
图3至5是横向IGEFT的依照实施例的半导体器件的部分的示意性横截面视图。
图6至9是包含横向IGFET的相邻槽之间的绝缘区的依照实施例的半导体器件的部分的示意性横截面视图。
图10图示制造半导体器件的工艺流程的实施例。
图11图示制造半导体器件的另一个工艺特征。
具体实施方式
在下面的详细描述中参考附图,附图形成本发明的部分并且在附图中通过图示的方式示出了在其中可以实施本发明的具体实施例。在不脱离本发明的范围的情况下,可以利用其它实施例并且可以做出结构的和逻辑的变化。例如,对于一个实施例所图示或所描述的特征能够被使用在其他实施例上或与其他实施例结合使用以产生又进一步的实施例。旨在本发明的各种实施例包含这样的修改和变化。示例是使用具体语言来描述的,这不应该被解释为限制所附权利要求的范围。附图不是按比例的并且仅为了图示的目的。如果不是另有声明,为清楚起见,在不同的附图中相同参考已指定相应的元件。
术语“具有”、“含有”、“包含”、“包括”等是开放的并且该术语指示所声明的结构、元件或特征的存在,但不排除附加元件或特征。
术语“接连地”、“相继地”等指示不排除被放置在有序的元件之间的附加元件的元件的未加束缚的排序。
冠词“一”、“一个”或“该”旨在包含复数以及单数,除非上下文另有清楚指示。
在本说明书中,p类型或p掺杂可以称为第一导电类型,而n类型或n掺杂被称为第二导电类型。能够用相对的掺杂关系形成半导体器件以致第一导电类型能够是p掺杂的并且第二导电类型能够是n掺杂的。此外,一些附图通过靠近掺杂类型指示“-”或“+”来图示相对的掺杂浓度。例如,“n-”意味着小于“n”掺杂区域的掺杂浓度的掺杂浓度,而“n+”掺杂区域具有比“n”掺杂区域更大的掺杂浓度。然而,除非另外声明,指示相对的掺杂浓度不意味着相同的相对掺杂浓度的掺杂区域具有相同的绝对掺杂浓度。例如,两个不同的n+区域能够具有不同的绝对掺杂浓度。例如,这同样应用到n+和p+区域。
第一导电类型可以是n或p类型,假定第二导电类型是互补的。
术语“电连接”描述在被电连接的元件之间的永久的低欧姆连接,例如经由金属和/或高掺杂的半导体的低欧姆连接或有关的元件之间的直接接触。
在这里描述的各种实施例的特征可以彼此组合,除非具体地另外注释。
图1示出半导体器件100的一个实施例的示意性平面视图。图2是如在图1中所示出的从剖面A-A’得到的半导体器件100的横截面视图。为了在横截面中半导体器件的图示目的,图2的示意性横截面视图不是真的关于图1中的线A-A’成比例的。另外,因为在不同的视图中图示半导体器件100,所以元件在这些视图的一些中可以是可见的并且由符号所指明,而相同的元件在其他的视图中可以是不可见的。因而,图1和2要被一起观察。
半导体器件100包含半导体基体200,该半导体基体200可以包含半导体衬底。半导体基体200包含半导体材料诸如硅(Si)、碳化硅(SiC)、锗(Ge)、锗化硅(SiGe)、氮化镓(GaN)或砷化镓(GaAs)。半导体基体可以包含在半导体衬底上的一个或多个可选的(一个或多个)半导体层,例如(一个或多个)外延层。在所图示的部分外,半导体基体200可以包含尤其是进一步掺杂和非掺杂的区段、外延半导体层、绝缘和导电的结构。
半导体基体200具有第一表面202和相对于第一表面202的第二表面204。半导体器件100可以包含具有至少一个横向IGFET 310的第一部分300、具有至少一个垂直IGFET 410的第二部分400和具有至少一个边缘终止结构510的边缘部分500。
在半导体器件100的第一部分300中,第一槽312从第一表面202以垂直方向延伸到半导体基体200中。在说明书中所使用的术语“垂直的”旨在描述与半导体衬底或半导体基体200的第一表面202正交布置的取向。
横向IGFET 310包含在第一表面202处的第一负载端子314、第一表面202处的第二负载端子316和第一槽312内的栅电极318。第一负载端子314可以包含在第一表面202上被连接到源区322的接触焊盘320,该源区322直接邻接第一表面202并且从第一表面202延伸到半导体基体200中。第二负载端子316可以包含被连接到漏区326的接触焊盘324,该漏区326直接邻接第一表面202并且从第一表面202延伸到半导体基体200中。在横向IGFET 310的源区322与漏区326之间形成横向IGFET 310的沟道区328。
第一负载端子314和第二负载端子316的接触焊盘320、324可以包含(一个或多个)导电材料诸如(一个或多个)金属、(一个或多个)金属合金、(一个或多个)金属硅化物、(一个或多个)高掺杂半导体,例如,高掺杂多晶硅、铝(Al)、铜(Cu)、AlSi、AlCu或AlSiCu、镍(Ni)、钛(Ti)、银(Ag)、金(Au)、铂(Pt)、钯(Pd)。接触焊盘320、324可以包含沿着到半导体基体200的界面选择性地形成的金属硅化物结构。
源区322与漏区326两者具有第一导电类型。第一导电类型可以是n类型。在源区322与漏区326之间的沟道区328可以具有第一导电类型以形成常开类型的横向IGFET 310。沟道区328还可以具有与第一导电类型相对的第二导电类型,例如p类型,以形成常关类型的横向IGFET。在沟道区328具有第一导电类型的情况下,沟道区328的净掺杂浓度可以低于源区322或漏区326的掺杂浓度。
沟道区328限制于两个相对的第一槽312之间,从而导致横向IGFET 310的横向FINFET结构。第一槽312包含栅电介质330,该栅电介质330装衬第一槽312的侧墙332并且邻接第一槽312内的栅电极318。两个相对的第一槽312的侧墙332因而面向沟道区328的侧区域以电控制经过横向IGFET 310的流经从源区322到漏区326的沟道区328的电流。
施加到栅电极318的电压控制沟道区328中的电荷载流子分布。在沟道区328具有第一导电类型的情况下,可以通过施加电压到栅电极318来降低电荷载流子浓度或耗尽沟道区328。在沟道区328具有第二导电类型的情况下,可以通过施加电压到栅电极318而在沟道区328中积累第一导电类型的电荷载流子以在源区322与漏区326之间形成导电沟道。在断开的状态下,源区322与漏区326电分离。栅电极318可以在第一表面202处被电连接到接触焊盘334。接触焊盘334可以具有与接触焊盘320、324相同的材料成分或可以由上面关于接触焊盘320、324所规定的任何材料形成。
绝缘区336被形成在半导体基体200中并且被配置为例如通过pn结隔离和/或电介质隔离来将沟道区328与邻接第二表面204的区域338电绝缘。绝缘区336可以包含阱注入区,通过在半导体基体200内相反掺杂轻掺杂外延层(例如,通过引入第二导电类型的注入杂质到邻接第一表面202的半导体基体200的预定义区段中)形成该阱注入区。在阱注入区内,可以通过相反掺杂阱注入区的预定义区段来形成源区322、沟道区328和漏区326。如果绝缘区336具有第二导电类型,绝缘区336的一部分可以直接邻接第一表面202以通过用于定义绝缘区336的电势的接触焊盘340被电耦合。
绝缘区336还可以是第二导电类型的掩埋区,并且例如可以通过深离子注入被形成或在外延生长工艺期间被形成。然而,绝缘区336还可以包含用于将源区322、沟道区328和漏区326与邻接半导体基体200的第二表面204的区域338绝缘的电介质材料。在横向侧部分处,横向IGFET 310的第一导电类型的源区322、漏区326和沟道区328也需要与衬底电隔离。为此,可以使用从第一表面202向下延伸到掩埋的绝缘区中的第二导电类型的阱或闭合的槽环(未示出)。可以通过接触焊盘340接触这个阱。可以通过第一槽312进一步提供在横向方向上源区322、沟道区328和漏区326的电隔离。
在第一部分300中,靠近横向IGFET 310提供横向IGFET的边缘终止结构360以确保横向IGFET 310的电压阻断能力。在这里,横向IGFET 310由终止槽362伴随,该终止槽362包括装衬终止槽362的侧墙366的电介质层364和终止槽362内的邻接电介质层364的场电极368。可以通过接触焊盘370电耦合横向IGFET的边缘终止结构360的场电极368。
在半导体基体200的第二部分400中形成第二槽412,该第二槽412从第一表面202在垂直方向上延伸到半导体基体200中。第二槽412可以与第一槽312具有相同的深度并且可以通过例如各向异性的蚀刻工艺诸如干法蚀刻被同时地形成。术语“相同的深度”包括由同时处理的槽的槽处理诸如RIE(反应离子蚀刻)滞后所引起的槽深度中的小的变化。由此,能够避免横向IGFET 310的栅结构的分离处理,并且因而节省一个注入掩模层,导致简化的和成本有效的处理。
在图1中所图示的第二槽412沿着横向方向平行地延伸。第二槽412的几何形状的进一步示例包含岛状和多边形的形状。
建立横向IGFET 310的沟道区328所需的台面宽度可以小于垂直IGFET 410的台面宽度。横向IGFET 310的沟道台面还可能不足够宽以允许在顶上的直接电接触。因而,横向IGFET 310的台面区域可以在沟道区328的外面被加宽以在源区322的顶上和在漏区326的顶上放置接触。结果,一个共同的栅槽结构能够被用于垂直IGFET 410和横向IGFET结构310,即常开型的FINFET器件能够被集成到CMOS-DMOS技术中。
因而,在沟道区328处的两个相对的第一槽312之间的距离可以比在源区322处或在漏区326处的两个相对的第一槽312更低。这允许狭窄的沟道部分328并且同时使依靠例如接触焊盘320和324能够容易接触源区322和漏区326。依赖于沟道区328中的掺杂浓度,在两个相对的第一槽312之间限制沟道区328的距离可以小于2μm、或小于500nm、或小于200nm、或甚至小于50nm。在横向IGFET 310的沟道区328处的两个相对的第一槽312之间的距离可以低于在垂直IGFET 410的基体区428处的两个相对的第二槽412之间的距离。在沟道区328处的两个相对的第一槽312之间的距离可以是在基体区428处的两个相对的第二槽412之间的距离的20%至80%。
第二部分400内的该至少一个垂直IGFET 410包含在半导体基体200的第一表面202处的第一负载端子414、第二表面204处的第二负载端子416和第二槽412内的栅电极418。垂直IGFET 410的第一负载端子414可以包含被电连接到源区422的第一接触焊盘420。第二负载端子416可以包含被电连接到邻接第二表面204的共同漏区426的第二接触焊盘424。源区422和共同漏区426具有第一导电类型。在源区422和共同漏区426之间形成基体区428,该基体区428具有第二导电类型。栅电介质430将垂直IGFET 410的栅电极418从基体区428中分离。栅电介质430装衬第二槽412的侧墙432。第一槽412内的栅电极418邻接垂直IGFET 410的栅电介质430的内侧。栅电极418可以包含导电材料,例如,高掺杂半导体材料诸如多晶硅、(一个或多个)金属和/或(一个或多个)金属合金。
施加到栅电极418的电压控制沿着栅电介质430的基体区428的沟道部分中的电荷载流子分布。在开通的状态下,第一导电类型的电荷载流子在邻接槽412的侧墙432和栅电介质430的沟道部分中积累,并且在源区422和漏区426之间形成导电沟道。在断开的状态下,基体区428将源区422从漏区426中电分离。基体区428可以通过基体接触区434被电连接,该基体接触区434被电连接到基体接触焊盘436。在共同漏区426和基体区428之间形成第一导电类型的漂移区438。栅电极418可以经由接触焊盘440被电耦合,该接触焊盘440可以包含与上面提到的接触焊盘320、324、334、340、420或436相同的材料或材料成分。
在半导体基体200的第三部分500中形成第三槽512,并且该第三槽512包括装衬第三槽512的侧墙516的场电介质514和邻接第三槽512内的场电介质514的边缘终止电极518。形成具有比栅电介质更高的厚度的场电介质514。第三槽512与边缘终止电极518一起可以以环状的形状围绕横向IGFET 310和垂直IGFET 410的单元阵列。还有可能的是,第三槽510仅围绕垂直IGFET 410阵列。此外,第三槽512还能够位于垂直IGFET 412阵列的两个相对侧部分,从而平行于第二槽412。在这里,第二槽412可以包含它们末端部分处邻接相应的栅结构的场电介质结构。可以依靠接触焊盘520将边缘终止电极518电耦合。如果(例如,通过各向异性蚀刻)与第一和第二槽312、412同时形成第三槽512,则它们可以具有与第一槽312和第二槽412可比较的深度。
在下面,横向IGFET 310的栅结构的不同实施例将被描述,其在与图6至9组合的图3至5中被图示。在这里,图3至5是与图2的横截面视图可比较的半导体器件100的部分的详细的横截面视图。
如在图3中所示出,通过沟道区328上的栅电极桥342连接两个相对的第一槽312的栅电极318。例如,可以依靠顶栅电介质344将沟道区328从栅电极桥342中分离。通过采用沟道区328上的栅电极桥342,施加到栅电极318的电压可以进一步引发从第一表面202到沟道区328中的电场以支持或改进控制沟道区328中的电荷载流子分布。
因为在图2或图3至图5中所示出的所得到的栅结构与FINFET栅结构可比较,所以横向IGFET 410具有带有非常小的体效应的对有源沟道的全栅控制。结果,阈值电压比在常规的耗尽型MOSFET器件中更少依赖于沟道/基体区域的掺杂水平。因而,横向IGFET 310与平面耗尽型MOSFET相比具有基本上更小的阈值电压的工艺变化。
如在图4中所示出,在另一个实施例中,栅电极318可以被掩埋在第一表面202下面。为了改进横向IGFET 310的夹断性质,横向IGFET 310的沟道区328还可以被掩埋在第一表面202下面并且面向掩埋的栅电极层318。沟道绝缘区346直接邻接第一表面202并且在垂直方向上延伸到半导体基体200中至少到掩埋的栅电极318的深度,以保证在横向方向上通过栅电极318对沟道区328的有效栅控制。根据一个实施例,沟道绝缘区346包含电介质。根据另一个实施例,沟道绝缘区346具有与沟道区328的导电类型相对的第二导电类型,由此提供pn结隔离。
在图5中所图示的进一步实施例中,栅电极桥348可以被形成在沟道区328上并且通过第一槽312中的电介质与掩埋的栅电极318分离。可以在沟道区328与栅电极桥348之间形成进一步电介质栅层350来将栅电极桥348与沟道区328电分离。
在图3至5中,仅示出横向IGFET 310的栅结构的上部分,而可以形成包含第一槽312的栅结构的下部分,如在图6至9中的任何一个中所示出。
图6图示在图2的横截面视图中所示出的栅结构的一个实施例。第一槽312延伸经过绝缘区336到邻接第二表面202的区域338中。因为第一槽312可以具有与第二槽412相同的深度,所以第二槽412可以充当垂直IGFET 410的漂移区438内的场板槽。
在图7中所图示的进一步实施例中,绝缘区336内的槽312末端仅仅比沟道区328从第一表面202更深地延伸到半导体基体200中并且限制沟道区328。因而,横向IGFET 310的槽312不需要是场板槽,如在图6中所示出。该槽还可以是标准的槽MOSFET或DMOSFET器件的简单的栅槽。在这个例子中,绝缘区336在槽312下面延伸并且到台面区域中使得保证沟道区328与区域338之间的电隔离。
如在图8中所示出,第一槽312进一步包含第一槽312的下部分处的场电介质352。场电介质352比栅电介质330更厚。因为在下部分中第二槽412可以具有与第一槽312相同的内部结构,所以该下部分可以充当垂直IGFET 410中的场板。在图8的结构中,第一槽312延伸经过绝缘区336,其可以与第二部分400中的基体区域428延伸到相同的深度到半导体基体200中并且其可以被同时处理。
如在图9中所图示,第一槽312可以进一步包含栅电极318下面的场电极354,栅电极318通过电介质层与场电极354电分离。在第一部分300中场电极354可以被电连接到源区322或到基体区,以便阻止经过绝缘区336的结隔离区的寄生电流或换句话说以便抑制垂直寄生双极型晶体管。然而,还可能的是,将场电极354连接到栅电极318,以便改进横向IGFET 310在其下部分中的栅控制。因为在下部分中第二槽412可以具有与第一槽312相同的内部结构,所以在第二部分440中场电极354可以被接触到垂直IGFET 410的源区422,从而充当所谓的源多(source-poly)电极。
在上面的实施例中,电介质330、430、364、514、350或352可以包含(一个或多个)隔离材料诸如氧化硅和/或氮化硅。电极318、318、418、518可以包含导电材料,例如,高掺杂半导体材料诸如高掺杂多晶硅、(一个或多个)金属和/或(一个或多个)金属合金。共同的漏区426可以是高掺杂半导体衬底,例如,n+掺杂或n++掺杂,其可以从第二表面204通过离子注入被形成。在这里,邻接第二表面的区域338可以具有与漏区426和漂移区域438相同的层结构和净掺杂轮廓。漂移区域438可以是n+掺杂的。另外,例如由于在不同区域中同时处理,基体区428和绝缘区336可以具有相同的层结构和相同的净掺杂轮廓。基体区428和绝缘区336可以是p掺杂的。此外,源区322、422和漏区326可以被同时处理并且具有相同的净掺杂浓度。源区322、422和漏区326可以n+掺杂。槽312、412、362和512的至少内部结构可以是类似的,并且它们中的至少部分可以被同时处理。槽312、412、362和512可以通过各向异性蚀刻被同时形成,导致槽312、412、362和512具有相同的深度。通过同时处理横向IGFET 310和垂直IGFET 410的部分,能够降低工艺和/或掩模步骤的数量,从而改进生产的效率和成本。
图10图示制造半导体器件的方法的示意性工艺流程。工艺特征S100包含:在半导体基体的第一部分300中形成第一槽312,该半导体基体具有第一表面和相对于第一表面的第二表面;并且在半导体基体的第二部分中形成第二槽。由此,第一和第二槽以这样的方式被形成:它们从第一表面延伸到半导体基体中并且具有相同的深度。工艺特征S110包含在第一部分中形成至少一个包括在第一表面处的第一负载端子、在第一表面处的第二负载端子和第一槽内的栅电极的横向IGFET。工艺特征S130包含在第二部分中形成至少一个包括在第一表面处的第一负载端子、在第二表面处的第二负载端子和第二槽内的栅电极的垂直IGFET。
根据实施例,制造半导体器件的方法进一步包括工艺特征S140,该工艺特征S140包含形成配置为将在第一部分中的至少一个横向IGFET与邻接第二表面的区域电绝缘的绝缘区。
第一槽和第二槽可以被同时处理。
总之,通过充当FINFET器件的横向IGFET 310来代替常规的平面耗尽型MOSFET器件。用结构的元件来构建FINFET器件,该结构的元件已经可用于处理其他器件,例如,在具有场板槽DMOS器件的CMOS-DMOS(互补金属氧化物半导体-双扩散金属氧化物半导体)技术中。典型地,用这样一种技术的器件被实现在n+衬底的顶上的n类型外延区域内。于是,FINFET器件310的沟道区328是在两个有源场板槽312之间的n掺杂的硅台面。这些槽312包括侧墙332上的栅氧化物330和多晶硅栅电极318。在DMOS器件410中,这被用来控制垂直MOS沟道。在FINFET器件310中,沟道328是横向的。通过336将它与衬底隔离。在现代的CMOS-DMOS技术中,掩埋的p区域已经可用于并且被用来构建用于隔离的PMOS(p沟道金属氧化物半导体)器件的隔离的n阱。通过在台面区域的顶上横向隔开的n+接触320、324来提供FINFET 310的源区322和漏区326。
虽然在这里已图示和描述了具体实施例,但是本领域普通技术人员将意识到的是,在不脱离本发明范围的情况下,各种替代和/或等同的实现可以代替示出和描述的具体的实施例。本申请旨在覆盖在这里讨论的具体实施例的任何改变或变化。因此,本发明旨在仅由权利要求及其等同物限制。
Claims (20)
1.一种半导体器件,包括:
半导体基体,具有第一表面和相对于所述第一表面的第二表面;
第一槽和第二槽,从所述第一表面延伸到所述半导体基体中;
至少一个横向IGFET,包括在第一表面处的第一负载端子、在第一表面处的第二负载端子和第一槽内的栅电极;以及
至少一个垂直IGFET,包括在第一表面处的第一负载端子、在第二表面处的第二负载端子和第二槽内的栅电极。
2.权利要求1的所述半导体器件,其中所述第一槽和所述第二槽具有相同的深度。
3.权利要求1的所述半导体器件,其中横向IGFET的沟道区被限制在被相对彼此布置的第一槽的两个之间。
4.权利要求3的所述半导体器件,其中在横向IGFET的沟道区处的两个相对布置的第一槽之间的距离小于在横向IGFET的源区处或漏区处的两个相对布置的第一槽之间的距离。
5.权利要求3的所述半导体器件,其中在横向IGFET的沟道区处的两个相对布置的第一槽之间的距离小于被相对彼此布置并且限制垂直IGFET的基体区的第二槽的两个之间的距离。
6.权利要求1的所述半导体器件,其中横向IGFET是常开型器件。
7.权利要求1的所述半导体器件,进一步包括邻接第三槽内的场电介质的边缘终止电极。
8.权利要求1的所述半导体器件,其中第一和第二槽中的至少一个进一步包括在所述第一和第二槽中的至少一个的下部分的场电介质,所述场电介质比装衬所述第一和第二槽中的至少一个的侧墙的栅电介质更厚。
9.一种半导体器件,包括:
半导体基体,具有第一表面和相对于所述第一表面的第二表面;
所述第一表面处的源区和漏区;
在所述源区与所述漏区之间形成的沟道区;
绝缘区,被配置为将所述沟道区与邻接第二表面的区域电绝缘;以及
第一槽,从所述第一表面比所述沟道区更深地延伸到所述半导体基体中并且限制所述沟道区,所述第一槽包括装衬第一槽的侧墙的栅电介质并且进一步包括邻接所述栅电介质的栅电极。
10.权利要求9的所述半导体器件,其中被相对彼此布置的第一槽的两个之间的距离在沟道区处比在所述源区处或所述漏区处更小。
11.权利要求9的所述半导体器件,其中被相对彼此布置的第一槽的两个的栅电极通过所述沟道区上的栅电极桥被连接。
12.权利要求9的所述半导体器件,其中所述栅电极被掩埋在所述第一表面下面。
13.权利要求12的所述半导体器件,其中所述沟道区被掩埋在所述第一表面下面并且面向掩埋的栅电极。
14.权利要求11的所述半导体器件,其中沟道区上的栅电极桥通过所述第一槽中的电介质与掩埋的栅电极分离。
15.权利要求9的所述半导体器件,进一步包括至少一个垂直IGFET,所述至少一个垂直IGFET包括在第一表面处的第一负载端子、在第二表面处的第二负载端子和邻接装衬从所述第一表面延伸到半导体基体中的第二槽的侧墙的栅电介质的栅电极。
16.权利要求15的所述半导体器件,其中第一和第二槽中的至少一个进一步包括在所述第一和第二槽中的至少一个的下部分的场电介质,所述场电介质比所述栅电介质更厚。
17.一种制造半导体器件的方法,包括:
在半导体基体的第一部分中形成第一槽,所述半导体基体具有第一表面和相对于第一表面的第二表面,并且在半导体基体的第二部分中形成第二槽,第一和第二槽从第一表面延伸到半导体基体中;
在第一部分中形成至少一个横向IGFET,所述横向IGFET包括在第一表面处的第一负载端子、在第一表面处的第二负载端子和第一槽内的栅电极;以及
在第二部分中形成至少一个垂直IGFET,所述垂直IGFET包括在第一表面处的第一负载端子、在第二表面处的第二负载端子和第二槽内的栅电极。
18.权利要求17的所述制造半导体器件的方法,进一步包括形成绝缘区,所述绝缘区被配置为将在第一部分中的至少一个横向IGFET与邻接第二表面的区域电绝缘。
19.权利要求18的所述制造半导体器件的方法,其中所述绝缘区是半导体区域,所述半导体区域被配置为提供相对于相对导电类型的周围的半导体区域的结隔离。
20.权利要求17的所述制造半导体器件的方法,其中所述第一槽和所述第二槽被同时处理。
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