CN107026203B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN107026203B
CN107026203B CN201610983600.3A CN201610983600A CN107026203B CN 107026203 B CN107026203 B CN 107026203B CN 201610983600 A CN201610983600 A CN 201610983600A CN 107026203 B CN107026203 B CN 107026203B
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CN107026203A (zh
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千大焕
郑永均
周洛龙
朴正熙
李钟锡
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Hyundai Motor Co
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Abstract

本公开涉及半导体器件及其制造方法。一种半导体器件包括：第一n‑型层和第二n‑型层，顺次布置在n+型碳化硅基板的第一表面上；第一沟槽和第二沟槽，布置在第二n‑型层处并且彼此分隔开；p型区域，围绕第一沟槽的侧表面和下表面；n+型区域，布置在p型区域和第二n‑型层上；栅极绝缘层，布置在第二沟槽中；栅电极，布置在栅极绝缘层上；氧化层，布置在栅电极上；源电极，布置在氧化层和n+型区域上且布置在第一沟槽中；以及漏极，布置在n+型碳化硅基板的第二表面处。

Description

半导体器件及其制造方法
相关申请的交叉引证
本申请要求于2015年12月14日提交至韩国知识产权局的韩国专利申请第10-2015-0178095号的优先权的权益，通过引证方式将其全部内容结合于此。
技术领域
本公开内容涉及包括碳化硅(SiC)的半导体器件及其制造方法。
背景技术
功率半导体器件通常需要低导通电阻或者低饱和电压来减小当大量电流流动时的导电状态下的功率损耗。此外，功率半导体器件需要在其PN结处经受反向高压的特征，当功率半导体器件关闭或者当开关断开时，反向高压可能被施加至功率半导体器件的相对端以使功率半导体器件具有高击穿电压的特征。
当基本上满足电气条件和物理条件的各种功率半导体器件被封装为一个模块中时，封装模块中所包括的半导体器件的数目及其电气规范可以根据系统要求的条件而改变。
通常，三相功率半导体模块被用于生成驱动电动机的洛仑兹力(Lorentz force)。即，三相功率半导体模块控制施加至电动机的电流和功率，使得确定电动机的驱动状态。
虽然这种三相半导体模块中已包括并使用常规的硅绝缘栅双极晶体管(IGBT)和硅二极管，但是三相半导体模块近年来趋向于包括碳化硅(SiC)金属氧化物半导体场效应晶体管(MOSFET)和碳化硅二极管以使其中的功率消耗最小化并且提高其切换速度。
当硅IGBT或者碳化硅MOSFET被连接至单独的二极管时，需要多条导线用于连接。因为由于存在多条导线而出现寄生电容和电感，所以模块的切换速度可能降低。
在该背景技术部分中公开的以上信息仅仅是用于增强对本发明背景技术的理解，并且因此它可能包含不构成对于本领域普通技术人员而言在本国中已经已知的现有技术的信息。
发明内容
本公开内容致力于提供执行MOSFET操作和二极管操作的碳化硅半导体器件。
根据本公开内容的实施方式，半导体器件包括：第一n-型层和第二n-型层，顺次布置在n+型碳化硅基板的第一表面上；第一沟槽和第二沟槽，布置在第二n-型层处并且彼此分隔开；p型区域，围绕第一沟槽的侧表面和下表面；n+型区域，布置在p型区域和第二n-型层上；栅极绝缘层，布置在第二沟槽中；栅电极，布置在栅极绝缘层上；氧化层，布置在栅电极上；源电极，布置在氧化层以及n+型区域上并且布置在第一沟槽中；以及漏极，布置在n+型碳化硅基板的第二表面处。
第二n-型层的掺杂浓度可以不同于第一n-型层的掺杂浓度(dopingconcentration)。
第二n-型层可以布置在第二沟槽与p型区域之间。
半导体器件可以进一步包括p+型区域，该p+型区域布置在第一沟槽的下表面与p型区域之间。
源电极可以接触被布置在第一沟槽下面的p+型区域。
源电极和漏极可包括欧姆金属(ohmic metal)。
第二n-型层的掺杂浓度可以等于第一n-型层的掺杂浓度。
根据本公开内容的另一实施方式，半导体器件的制造方法包括：在n+型碳化硅基板的第一表面上顺次形成第一n-型层和第二n-型层；在第二n-型层上形成n+型区域；通过蚀刻n+型区域和第二n-型层形成彼此分隔开的第一沟槽和第二沟槽；围绕第一沟槽的侧部和下部形成p型区域；在第一沟槽的下表面与p型区域之间形成p+型区域；在第二沟槽中形成栅极绝缘层；在栅极绝缘层上形成栅电极；在栅电极上形成氧化层；在氧化层和n+型区域上、并且在第一沟槽上形成源电极；并且在n+型碳化硅基板的第二表面处形成漏极，其中，源电极可以接触被布置在第一沟槽下面的p+型区域。
在形成p型区域的过程中，可以通过倾斜离子注入方法注入p离子。
根据本公开内容中的实施方式，因为半导体器件可以执行MOSFET操作和二极管操作，所以半导体器件不需要具有连接MOSFET设备和二极管设备的导线。因此，半导体器件的尺寸可以减小。
此外，根据本公开内容中的实施方式，因为一个半导体器件在没有导线的情况下可以执行MOSFET操作和二极管操作，所以半导体器件的切换速度可以得到提高。
附图说明
图1示出根据本公开内容中的示例性实施方式的半导体器件的示意性截面图。
图2至图4分别示出图1的半导体器件的操作的示意图。
图5至图9分别示出图1的半导体器件的制造方法的示意性截面图。
具体实施方式
在下文中，将参照附图更全面地描述本公开内容，在附图中示出了本公开的示例性实施方式。然而，应当理解本公开内容不限于所公开的实施方式，而是与之相反旨在覆盖各种变形。正如本领域的普通技术人员将认识到的，所描述的实施方式可以以各种不同的方式进行变形，所有这些都不偏离本公开内容的精神或范围。
在附图中，为清晰起见，放大了层、膜、面板、区域等的厚度。将理解的是，当诸如层、膜、区域或基板的元件被称为“在”另一个元件“之上”时，该元件可直接在另一个元件上或者还可以存在中间元件。
图1示出根据本公开内容中的示例性实施方式的半导体器件的示意性截面图。
参考图1，根据本公开内容的半导体器件包括n+型碳化硅基板100、第一n-型层200、第二n-型层250、p型区域300、p+型区域350、n+型区域500、栅电极700、源电极800以及漏极900。
第一n-型层200和第二n-型层250顺次布置在n+型碳化硅基板100的第一表面上。第二n-型层250的掺杂浓度不同于第一n-型层200的掺杂浓度。即，第二n-型层250的掺杂浓度可以小于或者大于第一n-型层200的掺杂浓度。然而，本公开内容不限于此，并且第二n-型层250的掺杂浓度可以等于第一n-型层200的掺杂浓度。
彼此分隔开的第一沟槽410和第二沟槽420被布置在第二n-型层250处。因此，第二n-型层250被布置在第一沟槽410与第二沟槽420之间。
p型区域300被布置在第一沟槽410的侧部及下部并且围绕第一沟槽410的侧部和下部。p+型区域350被布置在p型区域300与第一沟槽410的下部之间。
n+型区域500布置在p型区域300和第二n-型层250上。
栅极绝缘层600布置在第二沟槽420中。栅电极700布置在栅极绝缘层600上。氧化层610布置在栅电极700上。氧化层610覆盖栅电极700的侧表面。
源电极800布置在n+型区域500和氧化层610上并且在第一沟槽410中。源电极800在第一沟槽410的下表面处接触p+型区域350，在第一沟槽410的侧表面处接触p型区域300。漏极900布置在n+型碳化硅基板100的第二表面处。本文中，源电极800和漏极900可分别包括欧姆金属。n+型碳化硅基板100的第二表面是n+型碳化硅基板100的第一表面的相对表面。
根据本公开内容的半导体器件执行金属氧化物半导体场效应晶体管(MOSFET)操作和二极管操作。在这种情况下，MOSFET操作和二极管操作根据所施加的电压而被分开执行。
现在将参照图2至图4描述半导体器件的操作。
图2至图4分别示出图1的半导体器件的操作的示意图。
图2示出图1的半导体器件关闭的断开状态。图3示出图1的半导体器件的二极管操作状态。图4示出根据图1的MOSFET操作状态。
半导体器件在以下条件下被关闭。
VGS<VTH,VDS≥0V
在以下条件下执行半导体器件的二极管操作。
VGS<VTH,VDS<0V
在以下条件下执行半导体器件的MOSFET操作。
VGS≥VTH,VDS>0V
在此，VTH是MOSFET的阈值电压，VGS是(VG-VS)，并且VDS是(VD-VS)。VG是施加至栅电极的电压，VD是施加至漏极的电压以及VS是施加至源电极的电压。
参考图2，当半导体器件关闭时，耗尽层50形成为全部覆盖第二n-型层250并且几乎覆盖第一n-型层200，使得没有出现电流流动。
参考图3，当半导体器件执行二极管操作时，电子(e-)从漏极900移动至源电极800。从漏极900输出的电子(e-)通过第一n-型层200和第二n-型层250移动至源电极800。在这种情况下，耗尽层50形成在p型区域300的侧部和下部的第一n-型层200和第二n-型层250处。
参考图4，当半导体器件执行MOSFET操作时，电子(e-)从源电极800移动至漏极900。从源电极800输出的电子(e-)通过第二n-型层250和第一n-型层200移动至漏极900。在这种情况下，耗尽层50形成在p型区域300的侧部和下部的第一n-型层200和第二n-型层250处。本文中，第二n-型层250的掺杂浓度可以大于第一n-型层200的掺杂浓度。形成在p型区域300的下部处的耗尽层50的面积大于形成在p型区域300的侧部处的耗尽层50的面积。
因而，因为根据本公开内容的半导体器件执行MOSFET操作和二极管操作，所以不需要用于连接一般的MOSFET设备和二极管设备的导线。因此，可以减小半导体器件的尺寸。
此外，因为一个半导体器件在没有导线的情况下可以执行MOSFET操作和二极管操作，所以半导体器件的切换速度可以得到提高。
在下文中，将参考表1比较并描述根据本公开内容的半导体器件、一般的二极管设备以及一般的MOSFET设备的特性。
表1表示根据本公开内容的半导体器件、一般的二极管设备以及一般的MOSFET设备的各自的模拟结果。
比较例1是一般的二极管设备以及比较例2是一般的MOSFET设备。比较例3是半导体器件执行MOSFET操作和二极管操作的一种，其中，栅电极是没有布置在沟槽处而是在源电极侧面处的平面栅电极。
在表1中，在对相应的半导体器件施加基本上相同的击穿电压的状态下对比较例1、比较例2和比较例3的各自的半导体器件的电流密度进行比较。
(表1)
Figure BDA0001148564030000081
参考表1，相对于约100A的电流量，根据比较例1的二极管设备的导电面积约是0.33cm2以及根据比较例2的MOSFET设备的导电面积约是0.20cm2。当半导体器件的电流量约是100A时，根据比较例1和比较例2的导电面积的总和约是0.53cm2。
当二极管操作以约100A的电流量执行时，根据比较例3的半导体器件的导电面积约是0.50cm2。在根据比较例3的半导体器件的情况下，当半导体器件的面积约是0.50cm2时，可以看出其在二极管操作期间的电流量约是100A并且其在MOSFET操作期间的电流量约是385A。
根据示例性实施方式，在二极管操作期间，对于约100A的电流量的导电面积约是0.45cm2。在半导体器件的面积约是0.45cm2时，可以看出其在二极管操作期间的电流量约是100A并且其在MOSFET操作期间的电流量约是488.7A。
即，在相对于约100A的电流量的导电面积中，可以看出根据示例性实施方式的半导体器件的对应面积相对于根据比较例1和2的半导体器件的对应面积的总和减少约15％。另外，可以看出根据示例性实施方式的半导体器件的对应面积相对于根据比较例3的半导体器件的对应面积减少约10％。
在下文中，将参考图5至图9以及图1描述在图1中示出的半导体器件的制造方法。
图5至图9分别示出图1的半导体器件的制造方法的示意性截面图。
参考图5，制备n+型碳化硅基板100，通过外延生长在n+型碳化硅基板100的第一表面处形成第一n-型层200，并且然后通过外延生长在第一n-型层200上形成第二n-型层250。第二n-型层250的掺杂浓度不同于第一n-型层200的掺杂浓度。即，第二n-型层250的掺杂浓度可以小于或者大于第一n-型层200的掺杂浓度。然而，本公开内容不限于此，并且第二n-型层250的掺杂浓度可以等于第一n-型层200的掺杂浓度。
参考图6，n+型区域500形成在第二n-型层250上。n+型区域500可以通过在第二n-型层250上注入n+离子而形成或者可以通过外延生长而形成在第二n-型层250上。
参考图7，通过蚀刻n+型区域500和第二n-型层250形成第一沟槽410和第二沟槽420。在这种情况下，第一沟槽410和第二沟槽420同时形成。
参考图8，通过将p离子注入第一沟槽410的侧表面和下表面形成p型区域300，并且然后通过将p+离子注入第一沟槽410的下表面形成p+型区域350。在这种情况下，p型区域300形成为围绕第一沟槽410的侧表面和下表面。另外，p+型区域350形成在p型区域300与第一沟槽410的下部之间。在这种情况下，通过倾斜离子注入方法注入p离子。倾斜离子注入方法是具有相对于水平表面比直角更小的注入角度的方法。
参考图9，在栅极绝缘层600形成在第二沟槽420之后，在栅极绝缘层600上形成栅电极700，并且然后在栅电极700上形成氧化层。
参考图1，源电极800形成在氧化层610和n+型区域500上和第一沟槽410处，并且漏极900形成在n+型碳化硅基板100的第二表面处。
在根据本公开内容的半导体器件的制造方法中，在同时形成第一沟槽410和第二沟槽420之后，可以形成p型区域300和p+型区域350。在特定实施方式中，在首先形成第一沟槽410之后，可以形成p型区域300和p+型区域350并且然后可以形成第二沟槽420。
虽然已经结合目前被认为是实用的示例性实施方式的示例描述了本发明，但是将要理解的是，本发明不局限于所公开的实施方式，而与此相反的是，本发明旨在覆盖包含于所附权利要求的精神和范围内的各种变形和等同布置。

Claims (11)

1.一种半导体器件，包括：
第一n-型层和第二n-型层，顺次布置在n+型碳化硅基板的第一表面上；
第一沟槽和第二沟槽，布置在所述第二n-型层处并且彼此分隔开；
p型区域，围绕所述第一沟槽的侧表面和下表面；
n+型区域，布置在所述p型区域和所述第二n-型层上；
栅极绝缘层，布置在所述第二沟槽中；
栅电极，布置在所述栅极绝缘层上；
氧化层，布置在所述栅电极上；
源电极，布置在所述氧化层和所述n+型区域上并且布置在所述第一沟槽中；以及
漏电极，布置在所述n+型碳化硅基板的第二表面处，
其中，当所述半导体器件关闭时形成在所述第一n-型层和第二n-型层中的耗尽层的面积大于当所述半导体器件执行MOSFET操作时形成在所述第一n-型层和第二n-型层中的耗尽层的面积。
2.根据权利要求1所述的半导体器件，其中，
所述第二n-型层的掺杂浓度不同于所述第一n-型层的掺杂浓度。
3.根据权利要求2所述的半导体器件，其中，
所述第二n-型层布置在所述第二沟槽与所述p型区域之间。
4.根据权利要求3所述的半导体器件，进一步包括：
p+型区域，布置在所述第一沟槽的下表面与所述p型区域之间。
5.根据权利要求4所述的半导体器件，其中，
所述源电极接触被布置在所述第一沟槽下面的所述p+型区域。
6.根据权利要求1所述的半导体器件，其中，
所述源电极和所述漏电极中的每一个包括欧姆金属。
7.根据权利要求1所述的半导体器件，其中，
所述第二n-型层的掺杂浓度等于所述第一n-型层的掺杂浓度。
8.一种半导体器件的制造方法，所述制造方法包括以下步骤：
在n+型碳化硅基板的第一表面上顺次形成第一n-型层和第二n-型层；
在所述第二n-型层上形成n+型区域；
通过蚀刻所述n+型区域和所述第二n-型层形成彼此分隔开的第一沟槽和第二沟槽；
形成p型区域以围绕所述第一沟槽的侧部和下部；
在所述第一沟槽的下表面与所述p型区域之间形成p+型区域；
在所述第二沟槽中形成栅极绝缘层；
在所述栅极绝缘层上形成栅电极；
在所述栅电极上形成氧化层；
在所述氧化层和所述n+型区域上并且在所述第一沟槽中形成源电极；并且
在所述n+型碳化硅基板的第二表面处形成漏电极，
其中，所述源电极接触被布置在所述第一沟槽下面的所述p+型区域，以及
其中，当所述半导体器件关闭时形成在所述第一n-型层和第二n-型层中的耗尽层的面积大于当所述半导体器件执行MOSFET操作时形成在所述第一n-型层和第二n-型层中的耗尽层的面积。
9.根据权利要求8所述的制造方法，其中，
所述第二n-型层的掺杂浓度不同于所述第一n-型层的掺杂浓度。
10.根据权利要求9所述的制造方法，其中，在形成所述p型区域的过程中，
通过倾斜离子注入来注入p离子。
11.根据权利要求8所述的制造方法，其中，
所述第二n-型层的掺杂浓度等于所述第一n-型层的掺杂浓度。
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