JP2013077656A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2013077656A JP2013077656A JP2011215726A JP2011215726A JP2013077656A JP 2013077656 A JP2013077656 A JP 2013077656A JP 2011215726 A JP2011215726 A JP 2011215726A JP 2011215726 A JP2011215726 A JP 2011215726A JP 2013077656 A JP2013077656 A JP 2013077656A
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Abstract
アバランシェ耐量の増大と、オン抵抗の低減とを兼ね備えた半導体装置を提供することである。
【解決手段】
実施形態の半導体装置は、第1半導体層を含む半導体基板と、前記半導体基板内に設けられた複数の第2半導体層と、前記半導体基板の一方の表面側に設けられた複数の第3半導体層と、前記第3半導体層の表面に選択的に形成された第4半導体層と、前記第4半導体層の表面側に設けられた制御電極と、前記第1半導体層の他方の表面に設けられた第6半導体層とを有するMOSと、前記半導体基板の一方の表面側に設けられた第5半導体層と、前記第1半導体層と、前記第2半導体層と、前記第6半導体層を含んで構成され、前記第5半導体層に接続するクランプ電極に接続された第1ダイオードと、前記制御電極に接続された第7半導体層を含んで構成され、前記第1ダイオードと逆直列になるように前記クランプ電極に接続された第2ダイオードとを有する。
【選択図】図1
Description
図1は第1の実施形態を示す半導体装置1の要部断面図を示しており、図2はその半導体装置1の等価回路図を示している。
図4は、第2の実施形態を示す半導体装置1の要部断面図を示している。この第2の実施形態の各部について、図1に示す第1の実施形態の半導体装置1の各部と同一部分は同一符号で示す。
図5は第3の実施形態を示す半導体装置1の要部平面図、図6は図5のX‐A‐X’線における断面を示す要部断面図、図7は第3の実施形態の変形例を示す半導体装置1の要部断面図をそれぞれ示している。この第3の実施形態及び第3の実施形態の変形例の各部について、図1に示す第1の実施形態の半導体装置1の各部と同一部分は同一符号で示す。
図8の(a)は第4の実施形態を示す半導体装置1の要部断面図であり、(b)は(a)に示す部分の縦方向(深さ方向)の不純物濃度プロファイルを示すグラフを示している。図8(b)において長鎖線はn−型ドリフト層20の濃度プロファイルを示すグラフ、実線はp型ベース層22下におけるp型ピラー層21の濃度プロファイルを示すグラフ、破線はp型クランプ層30下におけるp型ピラー層21の濃度プロファイルを示すグラフをそれぞれ示している。
図11は第5の実施形態を示す半導体装置1の要部断面図、図12は第5の実施形態の変形例を示す半導体装置1の要部断面図をそれぞれ示している。この第5の実施形態及び第5の実施形態の変形例の各部について、図1に示す第1の実施形態の半導体装置1の各部と同一部分は同一符号で示す。
Claims (10)
- 第1導電型の第1半導体層を含む半導体基板と、前記半導体基板の一方の表面側から深さ方向に延在し、かつ互いに間隔をおいて前記半導体基板内に設けられた複数の第2導電型の第2半導体層と、前記半導体基板の一方の表面側において一部の前記第2半導体層と接するように設けられた複数の第2導電型の第3半導体層と、前記第3半導体層の表面に選択的に形成された第1導電型の第4半導体層と、前記第1半導体層、前記第3半導体層及び前記第4半導体層の表面側に絶縁膜を介して設けられた制御電極と、前記第3半導体層と前記第4半導体層に接続された第1主電極と、前記第1半導体層の他方の表面に設けられた第1導電型の第6半導体層と、前記第6半導体層に電気的に接続された第2主電極を有するMOSと、
前記半導体基板の一方の表面側において一部の前記第2半導体層と接するように設けられた第2導電型の第5半導体層と、前記第1半導体層と、前記第2半導体層と、前記第6半導体層を含んで構成され、前記第5半導体層に接続するクランプ電極に接続された第1ダイオードと、
前記制御電極に接続された第7半導体層を含んで構成され、前記第1ダイオードと逆直列になるように前記クランプ電極に接続された第2ダイオードと、
を有する半導体装置。 - 前記第1ダイオードの耐圧は、前記MOSの耐圧よりも低い請求項1に記載の半導体装置。
- 前記第1主電極の一部に、前記制御電極の外部への引き出し電極を設け、前記引き出し電極下に前記第1ダイオードと前記第2ダイオードが設けられている請求項1または請求項2に記載の半導体装置。
- 前記第5半導体層同士の間隔は、前記第3半導体層同士の間隔よりも広い請求項1乃至請求項3のいずれか一に記載の半導体装置。
- 前記第2半導体層同士の間隔は、前記MOS側よりも前記第1ダイオード側で広い請求項1乃至請求項4のいずれか一に記載の半導体装置。
- 前記第2半導体層の不純物濃度は、前記第2主電極側から前記第1主電極側へ近づくにつれて高くなっている請求項1乃至請求項5のいずれか一に記載の半導体装置。
- 前記第2主電極側から前記第1主電極側へ近づく際の前記第2半導体層の不純物濃度の変化は、前記MOS側よりも前記第1ダイオード側で大きい請求項1乃至6のいずれか一に記載の半導体装置。
- 前記第1ダイオード側では前記第1半導体層よりも前記第2半導体層の不純物濃度が高く、前記MOS側では前記第1半導体層よりも前記第2半導体層の不純物濃度が低い請求項1乃至7のいずれか一に記載の半導体装置。
- 前記第1半導体層と前記第2半導体層の不純物濃度は、前記MOS側よりも前記第1ダイオード側で高い請求項1乃至請求項8のいずれか一に記載の半導体装置。
- 前記第1主電極と前記第2主電極間に電圧を印加した際に、前記MOSよりも前記第1ダイオードで先にアバランシェ降伏が生じ、ゲート抵抗で生じる電圧降下により前記制御電極に印加される電圧が閾値電圧以上となった際に、前記第2主電極から前記第1主電極に電流が流れて動作する請求項1乃至9のいずれか一に記載の半導体装置。
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