US20130082261A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
US20130082261A1
US20130082261A1 US13/612,200 US201213612200A US2013082261A1 US 20130082261 A1 US20130082261 A1 US 20130082261A1 US 201213612200 A US201213612200 A US 201213612200A US 2013082261 A1 US2013082261 A1 US 2013082261A1
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United States
Prior art keywords
semiconductor
diode
electrode
semiconductor device
layer
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Abandoned
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US13/612,200
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English (en)
Inventor
Wataru Saito
Syotaro Ono
Toshiyuki Naka
Shunji Taniuchi
Hiroaki Yamashita
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Toshiba Corp
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Toshiba Corp
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Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SAITO, WATARU, NAKA, TOSHIYUKI, ONO, SYOTARO, TANIUCHI, SHUNJI, YAMASHITA, HIROAKI
Publication of US20130082261A1 publication Critical patent/US20130082261A1/en
Priority to US14/246,437 priority Critical patent/US9349721B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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Definitions

  • Embodiments described herein relate to a semiconductor device.
  • a vertical power MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • a vertical power MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • the vertical power MOSFET is used in a power management circuit and the safety circuit of a lithium-ion battery, it is required characteristics of low ON resistance, high breakdown voltage, low voltage operation and reducing switching loss.
  • the vertical power MOSFET has functions to switch with applied high voltage and to clamp an electrical voltage generated by an avalanche breakdown in the case of applied overvoltage. These functions prevent components in the circuit from being insulation breakdown.
  • the avalanche breakdown means an amount of current or energy in the avalanche state. It is available to have a low breakdown voltage of a semiconductor device for improving the avalanche breakdown. However, if the vertical power MOSFET has a low breakdown voltage, its ON resistance increases.
  • FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment
  • FIG. 2 is an equivalent circuit of the semiconductor device according to the first embodiment
  • FIG. 3 is a cross-sectional view of the semiconductor device including Schottky barrier diode according to the first embodiment
  • FIG. 4 is a cross-sectional view of the semiconductor device according to a second embodiment
  • FIG. 5 is a plane view of the semiconductor device according to a third embodiment
  • FIG. 6 is a cross-sectional view of main component along the line X-A-X′ in FIG. 5 ;
  • FIG. 7 is a cross-sectional view of an alternative of the semiconductor device according to the third embodiment.
  • FIG. 8A is a cross-sectional view of the semiconductor device according to a fourth embodiment.
  • FIG. 8B is a graph illustrating an impurity concentration profile along the vertical direction (depth direction) of the portion illustrated in FIG. 8A ;
  • FIG. 9A is a cross-sectional view of an alternative of the semiconductor device according to the fourth embodiment.
  • FIG. 9B is a graph illustrating an impurity concentration profile along the cross direction of the portion illustrated in FIG. 9A ;
  • FIG. 10A is a cross-sectional view of an alternative of the semiconductor device according to alternative of the fourth embodiment.
  • FIG. 10B is a graph illustrating an impurity concentration profile along the cross direction of the portion illustrated in FIG. 10A ;
  • FIG. 11 is a cross-sectional view of the semiconductor device according to a fifth embodiment.
  • FIG. 12 is a cross-sectional view of an alternative of the semiconductor device according to alternative of the fifth embodiment.
  • An aspect of the present invention is a semiconductor device comprising: a Metal Oxide Semiconductor Field Effect Transistor including: a semiconductor substrate including a first semiconductor layer of a first conductivity type; second semiconductor layers of a second conductivity type extending in a depth direction from one surface of the semiconductor substrate, and having space each other; third semiconductor layers of the second conductivity type formed on at least of the second semiconductor layers in one surface side of the semiconductor substrate; fourth semiconductor layers of the first conductivity type partially formed on a surface of the third semiconductor layers; each of control electrodes formed on a surface of the third semiconductor layer via an insulating film; a first electrode connected the third semiconductor layers and the fourth semiconductor layers; and a second electrode electrically connected on the other surface of the first semiconductor layer; a first diode including a fifth semiconductor layer of the second conductivity type contacting the second semiconductor layer in one surface side of the semiconductor substrate, the first semiconductor layer and the second semiconductor layers; and a cathode of a second diode including a seventh semiconductor layer connected to the control electrode, and an an
  • a semiconductor device comprising: a Metal Oxide Semiconductor Field Effect Transistor including: a semiconductor substrate including a first semiconductor layer of a first conductivity type; trenches extending in a depth direction from one surface of the semiconductor substrate, and having space each other; implanting electrode formed in second main electrode side of the trenches via gate insulating film; control electrode formed in first electrode side of the trenches via gate insulating film; third semiconductor layers of the second conductivity type formed in one surface side of the semiconductor substrate; fourth semiconductor layers of the first conductivity type partially formed on a surface of the third semiconductor layers; a first electrode connected the third semiconductor layers and the fourth semiconductor layers; and a second electrode electrically connected on the other surface of the first semiconductor layer; a first diode including the first semiconductor layer and fifth semiconductor layer of the second conductivity type contacting the second semiconductor layers in one surface side of the semiconductor substrate; and a cathode of a second diode including a seventh semiconductor layer connected to the control electrode, and an anode of the second
  • a first conductivity type is assumed to be an n-type
  • a second conductivity type is assumed to be a p-type
  • the invention can be practiced also under that the first conductivity type may be the p-type and the second conductivity type may be the n-type.
  • FIG. 1 shows a cross-sectional view of a semiconductor device according to a first embodiment
  • FIG. 2 shows an equivalent circuit of the semiconductor device according to the first embodiment.
  • a semiconductor device 1 according to a first embodiment is provided with MOSFET 2 , a first diode 3 and a second diode 4 .
  • the semiconductor device 1 is formed by an ion implantation method or an epitaxial growth for semiconductor substrate.
  • the semiconductor substrate is shown as an n ⁇ type drift layer 20 that is a first semiconductor layer.
  • many p type pillar layers 21 second semiconductor layers are extending in a depth direction from one surface of the n ⁇ type drift layer 20 , and have a space each other.
  • the n ⁇ type drift layer 20 and the p type pillar layer 21 are alternatively arranged (pn junction).
  • the formation is generally called a super junction structure.
  • the super junction structure has the same amount of charge (impurity amount) in each of the n ⁇ type drift layer 20 and the p type pillar layer 21 . And it creates a pseudo-non-doped layer, holds a high breakdown voltage, and passes a current through the highly doped n ⁇ type drift layer 20 to realize a low ON resistance superior to that of the material limit.
  • P type base layers 22 as third semiconductor layers are formed on one surface of the n ⁇ type drift layer 20 so as to contact at least of the p type pillar layers 21 .
  • n type source layers 23 as fourth semiconductor layers are selectively formed on the surface of the p type base layers 22 .
  • P type clamp layer 30 as a fifth semiconductor layer is formed on one surface of the n ⁇ type drift layer 20 so as to contact at least of the p type pillar layers 21 which don't contact the p type base layers 22 .
  • a gate insulating film 24 is formed on a region from the n type source layer 23 in one p type base layer 22 to the n type source layer 23 in the other p type base layer 22 .
  • the gate insulating film 24 may be a silicon oxide film.
  • Gate electrodes 25 as control electrodes are formed on the insulating film 24 .
  • the gate electrodes 25 are made from a poly-silicon.
  • a source electrode 50 as a first electrode is formed on the p type base layers 22 and the n type source layer 23 .
  • n + type drain layer 26 as a sixth semiconductor layer is formed on the other surface of the n ⁇ type drift layer 20 .
  • a drain electrode 51 as a second electrode is formed on the surface of the n + type drain layer 26 .
  • the n + type drain layer 26 is electrically connected to the drain electrode 51 .
  • the MOSFET 2 is provided with the n ⁇ type drift layer 20 , the p type pillar layers 21 , the p type base layers 22 , the n type source layer 23 , the gate insulating film 24 , the gate electrodes 25 and the n + type drain layer 26 .
  • the first diode 3 includes the p type clamp layer 30 , the n ⁇ type drift layer 20 , the p type pillar layers 21 and the n + type drain layer 26 .
  • the second diode 4 which is formed on the p type clamp layer 30 , is made from poly-silicon etc. same material of the gate electrode 25 .
  • the second diode 4 is a p-intrinsic-n diode.
  • a gate electrode 25 a electrically connected the gate electrode 25 is cathode.
  • the second diode 4 includes a semiconductor layer 40 as a seventh semiconductor layer and a p type semiconductor layer 41 as an eighth semiconductor layer.
  • the semiconductor layer 40 has impurity concentration lower than the p type semiconductor layer 41 .
  • a connecting junction 52 connected to the p type semiconductor layer 41 of the second diode 4 is electrically connected to the p type clamp layer 30 of the first diode 3 .
  • an anode of the first diode 3 is electrically connected to an anode of the second diode 4 .
  • the breakdown voltage of the first diode 3 is configured so as to be lower than the breakdown voltage of the MOSFET 2 .
  • a predetermined voltage (a gate voltage of a threshold voltage or more) is applied to the gate electrode 25 ; a channel (an n type inversion layer) is formed in the surface of the p type base layers 22 .
  • a channel an n type inversion layer
  • the n ⁇ type drift layer 20 and the n type source layer 23 are conductive.
  • an electric current flows between the source electrode 50 and the drain electrode 51 through the n type source layer 23 , the n ⁇ type drift layer 20 and the n + type drain layer 26 . That is, the semiconductor device 1 turns on.
  • FIG. 2 shows an equivalent circuit of the semiconductor device 1 according to the first embodiment.
  • a high-voltage is applied between the source electrode 50 and the drain electrode 51 when a signal don't input to an input terminal 60 connected to the terminal of the gate electrode 25 a.
  • avalanche breakdown occurs at the first diode 1 , because the first diode 1 has a lower breakdown voltage than the MOSFET 2 .
  • an electric current flows from the first diode 3 to the input terminal 60 through the second diode 4 and a gate resistor 61 . After the electric current flows, a voltage drop caused by the gate resistor 61 occurs. When an applied voltage to the gate electrode 25 exceeds the threshold voltage, the MOSFET 2 turns on and electric current flows from the drain electrode 51 to the source electrode 50 .
  • a voltage depended on the breakdown voltage of the first diode 3 clamps between the source electrode 50 and the drain electrode 51 , and electric current occurred by avalanche breakdown flow in the first diode 3 .
  • the MOSFET 2 it is possible to flow a current between the source electrode 50 and the drain electrode 51 without the current occurred by avalanche breakdown.
  • the semiconductor device 1 can realize high avalanche withstanding capability characteristics.
  • the second diode 4 formed between the MOSFET 2 and the first diode 3 , prevents an electric current to flow between the drain electrode 51 and the input terminal 60 when on-state signal (for example, 10V) inputs to the input terminal 60 . Therefore, it is preferable that the breakdown voltage of the second diode 4 is equal to or more than or equal to essential input voltage (for example, equal to or more than 30V) in its operating.
  • the semiconductor device 1 can have high avalanche withstanding capability by connecting the anode of the second diode 4 to the anode of the first diode 3 being lower breakdown voltage than the MOSFET 2 .
  • it is flexible to design the n ⁇ type drift layer 20 in the MOSFET 2 so that the trade-off between ON resistance and breakdown voltage improves and ON resistance of the semiconductor device 1 decreases.
  • the electrical capacitance between the source electrode 50 and the drain electrode 51 increases because of the first diode 3 being connected between the source electrode 50 and the drain electrode 51 . Therefore, it can be expected to improve switching speed of the MOSFET 2 .
  • the gate resistor 61 is formed outside the MOSFET 2 or the second diode 4 and connected to outside.
  • a gate resistance of the gate resistor 61 may be inside of the MOSFET 2 or be inside gate resistance and outside gate resistance.
  • FIG. 3 shows a cross-sectional view of the semiconductor device including Schottky barrier diode according to the first embodiment.
  • the second diode 4 is p-intrinsic-n diode.
  • a Schottky barrier diode may be formed a Schottky junction 42 at interface between the low impurity concentration semiconductor layer 40 and the connecting junction 52 without the p type semiconductor layer 41 .
  • the second diode 4 is formed on the p type clamp layer 30 , however the second diode 4 may be electrically connected the p type clamp layer 30 , by using the connecting junction 52 .
  • the second diode 4 may be formed anywhere in the semiconductor device 1 .
  • FIG. 4 shows a cross-sectional view of the semiconductor device according to a second embodiment.
  • the same sections as those of the semiconductor device 1 shown in FIG. 1 are represented by the same symbols.
  • a semiconductor device 1 in the second embodiment differs from the semiconductor device 1 in the first embodiment in that a gate electrode 25 b deriving the gate electrode 25 a is formed in part of the source electrode 50 forming on upside of the second diode 4 and the first diode 3 and the second diode 4 are formed under the gate electrode 25 b.
  • the semiconductor device 1 the MOSFET 2
  • the first diode 3 and the second diode 4 are invalid region that don't flow current.
  • the first diode 3 and the second diode 4 are generally invalid region. Therefore, in this embodiment, what the first diode 3 and the second diode 4 forming under the gate electrode 25 b being originally invalid region lead to be decrease an area of invalid region and chip.
  • the semiconductor device 1 can have high avalanche withstanding capability by connecting the anode of the second diode 4 to the anode of the first diode 3 being lower breakdown voltage than the MOSFET 2 .
  • it is flexible to design the n ⁇ type drift layer 20 in the MOSFET 2 so that the trade-off between ON resistance and breakdown voltage improves and ON resistance of the semiconductor device 1 decreases.
  • the electrical capacitance between the source electrode 50 and the drain electrode 51 increases because of the first diode 3 being connected between the source electrode 50 and the drain electrode 51 . Therefore, it can be expected to improve switching speed of the MOSFET 2 .
  • FIG. 5 shows a plane view of the semiconductor device according to a third embodiment.
  • FIG. 6 shows a cross-sectional view of main component along the line X-A-X′ in FIG. 5 .
  • FIG. 7 shows a cross-sectional view of an alternative of the semiconductor device according to the third embodiment.
  • the same sections as those of the semiconductor device 1 shown in FIG. 1 are represented by the same symbols.
  • the semiconductor device 1 in the third embodiment differs from the semiconductor devices 1 in the first embodiment and the second embodiment in that a space between the p type clamp layers 30 is wider than a space between the p type base layers 22 .
  • a space between the p type clamp layers 30 is wider than a space between the p type base layers 22 .
  • a length y of such as poly-silicon forming the low impurity concentration semiconductor layer 40 and the p type semiconductor layer 41 is longer than a length x of the gate electrode 25 .
  • the space between the p type clamp layers 30 forming with such as poly-silicon is longer than the space between the p type base layers 22 forming with the gate electrode 25 .
  • the semiconductor device 1 can have high avalanche withstanding capability by connecting the anode of the second diode 4 to the anode of the first diode 3 being lower breakdown voltage than the MOSFET 2 .
  • it is flexible to design the n ⁇ type drift layer 20 in the MOSFET 2 so that the trade-off between ON resistance and breakdown voltage improves and ON resistance of the semiconductor device 1 decreases.
  • the electrical capacitance between the source electrode 50 and the drain electrode 51 increases because of the first diode 3 being connected between the source electrode 50 and the drain electrode 51 . Therefore, it can be expected to improve switching speed of the MOSFET 2 .
  • FIG. 8A shows a cross-sectional view of the semiconductor device according to a fourth embodiment
  • FIG. 8B shows a graph illustrating an impurity concentration profile along the vertical direction (depth direction) of the portion illustrated in FIG. 8A .
  • FIG. 9A , FIG. 9B , FIG. 10A and FIG. 10B show alternatives of the fourth embodiment.
  • FIG. 9A shows a cross-sectional view of an alternative of the semiconductor device according to the fourth embodiment
  • FIG. 9B shows a graph illustrating an impurity concentration profile along the cross direction of the portion illustrated in FIG. 9A
  • FIG. 10A shows a cross-sectional view of an alternative of the semiconductor device according to alternative of the fourth embodiment
  • FIG. 10B shows a graph illustrating an impurity concentration profile along the cross direction of the portion illustrated in FIG. 10A .
  • the same sections as those of the semiconductor device 1 shown in FIG. 1 are represented by the same symbols.
  • the semiconductor device 1 in the fourth embodiment differs from the semiconductor devices 1 in the first-third embodiments in that an impurity concentration of the n ⁇ drift layer 20 and the p type pillar layer 21 is adjusted.
  • the impurity concentration of the p type pillar layer 21 in the source electrode 50 side is higher profile than in the drain electrode 51 side.
  • This impurity concentration profile results in decreasing an electric field of an upper and a lower end of a super junction structure, namely the p type pillar layer 21 .
  • change in the impurity concentration along a vertical direction (a depth direction) of the p type pillar layer 21 under the p type clamp layer 30 is bigger than change in the impurity concentration along the vertical direction (the depth direction) of the p type pillar layer 21 under the p type base layer 22 .
  • a breakdown voltage of the first diode 3 is certainly lower than a breakdown voltage between a drain and a source in the MOSFET 2 and avalanche breakdown of the first diode 3 increase.
  • change in the impurity concentration of the p type pillar layer 21 is shown for example.
  • the change can be illustratively the n ⁇ type drift layer 20 .
  • impurity the concentration of n ⁇ type drift layer 20 is higher than the p type pillar layer 21 at the drain electrode 51 side and the impurity concentration of n ⁇ type drift layer 20 is lower than the p type pillar layer 21 in the source electrode 50 side, same result is available.
  • the impurity concentration of the p type pillar layer 21 is higher than the impurity concentration of the n ⁇ type drift layer 20 under the p type clamp layer 30 and the impurity concentration of the p type pillar layer 21 is lower than the impurity concentration of the n ⁇ type drift layer 20 under the p type base layer 22 being allowed to be low avalanche withstanding capability.
  • the breakdown voltage between the MOSFET 2 and the first diode 3 is only different, it is also possible to achieve by the impurity concentration of the n ⁇ type drift layer 20 and p type pillar layer 21 under p type clamp layer 30 is higher than the impurity concentration of the n ⁇ type drift layer 20 and p type pillar layer 21 under p type base layer 22 as shown in FIG. 10 .
  • the breakdown voltage of the first diode 3 can certainly be lower than the breakdown voltage of the MOSFET 2 between the source electrode 50 and the drain electrode 52 .
  • the semiconductor device 1 can have high avalanche withstanding capability by connecting the anode of the second diode 4 to the anode of the first diode 3 being lower breakdown voltage than the MOSFET 2 .
  • it is flexible to design the n ⁇ type drift layer 20 in the MOSFET 2 so that the trade-off between ON resistance and breakdown voltage improves and ON resistance of the semiconductor device 1 decreases.
  • the breakdown voltage of the first diode 3 is certainly lower than the breakdown voltage of the MOSFET 2 between the source electrode 50 and the drain electrode 52 , ON resistance of the MOSFET 2 is reduced, avalanche breakdown of the first diode 3 is improved and the switching noise of the semiconductor device 1 decrease.
  • FIG. 11 shows a cross-sectional view of the semiconductor device according to a fifth embodiment
  • FIG. 12 shows a cross-sectional view of an alternative of the semiconductor device according to alternative of the fifth embodiment.
  • the same sections as those of the semiconductor device 1 shown in FIG. 1 are represented by the same symbols.
  • the semiconductor device 1 in the fifth embodiment differs from the semiconductor devices 1 in the first-fourth embodiments in that the semiconductor device 1 is a trench gate formation and a implanted electrode 53 is formed under the gate electrode 25 in a trench 54 .
  • the trenches 54 are formed in the n ⁇ type drift layer 20 and the implanted electrodes 53 in the trenches 54 are formed on the gate insulating film 24 .
  • the increase impurity concentration of the n ⁇ type drift layer 20 and decrease ON resistance of the semiconductor device 1 it is possible to the increase impurity concentration of the n ⁇ type drift layer 20 and decrease ON resistance of the semiconductor device 1 .
  • the semiconductor device 1 formed the implanted electrode 53 , it is possible to improve the avalanche withstanding capability by similarly forming the equivalent circuit shown in FIG. 2 of the first embodiment.
  • the implanted electrode 53 can also be connecting the implanted electrode 53 to the source electrode 50 or the gate electrode 25 .
  • the trench 54 adjoining the p type clamp layer 30 is formed, the implanted electrode 53 a in an upside of the trench 54 is formed on the gate insulating film 24 and the implanted electrode 53 b in a downside of the trench 54 is formed on the gate insulating film 24 .
  • a structure of the device edge termination portion is not particularly described, however, any edge termination structure such as a RESURF (Reduced SURface Field) structure and a guard ring structure can be used for implement.
  • RESURF Reduced SURface Field
  • the method of forming the semiconductor device 1 isn't only forming process of a super junction structure, but also processes repeating ion implantation and crystal growth, doing many ion implantation with changing acceleration voltage and doing crystal growth after forming trench.
  • the MOSFET based on silicon (Si) as a semiconductor has been described, however, the semiconductor can be illustratively based on a compound semiconductor such as silicon carbide (SiC) and gallium nitride (GaN), and a wide gap semiconductor such as diamond.
  • SiC silicon carbide
  • GaN gallium nitride
  • the embodiments are mainly formed by method using both ion implantation and epitaxial growth, however, the forming method can also be only ion implantation method or only epitaxial growth.

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US20140284704A1 (en) 2014-09-25
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