JP2011181583A - 半導体装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 143
- 239000012535 impurity Substances 0.000 claims description 24
- 238000012986 modification Methods 0.000 description 18
- 230000004048 modification Effects 0.000 description 18
- 238000010586 diagram Methods 0.000 description 7
- 230000012010 growth Effects 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
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Abstract
【解決手段】ドリフト領域2と、ベース領域3と、ベース領域3を挟んでドリフト領域2に対向して設けられたソース電極12と、ドリフト領域2とベース領域3とにゲート絶縁膜を介して接するトレンチ構造の複数のゲート電極6と、2つのゲート電極6の間において、ドリフト領域2とベース領域3との境界に沿って設けられ、ベース領域3に接する長さがゲート電極6よりも短いトレンチ構造のゲート電極7と、を備え、ソース電極12は2つのゲート電極6の間において、ソース電極12からゲート電極7に向かう方向に設けられたトレンチ9bの中に、ゲート電極7に近接した位置まで延在し、ゲート電極6のソース電極側の端とゲート電極7のソース電極側の端との間において、トレンチ9bの内壁面に露出したベース領域3に接していること。
【選択図】図1
Description
図1は、第1実施形態に係る半導体装置の構造を模式的に示す部分断面図である。ここでは、半導体装置の例としてMOSFET1を取り上げて説明するが、IGBTおよびIEGT等、他の半導体装置にも適用可能である。
図9は、第2実施形態に係る半導体装置の構造を模式的に示す部分断面図である。本実施形態に係るMOSFET60は、絶縁層31の主面上に設けられた横型構造を有している。なお、絶縁層31は、例えば、基板上に設けられたSiO2等の絶縁膜でも良いし、半絶縁性を有する半導体層であっても良い。
図13は、第3実施形態に係るMOSFET100の構造を模式的に示す部分断面図である。
図15は、第4実施形態に係る半導体装置120の構造を模式的に示す部分断面図である。半導体装置120は、絶縁層31の主面に交互に積層された複数のP型半導体領域24およびN型半導体領域25からなるスーパージャンクション構造を有する電力制御用半導体装置である。
3、33 ベース領域
4、34、52 ソース領域
5、51、58 コンタクト領域
6、7、35、36 ゲート電極
8、8a、8b、37、37a、37b ゲート絶縁膜
9a、9b トレンチ
12、38 ソース電極
13 N型半導体層
14 ドレイン層
18、54 P+領域
21 P型ピラー
22 N型ピラー
24 P型半導体領域
25 N型半導体領域
27 積層体
31 絶縁層
32 ドリフト領域
39、49 張り出し部
41 N型半導体領域
42 ドレイン領域
43 ドレイン電極
44 ドレイン層
45、46、47、55 トレンチ
53 N+領域
61 第1の主面
62 第2の主面
1、10、20、30、40,50,60,70,80、90 MOSFET
100、110、MOSFET
120 半導体装置
Claims (6)
- 第1導電型の半導体を含むドリフト領域と、
前記ドリフト領域に接して設けられた第2導電型の第1半導体領域と、
前記第1半導体領域を挟んで前記ドリフト領域に対向して設けられ、前記第1半導体領域に電気的に接続された主電極と、
前記ドリフト領域と前記第1半導体領域との境界に沿って設けられ、前記ドリフト領域と前記第1半導体領域とに第1のゲート絶縁膜を介して接するトレンチ構造の複数の第1ゲート電極と、
2つの前記第1ゲート電極の間において、前記ドリフト領域と前記第1半導体領域との前記境界に沿って、前記ドリフト領域と前記第1半導体領域とに第2のゲート絶縁膜を介して接するように設けられ、前記境界から前記主電極に向かう方向の前記第1半導体領域に接する長さが前記第1ゲート電極よりも短い前記トレンチ構造の第2ゲート電極と、
を備え、
前記主電極は、前記2つの第1ゲート電極の間において、前記主電極から第2ゲート電極に向かう方向に設けられたトレンチの中に、前記第2ゲート電極に近接した位置まで延在し、前記第1ゲート電極の前記主電極側の端と、前記第2ゲート電極の前記主電極側の端と、の間において、前記トレンチの内壁面に露出した前記第1半導体領域に接していることを特徴とする半導体装置。 - 前記第1半導体領域と前記主電極との間に、第1導電型の第2半導体領域をさらに備え、
前記主電極は、前記トレンチの内壁面に露出した、前記第2半導体領域と前記ドリフト領域との間の前記第1半導体領域に接していることを特徴とする請求項1記載の半導体装置。 - 前記トレンチの内壁面において、前記主電極が、前記第2半導体領域と前記ドリフト領域との間の前記第1半導体領域に接する、前記第2半導体領域から前記ドリフト領域に向かう方向の幅は、0.05μm以上であることを特徴とする請求項2に記載の半導体装置。
- 前記主電極が延在して前記第2ゲート電極に対向する端部と、前記第2ゲート電極と、の間の間隔は、前記トレンチの内壁面側で0.05μm以上であることを特徴とする請求項1または3のいずれかに記載の半導体装置。
- 前記主電極が延在して接触する前記トレンチの内壁面に露出する、前記第2半導体領域と前記ドリフト領域との間の前記第1半導体領域の表面に、第2導電型の不純物が前記第1半導体領域よりも高濃度にドープされた第3半導体領域を有することを特徴とする請求項2〜4のいずれか1つに記載の半導体装置。
- 前記ドリフト領域において、前記ドリフト領域と前記第1半導体領域との間の境界に沿った方向に、第1導電型の第4半導体領域と、第2導電型の第5半導体領域と、が交互に設けられたことを特徴とする請求項1〜5のいずれか1つに記載の半導体装置。
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JP2010042235A JP5762689B2 (ja) | 2010-02-26 | 2010-02-26 | 半導体装置 |
US13/034,443 US9024382B2 (en) | 2010-02-26 | 2011-02-24 | Semiconductor device |
CN201110046610.1A CN102194879B (zh) | 2010-02-26 | 2011-02-25 | 半导体装置 |
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Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014157883A (ja) * | 2013-02-14 | 2014-08-28 | Sanken Electric Co Ltd | 半導体装置 |
JP2015038954A (ja) * | 2013-07-16 | 2015-02-26 | 株式会社東芝 | 半導体装置 |
JP2016219739A (ja) * | 2015-05-26 | 2016-12-22 | トヨタ自動車株式会社 | 半導体装置 |
JP2017054968A (ja) * | 2015-09-10 | 2017-03-16 | 株式会社東芝 | 半導体装置及びその駆動方法 |
JP2017212462A (ja) * | 2012-08-21 | 2017-11-30 | ローム株式会社 | 半導体装置 |
US10062774B2 (en) | 2012-08-21 | 2018-08-28 | Rohm Co., Ltd. | Trench-type insulated gate semiconductor device including an emitter trench and an overlapped floating region |
JP2019145716A (ja) * | 2018-02-22 | 2019-08-29 | 株式会社豊田中央研究所 | 半導体装置 |
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JP5762689B2 (ja) | 2015-08-12 |
CN102194879B (zh) | 2014-01-22 |
US20110210391A1 (en) | 2011-09-01 |
US9024382B2 (en) | 2015-05-05 |
CN102194879A (zh) | 2011-09-21 |
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