JP6421487B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 246
- 238000004519 manufacturing process Methods 0.000 title claims description 46
- 239000012535 impurity Substances 0.000 claims description 62
- 238000005468 ion implantation Methods 0.000 claims description 52
- 238000000034 method Methods 0.000 claims description 29
- 230000015572 biosynthetic process Effects 0.000 claims description 15
- 238000009792 diffusion process Methods 0.000 claims description 10
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 30
- 239000000758 substrate Substances 0.000 description 23
- 230000015556 catabolic process Effects 0.000 description 18
- 230000008569 process Effects 0.000 description 16
- 238000005520 cutting process Methods 0.000 description 14
- 239000002019 doping agent Substances 0.000 description 12
- 230000000694 effects Effects 0.000 description 10
- 238000010438 heat treatment Methods 0.000 description 10
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 7
- 229910052796 boron Inorganic materials 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 6
- 230000001133 acceleration Effects 0.000 description 5
- 230000003247 decreasing effect Effects 0.000 description 5
- 238000013461 design Methods 0.000 description 5
- 239000000969 carrier Substances 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000007429 general method Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
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Description
実施の形態1にかかる半導体装置の構造について説明する。図1は、実施の形態1にかかる半導体装置のトレンチゲート構造の平面レイアウトを示す平面図である。図1にはゲート絶縁膜、層間絶縁膜、ソース電極およびパッシベーション膜を図示省略する(図2〜4,10,14についても同様)。図2は、図1の切断線A−A’における断面構造を示す断面図である。図3は、図1の切断線B−B’における断面構造を示す断面図である。図4は、図1の切断線C−C’における断面構造を示す断面図である。切断線A−A’は、トレンチ3およびp++型コンタクト領域(第4半導体領域)7を通る。切断線B−B’は、トレンチ3およびn+型エミッタ領域(第3半導体領域)6を通る。切断線C−C’は、n+型エミッタ領域6、p++型コンタクト領域7およびp+型領域(第5半導体領域)8を通る。
実施の形態2にかかる半導体装置の構造について説明する。図10は、実施の形態2にかかる半導体装置のトレンチゲート構造の要部を示す断面図である。図10には、図1の切断線C−C’における断面構造を示す。トレンチゲート構造の平面レイアウト、トレンチ3およびp++型コンタクト領域7を通る断面構造(図1の切断線A−A’)、および、トレンチ3およびn+型エミッタ領域6を通る断面構造(図1の切断線B−B’)は実施の形態1と同様である(図1〜3参照)。実施の形態2にかかる半導体装置が実施の形態1にかかる半導体装置と異なる点は、n+型エミッタ領域6とp++型コンタクト領域7との接合界面の下側の端部を覆うp+型領域28の深さを、n+型エミッタ領域6の深さよりも深く、かつp++型コンタクト領域7の深さよりも浅くする点である。
実施の形態3にかかる半導体装置の構造について説明する。図14は、実施の形態3にかかる半導体装置のトレンチゲート構造の要部を示す斜視図である。実施の形態3にかかる半導体装置が実施の形態1にかかる半導体装置と異なる点は、隣り合うトレンチ3間に挟まれたp-型ベース領域2に、n+型エミッタ領域6を設けて単位セル構造としたメサ部と、n+型エミッタ領域6を設けずにp-型フローティング領域42としたメサ部と、を配置した点である。具体的には、トレンチ3がストライプ状の延びる第1方向と直交する第2方向に、n+型エミッタ領域6およびp++型コンタクト領域7からなる単位セルとしたメサ部と、エミッタ電位のp-型フローティング領域42としたメサ部とが交互に繰り返し配置されている。
2 p-型ベース領域
3 トレンチ
4 ゲート絶縁膜
5 ゲート電極
6 n+型エミッタ領域
7 p++型コンタクト領域
8,28 p+型領域
11,14,31 レジストマスク
12 第1イオン注入
13,32 第2イオン注入
15,33 第3イオン注入
W1 n+型エミッタ領域の第1方向(トレンチがストライプ状の延びる方向)の幅
W2 p++型コンタクト領域の第1方向の幅
W3 p+型領域の第1方向の幅
W4 n+型エミッタ領域下端の第1方向の幅
W11 第1方向に隣り合うn+型エミッタ領域とp++型コンタクト領域とのマスク上の間隔
W12 第1方向に隣り合うn+型エミッタ領域とp++型コンタクト領域との間隔
Claims (11)
- 第1導電型の第1半導体領域の一方の面側に設けられた第2導電型の第2半導体領域と、前記第2半導体領域を深さ方向に貫通して前記第1半導体領域に達し、かつストライプ状の平面パターンで配置された複数のトレンチと、前記トレンチの内部にゲート絶縁膜を介して設けられたゲート電極と、前記第2半導体領域の、隣り合う前記トレンチ間に挟まれたメサ部に選択的に設けられた第1導電型の第3半導体領域と、前記メサ部に、前記第3半導体領域に接して設けられた、前記第2半導体領域よりも不純物濃度の高い第2導電型の第4半導体領域と、を備えた半導体装置の製造方法であって、
前記メサ部に、前記トレンチがストライプ状に延びる第1方向に所定の間隔で前記第3半導体領域を選択的に形成する第1工程と、
前記メサ部の、前記第1方向に隣り合う前記第3半導体領域の間に挟まれた部分全体に、前記第2半導体領域よりも不純物濃度の高い第2導電型の第5半導体領域を形成する第2工程と、
前記第5半導体領域の内部に、前記第3半導体領域と離して、前記第5半導体領域よりも不純物濃度の高い前記第4半導体領域を選択的に形成する第3工程と、
前記第1方向に前記第3半導体領域と前記第4半導体領域とが交互に繰り返し配置されるように、前記第1方向に隣接する前記第5半導体領域に前記第3半導体領域と前記第4半導体領域とを拡散させて接触させる第4工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記第4工程では、前記第3半導体領域と前記第4半導体領域との接合界面の、前記第1半導体領域側に前記第5半導体領域を残すことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第2工程では、前記第3半導体領域の深さ以下の深さで前記第5半導体領域を形成することを特徴とする請求項1または2に記載の半導体装置の製造方法。
- 前記第2工程では、前記第3半導体領域の深さよりも深く、かつ前記第4半導体領域の深さよりも浅い前記第5半導体領域を形成することを特徴とする請求項1または2に記載の半導体装置の製造方法。
- 前記第2工程では、前記メサ部の全面に第2導電型不純物をイオン注入することにより前記第5半導体領域を形成することを特徴とする請求項3に記載の半導体装置の製造方法。
- 前記第1工程の前に、前記メサ部の表面に、前記第3半導体領域の形成領域に対応する部分を開口した第1マスクを形成する第1マスク工程と、
前記第1工程の後、前記第2工程の前に、前記第1マスクを除去する工程と、
前記第2工程の後、前記第3工程の前に、前記メサ部の表面に、前記第4半導体領域の形成領域に対応する部分を開口した第2マスクを形成する第2マスク工程と、
をさらに含み、
前記第1工程では、前記第1マスクをマスクとして第1導電型不純物をイオン注入することにより前記第3半導体領域を形成し、
前記第3工程では、前記第2マスクをマスクとして第2導電型不純物をイオン注入することにより前記第4半導体領域を形成し、
前記第1マスクによって露出させる領域と、前記第2マスクによって露出させる領域との間隔を0.4μm以上1.2μm以下にすることを特徴とする請求項5に記載の半導体装置の製造方法。 - 前記第1工程の後、前記第2工程の前に、前記メサ部の表面に、前記第4半導体領域の形成領域に対応する部分を開口した第2マスクを形成する第2マスク工程をさらに含み、
前記第2工程では、前記第2マスクをマスクとして第1の第2導電型不純物をイオン注入することにより前記第5半導体領域を形成し、
前記第3工程では、前記第2マスクをマスクとして前記第1の第2導電型不純物よりも拡散係数の低い第2の第2導電型不純物をイオン注入することにより前記第4半導体領域を形成することを特徴とする請求項4に記載の半導体装置の製造方法。 - 前記第1工程の前に、前記メサ部の表面に、前記第3半導体領域の形成領域に対応する部分を開口した第1マスクを形成する第1マスク工程をさらに含み、
前記第1工程では、前記第1マスクをマスクとして第1導電型不純物をイオン注入することにより前記第3半導体領域を形成し、
前記第1マスクによって露出させる領域と、前記第2マスクによって露出させる領域との間隔を0.4μm以上1.2μm以下にすることを特徴とする請求項7に記載の半導体装置の製造方法。 - 第1導電型の第1半導体領域の一方の面側に設けられた第2導電型の第2半導体領域と、
前記第2半導体領域を深さ方向に貫通して前記第1半導体領域に達し、かつストライプ状の平面パターンで配置された複数のトレンチと、
前記トレンチの内部にゲート絶縁膜を介して設けられたゲート電極と、
前記第2半導体領域の、隣り合う前記トレンチ間に挟まれたメサ部に、前記トレンチがストライプ状に延びる第1方向に所定の間隔で選択的に設けられた第1導電型の第3半導体領域と、
前記メサ部に、前記第1方向に前記第3半導体領域と交互に繰り返し配置されるように、前記第3半導体領域に接して設けられた、前記第2半導体領域よりも不純物濃度の高い第2導電型の第4半導体領域と、
前記第3半導体領域と前記第4半導体領域との接合界面の、前記第1半導体領域側の端部を覆うように選択的に設けられた、前記第2半導体領域よりも不純物濃度の高く、かつ前記第4半導体領域よりも不純物濃度の低い第2導電型の第5半導体領域と、
を備え、
前記第4半導体領域および前記第5半導体領域からなる第2導電型領域の前記第1方向の端部の曲率は、前記第4半導体領域の前記第1方向の端部の曲率よりも大きいことを特徴とする半導体装置。 - 前記第5半導体領域の深さは、前記第3半導体領域の深さ以下であることを特徴とする請求項9に記載の半導体装置。
- 前記第5半導体領域の深さは、前記第3半導体領域の深さよりも深く、かつ前記第4半導体領域の深さよりも浅いことを特徴とする請求項9に記載の半導体装置。
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