CN103329268B - 半导体器件及制造其的方法 - Google Patents

半导体器件及制造其的方法 Download PDF

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CN103329268B
CN103329268B CN201280005804.XA CN201280005804A CN103329268B CN 103329268 B CN103329268 B CN 103329268B CN 201280005804 A CN201280005804 A CN 201280005804A CN 103329268 B CN103329268 B CN 103329268B
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vertical trench
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CN103329268A (zh
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丰田善昭
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Abstract

一种半导体器件包括垂直沟槽栅极MOSFET(30)和用于控制的横向n沟道MOSFET元件部分(22)，该用于控制的横向n沟道MOSFET元件部分包括p-阱扩散区(4a)，以及围绕垂直沟槽栅极MOSFET(30)和用于控制的横向n沟道MOSFET元件部分(22)的结边缘终止区(23)。结边缘终止区(23)包括LOCOS氧化层(llc)，设置在端部处且与沟槽形成接触的p型维持区(50)，以及与p型维持区(50)形成接触的p-扩散区(4b)。p-扩散区(4b)比p型基极区(5)深，并且具有低浓度。p型维持区(50)比p-扩散区(4b)窄，并且具有高浓度。p-扩散区(4a)比p型基极区(5)和p型维持区(50)深，并且具有低浓度。结边缘终止区(23)和p-阱扩散区(4a)的击穿电压比MOSFET元件部分(30)的击穿电压高。

Description

半导体器件及制造其的方法
技术领域
本发明涉及称为复杂半导体器件(诸如具有高击穿电压的沟槽栅极类型功率IC)的半导体器件及制造其的方法，其中该复杂半导体器件中垂直沟槽MOS栅极类型半导体元件和用于保护和控制的半导体元件被形成于同一半导体衬底上。
背景技术
已提出垂直沟槽MOS栅极类型半导体元件，其中栅极区被设置在沟槽中以便减小具有小面积的MOS类型半导体元件的电阻。图3是例示一般垂直沟槽栅极MOS类型半导体元件及其结边缘终止区的主要部分的横截面视图。在图3中例示的半导体元件中，结边缘终止区69的击穿电压必须高于活跃区的击穿电压，以使得由雪崩击穿导致的电流流入活跃区68。
因此，具有比p型基极区55的浓度低的浓度的p-扩散区54被设置在结边缘终止区69中。由此，当施加截止电压时，耗尽层很可能从活跃区68延伸至结边缘终止区69。因此，结边缘终止区区域69的最大场强被充分减小且结边缘终止区69的击穿电压增加。结果，沟槽栅极MOS类型半导体元件的整体击穿电压由p型基极区结或归因于沟槽栅极的底部的电场浓度的击穿来决定。
此外，已提出被称为带有保护功能的绝缘栅极半导体器件的复杂半导体器件(其中图2的横截面视图中例示的用于保护的横向半导体元件被形成于同一半导体衬底上)，以便以低成本来改进图3中所例示的用作输出级元件的沟槽栅极MOS类型半导体元件的击穿电压可靠性或击穿电阻(专利文献1)。
图2是例示用于控制的一般横向平面MOS类型半导体元件的横截面视图。图2中所例示的保护性半导体元件包括横向n沟道MOSFET，该横向n沟道MOSFET被设置在被阱结40分隔开的p-阱扩散区35中。
在图2和3中所例示的半导体元件的复杂半导体器件中，包括n+衬底(对应于图2中的附图标记32以及图3中的附图标记52)和设置在该n+衬底上的n-外延层(对应于图2中的附图标记33和图3中的附图标记53)的公共半导体衬底包括保护性横向半导体元件和垂直MOSFET(MOS场效应晶体管)的活跃区(对应于图2中的附图标记48以及图3中的附图标记68)以及围绕这些活跃区的结边缘终止区(对应于图2中的附图标记49以及图3中的附图标记69)。
在复杂半导体设备中，施加到为输出级元件的垂直MOSFET的截止电压被同时施加到输出级元件和图2中所例示的保护性半导体元件的阱结40。因此，图3中所例示的垂直MOSFET的活跃区68和图2中所例示的保护性半导体元件的阱结40(即，p-阱扩散区35与n-外延层33)两者必须具有用于截止电压的有效击穿电压。
在图2中所例示的保护性半导体元件中，横向n沟道MOSFET被形成于由阱结40分隔开的阱扩散区中。阱结40的击穿电压是例如50V。此外，在以下描述中，出于方便起见，50V或更小的击穿电压被称为低击穿电压，而高于50V的击穿电压被称为高击穿电压。
图2中例示的保护性半导体元件的活跃区48包括栅极氧化层37、栅极电极36、漏极区域38a、源极区域38b、形成p-阱扩散区35的一部分的p型基极区和基极接触区39、以及与每个区的表面形成接触的漏极电极12、源极电极13、和基极电极14。另外，结边缘终止区49包括LOCOS氧化层41以便防止阱结40的击穿电压的减小。
另一方面，图3中所例示的垂直沟槽MOS栅极类型半导体元件部分包括连接至n+源极区58的源极电极65，p型基极区55、以及设置在半导体衬底的主表面上的p+接触区60，和在背侧在漏极区中与n+衬底52形成接触的漏极电极51。栅极电极56通过在沟槽中填充多晶硅来形成(其间插入有栅极氧化层57)，并且通过栅极电极线(未示出)被连接至衬底的表面上的栅极电极焊点。包括例如p型基极区55、栅极电极56、栅极氧化层57、n+源极区58、以及具有高杂质浓度的p+接触区的结构被称为沟槽MOS栅极结构。
围绕活跃区68的结边缘终止区69包括LOCOS氧化层61和具有电场减小功能的p-扩散区54，并且被设置成使其击穿电压高于p型基极区55与n-外延层53之间的主结的击穿电压。在结边缘终止区69中，由于结并非是平坦的，因此通过应用截止电压而生成的最大场强很可能集中在狭窄区上，并且元件击穿很可能发生。因此，需要具有电场减小功能的p-扩散区54，以便防止归因于击穿电压的减小的电流集中。
在图3中所示的垂直沟槽栅极MOSFET元件中，与平面栅极MOSFET相比，沟槽栅极结构使其可能改进沟道密度并减小截止电阻。因此，沟槽栅极结构被施加到功率IC，该功率IC包括垂直MOSFET并且具有大约50V至100V的相关电压，或者具有高于额定电压的高击穿电压玻璃。
由此，当击穿电压增至50V或更大时，在施加截止电压时在仅包括LOCOS氧化层61的结边缘终止区中扩展的耗尽层中，电场未被充分减小，并且在结边缘终止区中，击穿电压很可能将被减小。因此，除LOCOS氧化层61之外还设置以上所描述的p-扩散区，这使得可减小电场并防止击穿电压的减小。
图5例示根据相关技术的垂直沟槽栅极MOS类型半导体元件的主要部分及其结边缘终止区的横截面视图。图5例示了具有高击穿电压的垂直沟槽栅极MOS类型半导体元件的较佳示例。如图5中所例示的，已提出一种元件，该元件不包括以上所提及的保护性半导体元件，而包括具有垂直沟槽栅极MOS结构的活跃区68和结边缘终止区69(该结边缘终止区69被布置成围绕活跃区68的外周)，并且包括用于减小电场的p--RESURF(减小的表面电场)区70(例如，参看以下专利文献2)。
在诸如通过整合保护性半导体元件和垂直沟槽栅极MOS类型半导体元件形成的沟槽栅极功率IC之类的复杂半导体器件中，出于与以上所描述的相同的原因，结边缘终止区69必须被配置成使得其击穿电压高于主结击穿电压，以便减小垂直沟槽栅极MOS类型半导体元件的截止电阻以及防止击穿电压的减小。为了满足需求，除与图3中所例示的p-扩散区54相同的区之外，将电场减小机构(诸如多晶硅膜场板56c或金属膜场板66)添加到结边缘终止区69是有效的，多晶硅膜场板56c经由形成在层间电介质67上的接触孔与金属膜场板66相连。另外，在涉及以上所提及的沟槽栅极类型功率IC的专利文献2中，被设置以便减小结边缘终止区中的电场的p--RESURF区70是具有已知RESURF效果的区，即，具有通过充分耗尽基本上整个p--RESURF区70使得其表面不被完全耗尽而减小场强的效果的区。
引用列表
专利文献
专利文献1：JP2003-264289A(段落0002)
专利文献2：JP2009-105,268A(图2)
发明内容
技术问题
然而，必须添加一种用于形成具有低杂质浓度的p--RESURF区的工艺，以便无需任何改变地应用具有低杂质浓度的p--RESURF区70，该具有低杂质浓度的p--RESURF区70满足对复杂半导体器件(诸如沟槽栅极类型功率IC)的RESURF效应的条件。在此情形中，工艺成本增加，这导致成本的增加。
当满足RESURF效应的具有低杂质浓度的p--RESURF区被用在终止击穿电压结构中时，场强分布很可能因外部电荷在靠近衬底的表面的结的端部的邻近区中的影响而随时间改变。其结果是，击穿电压的可靠性降低。
鉴于以上提及的问题以提出本发明，并且本发明的目的在于提供一种半导体器件以及制造其的方法，该半导体器件可减小导通电阻并改进击穿电压和击穿电阻的可靠性，而无需添加新的制造工艺，并且可以低成本制造，而不会有成本的增加。
问题的解决方案
为了解决问题和达成目的，根据本发明的半导体器件包括：主漏极区，其为第一导电类型并且形成于第一导电类型的半导体衬底的第一主表面上；垂直沟槽MOS栅极类型半导体元件部分，包括基极区，该基极区为第二导电类型且选择性地形成于半导体衬底的第二主表面上，主源极区，该主源极区为第一导电类型且选择性地形成于基极区的表面上，沟槽，该沟槽从基极区的表面穿过基极区和主源极区延伸至半导体衬底，以及沟槽MOS栅极，该沟槽MOS栅极包括设置在沟槽中的栅极电极，且其间插入有第一绝缘薄膜，第一绝缘薄膜是绝缘薄膜；毗邻垂直沟槽MOS栅极类型半导体元件部分的用于控制的半导体元件部分，其具有元件隔离区，该元件隔离区包括形成于半导体衬底的第二主表面上并且比插入其间的第一绝缘薄膜厚的第二绝缘薄膜，该用于控制的半导体元件部分包括：阱扩散区，该阱扩散区为第二导电类型且在半导体衬底的第二主表面上与半导体衬底形成pn结，用于控制的栅极电极，该用于控制的栅极电极形成于阱扩散区的表面上且其间插入有比第二绝缘薄膜薄的第三绝缘薄膜，以及第一导电类型的控制漏极区和第一导电类型的控制源极区，它们被设置在阱扩散区的所述表面上且之间插入有控制栅极电极，并且控制垂直沟槽MOS栅极类型半导体元件部分；以及结边缘终止区，该结边缘终止区包括设置在半导体衬底的第二主表面上的第二绝缘薄膜并且围绕所述垂直沟槽MOS栅极类型半导体元件或者围绕垂直沟槽MOS栅极类型半导体元件部分和用于控制的半导体元件部分两者。结边缘终止区包括第二绝缘薄膜，为第二导电类型且在垂直沟槽MOS栅极类型半导体元件部分的端部处与沟槽形成接触的维持区，以及为第二半导体类型且被设置成与维持区的外侧形成接触的第一区。第一区具有比基极区的结深度更大的结深度，并且具有低杂质浓度。维持区具有比第一区的结深度更小的结深度，并且具有高杂质浓度。阱扩散区具有比基极区和维持区的结深度更大的结深度，并且具有低杂质浓度。结边缘终止区和阱扩散区的雪崩击穿电压高于垂直沟槽MOS栅极类型半导体元件部分的雪崩击穿电压。
此外，在根据本发明的半导体器件中，结边缘终止区域可包括设置在所述第二绝缘薄膜上的场板。在根据本发明的半导体器件中，垂直沟槽MOS栅极类型半导体元件可以为包括集电极层的IGBT，集电极层为第二导电类型且在第一主表面的侧面上与主漏极区形成接触。
一种根据本发明的制造半导体器件的方法包括：同时形成半导体器件中所包括的第一区和阱扩散区。在根据本发明的制造半导体器件的方法中，可同时形成半导体器件中所包括的维持区和基极区。
本发明的有益效果
根据本发明，可提供一种半导体器件以及制造其的方法，该半导体器件可减小导通电阻并改进击穿电压和击穿电阻的可靠性，而无需添加新的制造工艺，并且可以低成本制造，而不会有成本的增加。
附图说明
图1是例示根据本发明的半导体器件的第一实施例的垂直沟槽栅极类型功率IC的主要部分的横截面视图。
图2是例示用于控制的一般横向平面MOS类型半导体元件的横截面视图。
图3是例示一般垂直沟槽栅极MOS类型半导体元件及其结边缘终止区的主要部分的横截面视图。
图4是例示根据本发明的半导体器件的第五实施例的另一半导体器件的主要部分的横截面视图。
图5是例示根据相关技术的垂直沟槽栅极MOS类型半导体元件及其结边缘终止区的主要部分的横截面视图。
图6是例示根据本发明的半导体器件的第一实施例的垂直沟槽栅极类型功率IC的平面视图。
图7是例示根据本发明的半导体器件的第四实施例的垂直沟槽栅极类型功率IC的修改的平面视图。
图8是例示根据本发明的半导体器件的第二实施例的垂直沟槽栅极类型功率IC的修改的主要部分的横截面视图。
图9是例示根据本发明的半导体器件的第三实施例的垂直沟槽栅极类型功率IC的修改的主要部分的横截面视图。
具体实施方式
在下文中，将参考附图详细描述根据本发明的实施例的半导体器件及其制造方法。本发明不限于以下实施例，只要不背离本发明的精神及其范围。另外，在说明书中，“击穿电压”表示在高电压被施加到截止状态的元件之时，因雪崩击穿，雪崩电流开始流动时的电压，即雪崩击穿电压。
(第一实施例)
图1是例示根据本发明的半导体器件的第一实施例的垂直沟槽栅极类型功率IC的主要部分的横截面视图。图1是例示根据本发明的复杂半导体器件的第一实施例的垂直沟槽栅极类型功率IC100的主要部分的横截面视图。
在第一实施例中，垂直沟槽栅极类型功率IC100包括：垂直沟槽栅极MOSFET元件部分30，其具有50V至100V的击穿电压，并且用作输出级半导体元件；横向n沟道MOSFET元件部分22，其具有大约10V的击穿电压，并且用作控制半导体元件；以及结边缘终止区23，其围绕元件部分。阱结18(其为包括控制半导体元件和n-外延层3的p-阱扩散区的pn结)的击穿电压以及结边缘终止区23的击穿电压等于或大于100V。
垂直沟槽栅极MOSFET元件部分30和平面栅极类型横向n沟道MOSFET元件部分(用于控制的纵向n沟道MOSFET元件部分)被形成于包括n+衬底2和外延层3的半导体衬底上。横向n沟道MOSFET元件部分22和垂直沟槽栅极MOSFET元件部分30共享n+衬底2和半导体衬底(其是设置在n+衬底2上的n-外延层3)并且彼此毗邻，且其间插入有元件隔离区90。
垂直沟槽栅极MOSFET元件部分30和用于控制的横向n沟道MOSFET元件部分22在半导体衬底上被布置成彼此平行，且其间插入有用作元件隔离区90的LOCOS氧化层11a(图1)。另外，n+衬底2是垂直沟槽栅极MOSFET元件部分30中的n型漏极区(主漏极区)。
为了解决本发明的问题，首先，当截止电压被施加以导致击穿(雪崩击穿电流)时，必须防止电流集中在结边缘终止区23并由此防止元件击穿。为了满足这些要求，用于控制的横向n沟道MOSFET元件部分22的阱结18和结边缘终止区23的击穿电压必须高于垂直沟槽栅极MOSFET元件部分30中的活跃区21中的主结19(p型基极区5和n-外延层3的pn结)的击穿电压。因此将在下文中描述该结构。
图6是例示根据本发明的半导体器件的第一实施例的垂直沟槽栅极类型功率IC的平面视图。在图6中，结边缘终止区23被布置成围绕垂直沟槽栅极MOSFET元件部分30和用于控制的横向n沟道MOSFET元件部分22。垂直沟槽栅极MOSFET元件部分30被布置在芯片的中心并且包括作为主电流路径的活跃区21。
活跃区21包括沟槽栅极结构，其中由多晶硅制成的栅极电极6a被填充到沟槽中，且其间插入有栅极氧化层7a，活跃区21还包括与沟槽栅极结构形成接触的p型基极区5。另外，活跃区21包括n+源极区8b(主源极区)，其形成于p型基极区5的表面层上并与p型基极区5和沟槽的内壁以及具有高杂质浓度的p+接触区10形成接触。源电极15与n+源极区8b和p+接触区10形成接触。源电极15是源极端子。另外，n+衬底2是MOSFET的n型漏极区。形成于n+衬底2的背表面上的漏极电极1是漏极端子。层间电介质17a被设置在源极电极15与由多晶硅制成的栅极电极6a之间。
用于控制的横向n沟道MOSFET元件部分22包括p-阱扩散区4a，以及形成于p型阱扩散区4a的表面层上的n+漏极区8a(控制漏极区)、n+源极区8b(控制源极区)、和p+接触区9。金属膜是漏极电极12或源极电极13。基极电极14充当后栅极电极，并且被连接至p+接触区9。多晶硅的栅极电极6b形成于栅极氧化层7b的上表面上。栅极电极6b是栅极端子。
LOCOS氧化层11a和与LOCOS氧化层11a形成接触的层间电介质17b被形成于垂直沟槽栅极MOSFET元件部分30与用于横向n沟道MOSFET元件部分22之间。LOCOS氧化层11a和层间电介质17b充当元件隔离区90。另外，LOCOS氧化层11b形成于横向MOSFET与形成控制电路的另一横向MOSFET(未示出)之间，并且还充当电路元件之间的元件隔离区。
结边缘终止区23具有结终止结构，用于改进击穿电压和维持击穿电压的可靠性。在结边缘终止区23中，p型维持区50被形成为在垂直沟槽栅极MOSFET元件部分30的芯片的外周端部处与沟槽形成接触，而具有低杂质浓度的p-扩散区4b被形成为与p型维持区50相接续。P型维持区50是通过与p型基极区5相同的工艺形成的扩散区，并且可在没有任何附加工艺的情况下形成。
另外，金属膜场板16和多晶硅膜场板6c形成于LOCOS氧化层11c上，该LOCOS氧化层11c形成于p-扩散区4b和n-外延层3的表面上。p-扩散区4b是由与用于控制的横向n沟道MOSFET元件部分22的p-阱扩散区4a相同的工艺形成的扩散层，并且可在没有附加工艺的情况下形成。
p-扩散区4b沿结边缘终止区23的内部以环状形成。另外，p-扩散区4b在比p型基极区5或p型维持区50的浓度小的浓度下形成，并且具有比p型基极区5或p型维持区50的扩散深度更大的扩散深度。P型维持区50在元件的任意位置处被电连接至p型基极区5。由于p-扩散区4b被如上所述形成为与p型维持区50相接续，因此其被电连接至p型维持区50。
例如，p型基极区5和p型维持区50具有1.5μm至2.5μm的扩散深度以及5×1016cm-3至9×1016cm-3的表面杂质浓度。由于p-阱扩散区4a和p-扩散区4b同时形成，因此它们具有2μm至5μm的扩散深度以及1×1016cm-3至5×1016cm-3的表面杂质浓度。
由此，p-扩散区4b具有比p型基极区5或p型维持区50的扩散深度更大的扩散深度，以及比p型基极区5或p型维持区50的杂质浓度更低的杂质浓度。因此，与其中没有形成p-扩散区4b的情形相比，增大结边缘终止区23中的耗尽层的面积是可能的。结果，在耗尽层被扩展时减小最大场强是可能的。
以此方式，由n-外延层3、以及p-阱扩散区4a和p-扩散区4b之间的pn决定的击穿电压可高于由垂直沟槽栅极MOSFET元件部分的活跃区21中的沟槽栅极的主结19或底部决定的击穿电压。
以此方式，当在截止状态中施加与击穿电压相对应的电压时，雪崩电流流入活跃区21的主结19，并且防止雪崩电流集中在结边缘终止区23上是可能的。结果，防止功率IC的雪崩击穿导致的损坏是可能的。
如以上所描述的，由于扩散区4b的p-杂质浓度与p-阱扩散区4a的杂质浓度相同，因此其高于以上提及的专利文献2中公开的p--RESURF区70(参见图5)的杂质浓度。另外，p-扩散区4b的杂质浓度必须低于与形成一般保护环的杂质浓度相等的p型基极区5的杂质浓度。这是因为在其中p-扩散区4b的表面的杂质浓度变为RESURF区的低杂质浓度下或者在垂直沟槽栅极MOSFET的p型基极区5的浓度下，难以获得用于控制的横向n沟道MOSFET元件部分22所需的阈值电压或导通电流。
本发明的另一特性在于，p型维持区50被设置成在垂直沟槽栅极MOSFET元件部分30的外周端部与沟槽形成接触并且与p-扩散区4b相接续。p型维持区50被电连接至p型基极区5。如以上所描述的，由于p-扩散区4b通过与p-阱扩散区4a相同的工艺形成，因此p-扩散区4b的杂质浓度高于RESURF区的杂质浓度，但是必须低于形成一般保护环的杂质浓度。
因此，当具有大约每单位面积1×1012/cm2的浓度的强电荷来自元件外部时，很可能在层间电介质17a与端部处的沟槽同LOCOS氧化层11c间的区域中的半导体衬底之间的界面处感生电荷。在一些情形中，在施加截止电压时被扩展的耗尽层的等电位线的分布因感生的电压而改变并且击穿电压被减小。
如以上所描述的，当p型维持区50被形成为电连接至p型基极区5时，等电位线分布通过p型维持区50分布在p-扩散区4b中。因此，即使当外部电荷进入与p型维持区50的上部分形成接触的层间电介质17a的表面时，在层间电介质17a与半导体衬底之间的界面处较不可能感生电荷，并且等电位线的分布变化可被减小至最小。其结果是，击穿电压的可靠性得以改进。
(第二实施例)
图8是例示根据本发明的半导体器件的第二实施例的垂直沟槽栅极类型功率IC的修改的主要部分的横截面视图。第二实施例是第一实施例的修改，并且与第一实施例的不同之处在于，p型维持区50与p-扩散区4b之间的重叠区被扩展以便减小外部电荷对击穿电压的影响，如图8中例示的。
具体地，放置一屏蔽，以使得在形成p型维持区50时的硼离子注入区与在形成p-扩散区4b时的硼离子注入区相重叠，且硼离子被注入到每个区中。以此方式，可能进一步增大从设置在活跃区的端部处的沟槽至LOCOS氧化层11c的部分中的p型区的表面浓度。结果，可能减小外部电荷对击穿电压的影响。
(第三实施例)
图9是例示根据本发明的半导体器件的第三实施例的垂直沟槽栅极类型功率IC的修改的主要部分的横截面视图。第三实施例是第二实施例的修改并且与第二实施例的不同之处在于，p+接触区10被附加地形成于p型维持区50的表面上以便减小外部电荷对击穿电压的影响，如图9中所例示的。根据此结构，可能进一步增大从设置在活跃区的端部处的沟槽至LOCOS氧化层11c的部分中的p型区的表面浓度。因此，可能减小外部电荷对击穿电压的影响。
(第四实施例)
图7是例示根据本发明的半导体器件的第四实施例的垂直沟槽栅极类型功率IC的修改的平面视图。在根据本发明的半导体器件的第四实施例的垂直沟槽栅极类型功率IC中，结边缘终止区23被形成为围绕垂直沟槽栅极MOSFET元件部分30，并且在半导体衬底上被布置成与用于控制的横向n沟道MOSFET元件部分22平行，且LOCOS氧化层11a充当插入其间的元件隔离区90。第四实施例与第一实施例的不同之处在于，结边缘终止区23被设置成仅围绕垂直沟槽栅极MOSFET元件部分30。当用于控制的横向n沟道MOSFET元件部分22在根据图2中例示的相关技术的结边缘终止区49中可具有足够高的击穿电压时，仅减小结边缘终止区23中的垂直沟槽栅极MOSFET元件部分30的场强是可能的。
(第五实施方式)
图4例示了本发明的第五实施例。图4例示了其中半导体层25(p+集电极层)被附加地形成于垂直沟槽栅极MOSFET元件部分30的n+衬底2的背表面上的结构，该垂直沟槽栅极MOSFET元件部分30是图1中例示的输出级半导体元件，用以获得垂直沟槽栅极IGBT24(绝缘栅极双极性晶体管)作为输出级半导体元件。
与MOSFET相比，IGBT可用作输出级元件，以便减小主电流流入其中的输出级半导体元件的活跃区中的导通电阻并增大该活跃区中的击穿电压。IGBT在大约300V或更高的额定电压下具有比MOSFET的导通电阻更低的导通电阻(导通电压)。然而，随着输出级元件的击穿电压增大，n-外延层3的特定电阻也增大。因此，在截止状态中扩展至结边缘终止区23的等电位线很可能受到外部电荷的影响。因此，p型维持区502使得能进一步降低外部电荷的影响并增大击穿电压的可靠性。
在本发明的上述实施例中，第一导电类型是n型，而第二导电类型是p型。然而，本发明不限于其中第一导电类型为n型而第二导电类型为p型的实施例。在本发明的实施例中，n型和p型可被交换以使得第一导电类型为p型而第二导电类型为n型。在此情形中，一些组件可以同以上描述相同的方式来操作。在以上所描述的本发明的实施例中，附图中每个区(p区和n区)的右侧描述的符号+(-)表示该区的杂质浓度高于(低于)其他区的杂质浓度。
工业应用性
如以上所述的，根据本发明的半导体器件和半导体器件制造方法对于复杂半导体器件(诸如具有高击穿电压的沟槽栅极类型功率IC)以及制造该复杂半导体器件的方法是有用的，在该复杂半导体器件中垂直沟槽MOS栅极类型半导体元件和用于保护和控制的半导体元件被形成于同一半导体衬底上。具体地，根据本发明的半导体器件和半导体器件制造方法适于诸如IGBT之类的MOS类型半导体器件以及制造该MOS类型半导体器件的方法，该MOS类型半导体器件可减小导通电阻并改进击穿电压和击穿电阻的可靠性的，而无需添加新的制造工艺，并且可以低成本来制造而不增加成本。

Claims (3)

1.一种制造半导体器件的方法，该半导体器件包括：
主漏极区，其为第一导电类型并且形成于第一导电类型的半导体衬底的第一主表面上；
垂直沟槽MOS栅极类型半导体元件部分，包括：基极区，所述基极区为第二导电类型且选择性地形成于所述半导体衬底的第二主表面上；主源极区，所述主源极区为第一导电类型且选择性地形成于所述基极区的表面上；沟槽，所述沟槽从所述基极区的表面穿过所述基极区和所述主源极区延伸至所述半导体衬底；以及沟槽MOS栅极，所述沟槽MOS栅极包括设置在所述沟槽中的栅极电极，且其间插入有第一绝缘薄膜，所述第一绝缘薄膜是绝缘薄膜；
毗邻所述垂直沟槽MOS栅极类型半导体元件部分的用于控制的半导体元件部分，其具有元件隔离区，该元件隔离区包括形成于所述半导体衬底的所述第二主表面上并且比插入其间的所述第一绝缘薄膜厚的第二绝缘薄膜，所述用于控制的半导体元件部分包括：阱扩散区，所述阱扩散区为第二导电类型且在所述半导体衬底的所述第二主表面上与所述半导体衬底形成pn结，用于控制的栅极电极，所述用于控制的栅极电极形成于所述阱扩散区的表面上且其间插入有比所述第二绝缘薄膜薄的第三绝缘薄膜，以及第一导电类型的控制漏极区和第一导电类型的控制源极区，它们被设置在所述阱扩散区的所述表面上且之间插入有所述控制栅极电极，并且控制所述垂直沟槽MOS栅极类型半导体元件部分；以及
结边缘终止区，所述结边缘终止区包括设置在所述半导体衬底的所述第二主表面上的所述第二绝缘薄膜并且围绕所述垂直沟槽MOS栅极类型半导体元件或者围绕所述垂直沟槽MOS栅极类型半导体元件部分和所述用于控制的半导体元件部分两者，
其中所述结边缘终止区包括为第二导电类型且在所述垂直沟槽MOS栅极类型半导体元件部分的外周端部处与所述沟槽形成接触的维持区，以及为所述第二导电类型且被设置成与所述维持区的外侧形成接触的第一区，
所述第一区具有比所述基极区的结深度更大的结深度，并且具有低杂质浓度，
所述维持区具有比所述第一区的结深度更小的结深度，并且具有高杂质浓度，
所述阱扩散区具有比所述基极区和所述维持区的结深度更大的结深度，并且具有低杂质浓度，以及
所述结边缘终止区和所述阱扩散区的雪崩击穿电压高于所述垂直沟槽MOS栅极类型半导体元件部分的雪崩击穿电压，
在制造所述半导体器件时，
同时形成所述半导体器件中所包括的所述第一区和所述阱扩散区，
同时形成所述半导体器件中所包括的所述维持区和所述基极区。
2.如权利要求1所述的制造半导体器件的方法，其特征在于，
所述结边缘终止区域包括设置在所述第二绝缘薄膜上的场板。
3.如权利要求1或2所述的制造半导体器件的方法，其特征在于，
所述垂直沟槽MOS栅极类型半导体元件部分为包括集电极层的IGBT，所述集电极层为第二导电类型且在所述第一主表面侧上与所述主漏极区形成接触。
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JP7279393B2 (ja) 2019-02-15 2023-05-23 富士電機株式会社 半導体集積回路の製造方法
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US20140008718A1 (en) 2014-01-09
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