WO2012127960A1 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- WO2012127960A1 WO2012127960A1 PCT/JP2012/054036 JP2012054036W WO2012127960A1 WO 2012127960 A1 WO2012127960 A1 WO 2012127960A1 JP 2012054036 W JP2012054036 W JP 2012054036W WO 2012127960 A1 WO2012127960 A1 WO 2012127960A1
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- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
Definitions
- the present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device including a high breakdown voltage field effect transistor and a method for manufacturing such a semiconductor device.
- LED Light Emitting Diode
- Integrated Circuits Integrated Circuits
- power supply control ICs power supply control ICs.
- an n-channel field effect transistor having an N-type well applied to the high voltage side (high side) will be described.
- An N-type well is formed from the main surface of the semiconductor substrate (P-type) to a predetermined depth, and a P-type well is formed from the surface to a predetermined depth.
- An N-type source region is formed in the P-type well from the surface to a predetermined depth.
- an N-type drain region is formed so as to surround the P-type well from the surface thereof to a predetermined depth.
- a gate electrode is formed on the P-type well portion and the N-type well portion sandwiched between the source region and the drain region with a gate insulating film interposed therebetween.
- the P-type well has a P-type back gate contact region extending from the surface to a predetermined depth in order to keep the threshold voltage to be applied to the gate electrode for forming the channel at a constant voltage. Is formed.
- the N-type source region and the P-type back gate contact region are alternately arranged in one direction (gate width direction).
- references disclosing high withstand voltage field effect transistors include, for example, Japanese Patent Application Laid-Open No. 05-267652 (Patent Document 1), Japanese Patent Application Laid-Open No. 2008-10628 (Patent Document 2) and Japanese Patent Application Laid-Open No. 11-307663 ( There exists patent document 3).
- the conventional semiconductor device has the following problems.
- an N-type impurity region having an impurity concentration lower than the impurity concentration of the N-type impurity region so as to surround each N-type impurity region of the source region and the drain region in order to prevent hot carriers and relax the electric field. -Impurity regions are formed.
- the impurity concentration of the N-impurity region is lower than the impurity concentration of the P-type back gate contact region, but the N-impurity region is formed deeper than the back gate contact region. For this reason, the N ⁇ impurity region is positioned as a high resistance region between the P type back gate contact region and the P type well region. Then, even if 0V is applied to the back gate contact region and the potential of the P-type well is fixed to 0V, the potential of the P-type well may float.
- the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device in which the junction breakdown caused by the parasitic bipolar transistor is suppressed.
- a method for manufacturing a semiconductor device is provided.
- a semiconductor device includes a first conductivity type semiconductor substrate having a main surface, a first conductivity type first impurity region, a second conductivity type second impurity region, and a second conductivity type.
- a third impurity region of conductivity type, a fourth impurity region of first conductivity type, a fifth impurity region of second conductivity type, and an electrode portion are provided.
- the first impurity region of the first conductivity type is formed over a predetermined depth from the main surface of the semiconductor substrate and has a first impurity concentration.
- the second impurity region of the second conductivity type is formed from the surface of the first impurity region to a predetermined depth so as to be surrounded from the side and below by the first impurity region, and has a second impurity concentration.
- the third impurity region of the second conductivity type is formed from the surface of the second impurity region to a predetermined depth so as to be surrounded from the side and below by the second impurity region, and is a third impurity concentration higher than the second impurity concentration. Has an impurity concentration.
- the fourth impurity region of the first conductivity type is formed from the surface of the first impurity region to a predetermined depth so as to be surrounded from the side and below by the first impurity region, and is in direct contact with the first impurity region.
- the fourth impurity concentration is higher than the one impurity concentration.
- the fifth impurity region of the second conductivity type is formed from the main surface of the semiconductor substrate to a predetermined depth with a distance from the first impurity region.
- the electrode portion is formed on a region sandwiched between the second impurity region and the fifth impurity region.
- a plurality of fourth impurity regions are formed. The plurality of fourth impurity regions are arranged at intervals in a direction intersecting the direction of the current flowing between the second impurity region and the fifth impurity region by applying a predetermined voltage to the electrode portion.
- a semiconductor device includes a first conductivity type semiconductor substrate having a main surface, a first conductivity type first impurity region, a second conductivity type second impurity region, A second impurity type third impurity region, a first conductivity type fourth impurity region, an isolation region, a second conductivity type fifth impurity region, and an electrode portion are provided.
- the first impurity region of the first conductivity type is formed over a predetermined depth from the main surface of the semiconductor substrate and has a first impurity concentration.
- the second impurity region of the second conductivity type is formed from the surface of the first impurity region to a predetermined depth so as to be surrounded from the side and below by the first impurity region, and has a second impurity concentration.
- the third impurity region of the second conductivity type is formed over a predetermined depth from the surface of the second impurity region so as to be surrounded from the side and below by the second impurity region, and is in direct contact with the first impurity region.
- the third impurity concentration is higher than the two impurity concentration.
- the fourth impurity region of the first conductivity type is formed from the surface of the first impurity region to a predetermined depth so as to be surrounded from the side and below by the first impurity region, and is a fourth impurity concentration higher than the first impurity concentration. Has an impurity concentration.
- the isolation region is formed between the third impurity region and the fourth impurity region, and electrically isolates the third impurity region and the fourth impurity region.
- the fifth impurity region of the second conductivity type is formed from the main surface of the semiconductor substrate to a predetermined depth with a distance from the first impurity region.
- the electrode portion is formed on a region sandwiched between the second impurity region and the fifth impurity region.
- a semiconductor device manufacturing method includes the following steps.
- a first conductivity type semiconductor substrate having a main surface is prepared.
- a first impurity region of the first conductivity type having a first impurity concentration is formed from the main surface of the semiconductor substrate to a predetermined depth.
- a second impurity region of the second conductivity type having a second impurity concentration is formed from the surface of the first impurity region to a predetermined depth so as to be surrounded by the first impurity region from the side and from below.
- the first impurity region has a fourth impurity concentration higher than the first impurity concentration over a predetermined depth from the surface of the first impurity region so as to be surrounded from the side and the lower side by the first impurity region, and is in direct contact with the first impurity region.
- a fourth impurity region of one conductivity type is formed.
- a fifth conductivity region of the second conductivity type is formed from the main surface of the semiconductor substrate to a predetermined depth with a distance from the first impurity region.
- An electrode portion is formed on a region sandwiched between the second impurity region and the fifth impurity region.
- the second impurity region is formed by implanting a second conductivity type impurity obliquely with respect to the surface of the semiconductor substrate through a predetermined implantation mask.
- a direction intersecting the direction of the current flowing between the first impurity region and the fifth impurity region by applying a predetermined voltage to the electrode portions of the plurality of fourth impurity regions. Are formed at intervals.
- a manufacturing method of a semiconductor device includes the following steps.
- a first conductivity type semiconductor substrate having a main surface is prepared.
- a first impurity region of the first conductivity type having a first impurity concentration is formed from the main surface of the semiconductor substrate to a predetermined depth.
- a second impurity region of the second conductivity type having a second impurity concentration is formed from the surface of the first impurity region to a predetermined depth so as to be surrounded by the first impurity region from the side and from below.
- the first impurity region has a fourth impurity concentration higher than the first impurity concentration over a predetermined depth from the surface of the first impurity region so as to be surrounded from the side and the lower side by the first impurity region, and is in direct contact with the first impurity region.
- a fourth impurity region of one conductivity type is formed.
- An isolation region that electrically isolates the third impurity region and the fourth impurity region is formed between the third impurity region and the fourth impurity region.
- a fifth conductivity region of the second conductivity type is formed from the main surface of the semiconductor substrate to a predetermined depth with a distance from the first impurity region.
- An electrode portion is formed on a region sandwiched between the second impurity region and the fifth impurity region.
- the operation of the parasitic bipolar transistor can be suppressed and the junction breakdown can be prevented.
- a method of manufacturing a semiconductor device According to a method of manufacturing a semiconductor device according to one embodiment and another embodiment of the present invention, it is possible to easily manufacture a semiconductor device in which the operation of a parasitic bipolar transistor is suppressed and junction breakdown can be prevented. Can do.
- FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention.
- FIG. 3 is a cross-sectional view taken along a cross-sectional line III-III shown in FIG. 2 in the same embodiment.
- FIG. 4 is a cross-sectional view taken along a cross-sectional line IV-IV shown in FIG. 2 in the same embodiment.
- FIG. 5 is a cross-sectional view taken along a cross-sectional line VV shown in FIG. 2 in the same embodiment.
- FIG. 3 is a cross-sectional view taken along a cross-sectional line III-III shown in FIG. 2 in the same embodiment.
- FIG. 4 is a cross-sectional view taken along a cross-sectional line IV-IV shown in FIG. 2 in the same embodiment.
- FIG. 5 is a cross-sectional view taken along a cross-sectional line VV shown in FIG. 2 in the same embodiment.
- FIG. 3 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device in the embodiment
- (A) is a cross-sectional view corresponding to a cross-sectional line III-III shown in FIG. 2
- (B) is a cross-sectional view
- 4 is a cross-sectional view taken along a cross-sectional line corresponding to the cross-sectional line VV shown in FIG. 2
- (C) is a cross-sectional view taken along a cross-sectional line corresponding to the cross-sectional line IV-IV shown in FIG.
- FIG. 7 is a cross-sectional view showing a step performed after the step shown in FIG.
- (A) is a cross-sectional view taken along a cross-sectional line corresponding to the cross-sectional line III-III shown in FIG. ) Is a cross-sectional view taken along a cross-sectional line VV shown in FIG. 2, and (C) is a cross-sectional view taken along a cross-sectional line IV-IV shown in FIG.
- FIG. 8 is a cross-sectional view showing a step performed after the step shown in FIG. 7 in the embodiment, (A) is a cross-sectional view taken along a cross-sectional line corresponding to the cross-sectional line III-III shown in FIG. ) Is a cross-sectional view taken along a cross-sectional line VV shown in FIG.
- FIG. 9 is a cross-sectional view showing a step performed after the step shown in FIG. 8 in the embodiment
- (A) is a cross-sectional view taken along a cross-sectional line corresponding to the cross-sectional line III-III shown in FIG. ) Is a cross-sectional view taken along a cross-sectional line VV shown in FIG. 2
- (C) is a cross-sectional view taken along a cross-sectional line IV-IV shown in FIG.
- FIG. 10 is a cross-sectional view showing a step performed after the step shown in FIG.
- (A) is a cross-sectional view taken along a cross-sectional line corresponding to cross-sectional line III-III shown in FIG. ) Is a cross-sectional view taken along a cross-sectional line VV shown in FIG. 2, and (C) is a cross-sectional view taken along a cross-sectional line IV-IV shown in FIG.
- FIG. 11 is a cross-sectional view showing a step performed after the step shown in FIG. 10 in the embodiment
- (A) is a cross-sectional view taken along a cross-sectional line corresponding to the cross-sectional line III-III shown in FIG. ) Is a cross-sectional view taken along a cross-sectional line VV shown in FIG.
- FIG. 12 is a cross-sectional view showing a step performed after the step shown in FIG. 11 in the same embodiment
- (A) is a cross-sectional view taken along a cross-sectional line corresponding to the cross-sectional line III-III shown in FIG. ) Is a cross-sectional view taken along a cross-sectional line VV shown in FIG. 2
- (C) is a cross-sectional view taken along a cross-sectional line IV-IV shown in FIG. It is a top view of the semiconductor device concerning a comparative example.
- FIG. 14 is a sectional view taken along a sectional line XIV-XIV shown in FIG.
- FIG. 14 is a cross-sectional view taken along a cross-sectional line XV-XV shown in FIG.
- FIG. 14 is a sectional view taken along a sectional line XVI-XVI shown in FIG. 13.
- It is a graph which shows the impurity concentration profile for demonstrating the problem in the semiconductor device which concerns on a comparative example.
- It is sectional drawing which shows the parasitic bipolar transistor for demonstrating the problem in the semiconductor device which concerns on a comparative example.
- It is a graph which shows the measurement result of the drain voltage and drain current for demonstrating the problem in the semiconductor device which concerns on a comparative example.
- it is a graph which shows the measurement result of drain voltage and drain current.
- FIG. 22 is a cross sectional view taken along a cross sectional line XXII-XXII shown in FIG. 21 in the embodiment.
- FIG. 22 is a cross sectional view taken along a cross sectional line XXIII-XXIII shown in FIG. 21 in the embodiment.
- FIG. 22 is a cross sectional view taken along a cross sectional line XXIV-XXIV shown in FIG. 21 in the embodiment.
- FIG. 26 is a cross sectional view taken along a cross sectional line XXVI-XXVI shown in FIG. 25 in the embodiment.
- FIG. 26 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device in the embodiment, taken along a cross-sectional line corresponding to cross-sectional line XXVI-XXVI shown in FIG. 25.
- FIG. 26 is a cross-sectional view showing a step performed after the step shown in FIG. 27 in the embodiment, and is a cross-sectional view taken along a cross-sectional line corresponding to cross-sectional line XXVI-XXVI shown in FIG.
- FIG. 26 is a cross-sectional view showing a process performed at the trace of the process shown in FIG. 28 in the embodiment, and is a cross-sectional view taken along a cross-sectional line corresponding to cross-sectional line XXVI-XXVI shown in FIG.
- FIG. 31 is a sectional view taken along a sectional line XXXI-XXXI shown in FIG. 30 in the embodiment.
- FIG. 31 is a cross sectional view taken along a cross sectional line XXXII-XXXII shown in FIG. 30 in the embodiment.
- FIG. 31 is a cross sectional view taken along a cross sectional line XXXIII-XXXIII shown in FIG. 30 in the same embodiment.
- FIG. 31 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device in the embodiment, (A) is a cross-sectional view taken along a cross-sectional line XXXI-XXXI shown in FIG. 30, and (B) 30 is a cross-sectional view taken along a cross-sectional line XXXII-XXXII shown in FIG. 30, and (C) is a cross-sectional view taken along a cross-sectional line XXXIII-XXXIII shown in FIG.
- FIG. 35 is a cross-sectional view showing a step performed after the step shown in FIG.
- FIG. 34 in the embodiment (A) is a cross-sectional view taken along a cross-sectional line XXXI-XXXI shown in FIG. ) Is a cross-sectional view taken along a cross-sectional line XXXII-XXXII shown in FIG. 30, and (C) is a cross-sectional view taken along a cross-sectional line XXXIII-XXXIII shown in FIG. 30.
- FIG. 36 is a cross-sectional view showing a step performed after the step shown in FIG. 35 in the embodiment, (A) is a cross-sectional view taken along a cross-sectional line XXXI-XXI shown in FIG.
- FIG. 37 is a cross-sectional view showing a step performed after the step shown in FIG. 36 in the embodiment
- A is a cross-sectional view taken along a cross-sectional line XXXI-XXXI shown in FIG.
- FIG. 38 is a cross-sectional view showing a step performed after the step shown in FIG. 37 in the embodiment, (A) is a cross-sectional view taken along a cross-sectional line XXXI-XXXI shown in FIG. ) Is a cross-sectional view taken along a cross-sectional line XXXII-XXXII shown in FIG. 30, and (C) is a cross-sectional view taken along a cross-sectional line XXXIII-XXXIII shown in FIG. 30.
- FIG. 38 is a cross-sectional view showing a step performed after the step shown in FIG. 37 in the embodiment, (A) is a cross-sectional view taken along a cross-sectional line XXXI-XXXI shown in FIG. ) Is a cross-sectional view taken along a cross-sectional line XXXII-XXXII shown in FIG. 30, and (C) is a cross-sectional view taken along a cross
- FIG. 39 is a cross-sectional view showing a step performed after the step shown in FIG. 38 in the embodiment
- (A) is a cross-sectional view taken along a cross-sectional line XXXI-XXXI shown in FIG. ) Is a cross-sectional view taken along a cross-sectional line XXXII-XXXII shown in FIG. 30, and
- (C) is a cross-sectional view taken along a cross-sectional line XXIII-XXXIII shown in FIG. 30.
- FIG. 41 is a cross sectional view taken along a cross sectional line XLI-XLI shown in FIG. 40 in the embodiment.
- FIG. 41 is a cross sectional view taken along a cross sectional line XLII-XLII shown in FIG. 40 in the embodiment.
- FIG. 41 is a cross sectional view taken along a cross sectional line XLIII-XLIII shown in FIG. 40 in the embodiment. It is a top view of the semiconductor device which concerns on Embodiment 6 of this invention.
- FIG. 45 is a cross sectional view taken along a cross sectional line XLV-XLV shown in FIG. 44 in the embodiment.
- FIG. 45 is a cross sectional view taken along a cross sectional line XLVI-XLVI shown in FIG. 44 in the embodiment.
- FIG. 45 is a cross sectional view taken along a cross sectional line XLVII-XLVI shown in FIG.
- FIG. 49 is a cross sectional view taken along a cross sectional line XLIX-XLIX shown in FIG. 48 in the embodiment. It is a top view of the semiconductor device which concerns on Embodiment 8 of this invention.
- FIG. 51 is a cross sectional view taken along a cross sectional line LI-LI shown in FIG. 50 in the embodiment.
- FIG. 51 is a cross sectional view taken along a cross sectional line LII-LII shown in FIG. 50 in the embodiment.
- FIG. 51 is a cross sectional view taken along a cross sectional line LIII-LIII shown in FIG. 50 in the embodiment.
- a semiconductor device applied as a control IC for a power supply or the like has a mode of controlling a plurality of different voltages.
- FIG. 1 in this type of semiconductor device, in terms of circuit, an N-channel high breakdown voltage field effect transistor TNH that controls a relatively high voltage and an N-channel that controls a relatively low voltage.
- a high-voltage field-effect transistor TNL of a type is connected in series.
- an N-type well is formed in order to electrically isolate a source region from a semiconductor substrate.
- an N-type well is not formed in an N-channel field effect transistor (low-side field effect transistor) that controls a low voltage.
- Embodiment 1 a first example of a semiconductor device including a high-side field effect transistor will be described.
- isolation regions BRU and BRS defining element formation regions for forming a source region and a drain region, respectively, in predetermined regions of a P-type semiconductor substrate SUB. Is formed.
- Isolation regions BRU and BRS are formed of, for example, a LOCOS (LoCal Oxidation of Silicon) oxide film.
- an N-type well NW having a relatively low impurity concentration (about 1 ⁇ 10 16 / cm 3 ) is formed from the surface to a predetermined depth.
- the portion of the N-type well NW sandwiched between the isolation region BRS and the isolation region BRU has a predetermined depth from the surface of the N-type well so as to be surrounded by the N-type well NW from the side and below.
- the portion of the N-type well NW located inside the isolation region BRU has a predetermined impurity concentration (3) from the surface of the N-type well to a predetermined depth so as to be surrounded by the N-type well NW from the side and below.
- a P-type well PW is formed as a back gate region having about ⁇ 10 17 / cm 3 .
- the P-type well PW has a relatively low impurity concentration (about 1 ⁇ 10 18 / cm 3 ) over a predetermined depth from the surface of the P-type well so as to be surrounded by the P-type well PW from the side and the lower side.
- An N-type source region NS is formed.
- the portion of the N-type source region NS has a relatively high impurity concentration (1 ⁇ 10 5) over a predetermined depth from the surface of the portion of the N-type source region NS so as to be surrounded by the N-type source region from the side and below.
- N + type source region NNS having about 19 / cm 3 ) is formed.
- the P-type well PW has a relatively high impurity concentration (1 ⁇ 10 19 / cm 3) over a predetermined depth from the surface of the P-type well PW so as to be surrounded by the P-type well PW from the side and the lower side.
- P + type impurity region BCR as a back gate contact region is formed.
- the portion of the N-type drain region ND has a relatively high impurity concentration over a predetermined depth from the surface of the portion of the N-type drain region ND so as to be surrounded by the N-type drain region ND from the side and below.
- N + type drain region NND having about 1 ⁇ 10 19 / cm 3 is formed.
- a gate electrode G is formed on the P-type well PW portion and the N-type well NW portion sandwiched between the N-type source region NS and the N-type drain region ND with the gate insulating film GZ interposed therebetween. ing.
- An interlayer insulating film DF is formed so as to cover the gate electrode G.
- Contact holes CHS, CHD, and CHB are formed so as to penetrate the interlayer insulating film DF.
- a contact plug CPS electrically connected to the N + type source region NNS is formed in the contact hole CHS.
- a contact plug CPD electrically connected to the N + type drain region NND is formed in the contact hole CHD.
- a contact plug CPB electrically connected to the P + type impurity region BCR is formed in the contact hole CHB.
- a metal wiring MLS electrically connected to the contact plug CPS is formed, and a metal wiring MLD electrically connected to the contact plug CPD is formed. Further, a metal wiring MLB that is electrically connected to the contact plug CPB is formed.
- the N-type source region NS and the P-type well PW intersect with the direction in which current flows between the N-type source region NS and the N-type drain region ND (substantially orthogonal). ) Are alternately arranged in the direction.
- the gate electrode G is formed so as to surround the N-type source regions NS and the P-type well PW that are alternately arranged.
- the N-type source region NS is formed in a portion of the P-type well PW located immediately below the N + -type source region NNS, and is located immediately below the P + -type impurity region BCR. It is not formed in the portion of the P-type well PW. For this reason, the P + type impurity region BCR as the back gate contact region is in direct contact with the portion of the P type well PW.
- a source region, a drain region, and the like are respectively formed in predetermined regions in the P-type semiconductor substrate SUB by, for example, LOCOS method.
- Isolation regions BRU and BRS that define element formation regions for formation are formed.
- a photoresist (not shown) is formed so as to expose the region of the semiconductor substrate SUB surrounded by the separation region BRS.
- the photoresist mask for example, phosphorus is implanted into the exposed region of the semiconductor substrate SUB with a predetermined implantation energy, so that FIG. 7A, FIG. 7B, and FIG. As shown, an N-type well NW is formed from the surface of the semiconductor substrate SUB to a predetermined depth. Thereafter, the photoresist is removed.
- a photoresist (not shown) is formed so as to expose a portion of the N-type well NW sandwiched between the isolation region BRS and the isolation region BRU.
- phosphorus is implanted into the exposed portion of the N-type well NW with a predetermined implantation energy, whereby FIGS. 8 (A), 8 (B), and 8 (C).
- An N-type drain region ND is formed from the surface of the N-type well NW to a predetermined depth. Thereafter, the photoresist is removed.
- a photoresist (not shown) is formed so as to expose a predetermined region in the N-type well NW surrounded by the isolation region BRU.
- boron is implanted into a predetermined region of the N-type well NW exposed with a predetermined implantation energy, whereby FIG. 8A, FIG. 8B, and FIG.
- a P-type well PW that becomes a back gate region is formed from the surface to a predetermined depth.
- the P-type well PW is surrounded by the N-type well NW from the side and the lower side thereof, thereby becoming a region electrically isolated from the semiconductor substrate SUB. Thereafter, the photoresist is removed.
- a gate insulating film GZ (see FIG. 9) is formed on the exposed surface of the N-type well NW or the like, and a conductive film (not shown) is formed on the gate insulating film.
- the conductive film is subjected to a predetermined photoengraving process and processing, so that a P-type well PW and an N-type are formed as shown in FIGS. 9A, 9B, and 9C.
- a gate electrode G is formed on a portion of the N-type well NW and a portion of the P-type well PW sandwiched between the drain regions ND with a gate insulating film GZ interposed therebetween.
- the P + type impurity region BCR (FIG. 10B) of the portion of the P type well PW that is not covered with the gate electrode G and exposed.
- the photoresist RM is formed so as to cover the region in which the N + type source region NNS (see FIG. 3) is to be formed.
- phosphorus is obliquely implanted at an inclination angle of about 45 ° with respect to the surface of the semiconductor substrate SUB, thereby extending a predetermined depth from the exposed surface of the P-type well PW.
- N-type source region NS is formed. Thereafter, the photoresist RM is removed.
- an insulating film such as a silicon oxide film is formed so as to cover the gate electrode G.
- anisotropic etching is performed on the entire surface of the insulating film, so that FIG.
- an insulating film spacer SS is formed on the side wall of the gate electrode G.
- the photoresist is covered so as to cover the region where the P + type impurity region BCR (see FIG. 4) is to be formed and to expose the region where the N + type source region NNS (see FIG. 4) is to be formed. (Not shown) is formed.
- the N-type source region NS is surrounded by the N-type source region NS from the side and the lower side.
- the N + type source region NNS is formed from the surface of the N type source region NS to a predetermined depth.
- an N + -type drain region NND is formed from the surface to a predetermined depth.
- a photoresist is exposed so as to expose a region where the P + type impurity region BCR (see FIG. 4) is to be formed and cover a region where the N + type source region NNS (see FIG. 4) is to be formed. (Not shown) is formed.
- boron is implanted with a predetermined implantation energy using the photoresist as a mask, thereby forming a P + type impurity region BCR as a back gate contact region. Thereafter, the photoresist is removed.
- an interlayer insulating film DF is formed so as to cover the gate electrode G and the like.
- contact holes CHS, CHD, and CHB (see FIG. 12) exposing the N + type source region NNS, the N + type drain region NND, and the P + type impurity region BCR are formed in the interlayer insulating film DF.
- a contact plug CPS electrically connected to the N + type source region NNS is formed in the contact hole CHS exposing the N + type source region NNS.
- a contact plug CPD electrically connected to the N + type drain region NND is formed in the contact hole CHD exposing the N + type drain region NND.
- a contact plug CPB electrically connected to the P + type impurity region BCR is formed in the contact hole CHB exposing the P + type impurity region BCR.
- a predetermined conductive film (not shown) is formed on the surface of the interlayer insulating film DF.
- a metal wiring MLS electrically connected to the contact plug CPS is formed, and a metal electrically connected to the contact plug CPD is formed.
- a wiring MLD is formed.
- a metal wiring MLB that is electrically connected to the contact plug CPB is formed.
- a logic circuit and the like are simultaneously formed on the same semiconductor substrate in addition to the high breakdown voltage field effect transistor. For this reason, for example, a process such as ion implantation is performed simultaneously with an ion implantation process when forming an element such as a logic circuit.
- the N-type source region NS is formed only in a region immediately below the N + -type source region NNS, and is formed in a region immediately below the P + -type impurity region BCR. It has not been. Therefore, the P + type impurity region BCR as the back gate contact region is in direct contact with the P type well PW as the back gate region. Thereby, the operation of the parasitic bipolar transistor is suppressed, and the junction breakdown of the high-voltage field-effect transistor can be prevented. This will be described with reference to a semiconductor device according to a comparative example.
- the N-type source region (HNS) is formed in both the region immediately below the N + -type impurity region (NNS) and the region immediately below the P + -type impurity region (BCR). Except for this, the semiconductor device has the same structure as that of the semiconductor device shown in FIG.
- an N-type well JNW is formed in a predetermined region of a P-type semiconductor substrate JSUB from the surface to a predetermined depth.
- An N-type drain region JND and a P-type well JPW are formed in predetermined regions of the N-type well JNW from the surface to a predetermined depth.
- An N-type source region JNS is formed in the P-type well JPW from the surface thereof to a predetermined depth.
- An N + type source region JNNS is formed at a predetermined depth from the surface of the N type source region JNS.
- a P + type impurity region JBCR as a back gate contact region is formed in the P type well JPW.
- an N + type drain region JNDN is formed in a portion of the N type drain region JND from the surface to a predetermined depth.
- a gate electrode JG is formed on the P-type well JPW portion and the N-type well JNW portion sandwiched between the N-type source region JNS and the N-type drain region JND.
- the N + type source region JNNS is electrically connected to the metal wiring JMLS via the plug CCPS
- the N + type drain region JNDD is electrically connected to the metal wiring JMLD via the plug JCPD
- the P + type impurity region JBCR is Are electrically connected to the metal wiring JMLB via the plug JCPB.
- the P + -type impurity region JBCR Ions are also implanted into the region located immediately below, and an N-type source region JNS is formed so as to surround the P + type impurity region JBCR. As shown in FIG.
- the N-type source region JNR includes a P + -type impurity region JBCR as a back gate contact region, It is located as a high resistance region between the P-type well JPW as a back gate region.
- the potential of the P type well PW may float.
- a parasitic bipolar transistor having the N-type source region NS as an emitter, the P + type impurity region BCR as a base, and the N-type drain region ND as a collector operates.
- the N-type source region NS is formed only in a region immediately below the N + -type source region NNS, and is formed in a region immediately below the P + -type impurity region BCR. It has not been. Therefore, the P + type impurity region BCR as the back gate contact region is in direct contact with the P type well PW as the back gate region. Therefore, when 0V is applied to the P + type impurity region BCR, the potential of the P type well PW is surely fixed to 0V without floating. As a result, as shown in FIG. 20, it is possible to prevent the parasitic bipolar transistor from operating and to suppress the drain current from rapidly increasing. As a result, it is possible to prevent the junction breakdown of the high breakdown voltage field effect transistor.
- the N-type source region NS extends in the gate width direction, and the N-type source region NS and the N-type drain region ND. Can be secured. As a result, it is possible to suppress a decrease in current driving capability as a field effect transistor.
- Embodiment 2 a second example of a semiconductor device including a high-side field effect transistor will be described.
- the P + type impurity region BCR as the back gate contact region intersects (substantially orthogonally) the direction (longitudinal) In the direction).
- An N + type source region NNS is formed so as to surround the P + type impurity region BCR in a plane.
- Planar means layout (two-dimensional).
- N-type source region NS is formed in a region located immediately below N + -type source region NNS, and is not formed in a region located directly below P + -type impurity region BCR. Since the configuration other than this is the same as the configuration of the semiconductor device shown in FIGS. 2, 3, 4, and 5, the same members are denoted by the same reference numerals and description thereof will not be repeated.
- the semiconductor device described above can be manufactured through the same process as that of the semiconductor device according to the first embodiment only by changing the arrangement pattern of the P + type impurity region BCR. That is, through the steps corresponding to FIGS. 10A, 10B, and 10C and the steps corresponding to FIGS. 11A, 11B, and 11C, N-type source region NS, N + -type source region NNS, and P + -type impurity region BCR shown in FIGS. 21, 22, 23, and 24 are formed.
- the P + type impurity region BCR is formed so as to be in direct contact with the P type well PW, in addition to the effect of suppressing the operation of the parasitic bipolar transistor, the following effect is obtained. can get.
- the N + type source region NNS is formed so as to surround the P + type impurity region BCR from the side, and the N type source region NS is formed immediately below the N + type source region NNS. .
- the length in which the N-type source region NS and the N-type drain region ND face each other is further increased.
- the current driving capability can be further improved as a field effect transistor.
- Embodiment 3 a third example of a semiconductor device including a high-side field effect transistor will be described.
- an N + type source region NNS is formed so as to surround the P + type impurity region BCR as a back gate contact region, and the P + type impurity region BCR and the N + type source are formed.
- a separation region BRN is formed between the region NNS.
- the N-type source region NS is formed in a region located immediately below the N + -type source region NNS, and is not formed in a region located directly below the P + -type impurity region BCR. Since the configuration other than this is the same as the configuration of the semiconductor device shown in FIGS. 2, 3, 4, and 5, the same members are denoted by the same reference numerals and description thereof will not be repeated.
- the semiconductor device described above can be manufactured through the same process as that of the semiconductor device according to the first embodiment only by changing the arrangement pattern of the isolation regions.
- separation regions BRU, BRS, and BRN corresponding to the plane pattern shown in FIG. 25 are formed in predetermined regions in the P-type semiconductor substrate SUB.
- separation regions BRU, BRS, and BRN corresponding to the plane pattern shown in FIG. 25 are formed in predetermined regions in the P-type semiconductor substrate SUB.
- an N-type source region NS, an N + -type source region NNS, a P + -type impurity region BCR, and the like are formed.
- N + type source region NNS via contact plug CPS.
- Metal wiring MLS electrically connected to N + type drain region NND through contact plug CPD
- metal wiring MLB electrically connected to P + type impurity region BCR through contact plug CPB. And are formed respectively.
- the P + type impurity region BCR is formed so as to be in direct contact with the P type well PW, in addition to the effect of suppressing the operation of the parasitic bipolar transistor, the following effect is obtained. can get.
- the isolation region BRN is formed between the P + type impurity region BCR and the N + type source region NNS.
- the P + type impurity region BCR and the N + type source region NNS can be electrically separated.
- a voltage (source potential) applied to the N + type source region NNS is applied to the P + type impurity region BCR. It is possible to apply to a usage in which a certain level is floated with respect to the applied voltage (back gate potential).
- Embodiment 4 a fourth example of a semiconductor device including a high-side field effect transistor will be described.
- the N-type source region NS is formed so as to surround the N + -type source region NNS from the side and the lower side.
- a P + type contact injection region PSAC as a projecting portion reaching the P type well PW from the N + type source region NNS is formed so as to penetrate the N type source region NS. Since the configuration other than this is the same as the configuration of the semiconductor device shown in FIGS. 2, 3, 4, and 5, the same members are denoted by the same reference numerals and description thereof will not be repeated.
- FIG. 34 (A), FIG. 34 (B) and FIG. 34 (C) the gate electrode G is formed.
- a region where the P + type impurity region BCR see FIG. 33
- an N + type source region NNS see FIG. 33.
- a photoresist (not shown) is formed so as to expose the region where the) will be formed.
- an N + -type source region NNS and a P + -type impurity region BCR are formed from the surface to a predetermined depth. Further, an N + type drain region NND is formed in the N type drain region ND from the surface to a predetermined depth.
- an interlayer insulating film DF is formed on the semiconductor substrate SUB so as to cover the gate electrode G.
- contact holes CHS, CHD, and CHB exposing the N + type source region NNS, the N + type drain region NND, and the P + type impurity region BCR are formed in the interlayer insulating film DF.
- the contact holes CHB exposing the P + type impurity regions BCR are left, and the other contact holes CHS and CHD are exposed to photoresist. Cover with PMS.
- boron is implanted at a predetermined energy into the P + type impurity region BCR through the contact hole CHB, so that the P + type contact reaching the P type well PW from the P + type impurity region BCR.
- An implantation region PSAC is formed. This P + type contact implantation region PSAC has an impurity concentration of about 5 ⁇ 10 18 / cm 3 .
- metal interconnection MLB electrically connected to P + type impurity region BCR is formed.
- the P + type impurity region BCR is electrically connected to the P type well PW via the P + type contact injection region PSAC, the operation of the parasitic bipolar transistor can be suppressed. The following effects can be obtained.
- the N-type source region NS is formed on the side and below the P + -type impurity region BCR, except for the portion where the P + -type contact implantation region PSAC is located.
- the length in which the N-type source region NS and the N-type drain region ND face each other is longer than the length in the semiconductor device described in the first embodiment.
- the current drive capability of the field effect transistor can be further improved.
- Embodiment 5 a first example of a semiconductor device including a low-side field effect transistor will be described.
- the semiconductor device according to the present embodiment is the same as that of FIG. 2, except that the N-type well NW (see FIG. 2 and the like) is not formed. 3, since it is the same as that of the structure of the semiconductor device shown in FIG. 4, FIG. 5, the same code
- the semiconductor device described above is manufactured by omitting the step of forming the N-type well NW from the series of manufacturing steps described in the first embodiment. That is, after the process shown in FIGS. 6A, 6B, and 6C, the process shown in FIGS. 8A, 8B, and 8C is changed from the process shown in FIG. A) A semiconductor device is manufactured through the steps shown in FIGS. 12B and 12C.
- the P + type impurity region BCR is formed so as to be in direct contact with the P type well PW, and the P type well PW is in direct contact with the P type semiconductor substrate SUB.
- the potential is stable and the operation of the parasitic bipolar transistor can be suppressed.
- this semiconductor device has an advantageous structure when it is not necessary to electrically isolate the P-type well PW from the semiconductor substrate SUB.
- Embodiment 6 a second example of a semiconductor device including a low-side field effect transistor will be described.
- the semiconductor device according to the present embodiment is the same as that of FIG. 21, except that the N-type well NW (see FIG. 1 and the like) is not formed. Since the configuration is the same as that of the semiconductor device shown in FIGS. 22, 23, and 24, the same reference numerals are given to the same members, and the description thereof will not be repeated.
- the semiconductor device described above is manufactured by omitting the step of forming the N-type well NW among the manufacturing steps described in the second embodiment.
- the P + type impurity region BCR is formed so as to be in direct contact with the P type well PW, and the P type well PW is in direct contact with the P type semiconductor substrate SUB.
- the potential is stable and the operation of the parasitic bipolar transistor can be suppressed.
- the N + type source region NNS is formed so as to surround the P + type impurity region BCR from the side, and the N type source region NS is formed immediately below the N + type source region NNS. Is formed.
- the length in which the N-type source region NS and the N-type drain region ND face each other is further increased.
- the current driving capability can be further improved as a field effect transistor.
- this semiconductor device has an advantageous structure when it is not necessary to electrically isolate the P-type well PW from the semiconductor substrate SUB.
- Embodiment 7 a third example of a semiconductor device including a low-side field effect transistor will be described.
- the semiconductor device according to the present embodiment is the same as the semiconductor device shown in FIGS. 25 and 26 except that the N-type well NW (see FIG. 1 and the like) is not formed. Since it is the same as that of a structure, the same code
- the semiconductor device described above is manufactured by omitting the step of forming the N-type well NW among the manufacturing steps described in the third embodiment.
- the P + type impurity region BCR is formed so as to be in direct contact with the P type well PW, and the P type well PW is in direct contact with the P type semiconductor substrate SUB.
- the potential is stable and the operation of the parasitic bipolar transistor can be suppressed.
- the isolation region BRS is formed between the P + type impurity region BCR and the N + type source region NNS.
- the P + type impurity region BCR and the N + type source region NNS can be electrically separated.
- a voltage (source potential) applied to the N + type source region NNS is applied to the P + type impurity region BCR. It is possible to apply to a usage in which a certain level is floated with respect to the applied voltage (back gate potential).
- Embodiment 8 a fourth example of a semiconductor device including a low-side field effect transistor will be described.
- the semiconductor device according to the present embodiment is the same as that of FIG. 30, except that the N-type well NW (see FIG. 2 and the like) is not formed. Since it is the same as the configuration of the semiconductor device shown in FIG. 31, FIG. 32 and FIG. 33, the same members are denoted by the same reference numerals and the description thereof will not be repeated.
- the semiconductor device described above is manufactured by omitting the step of forming the N-type well NW among the manufacturing steps described in the fourth embodiment.
- the P + type impurity region BCR is formed so as to be in direct contact with the P type well PW, and the P type well PW is in direct contact with the P type semiconductor substrate SUB.
- the potential is stable and the operation of the parasitic bipolar transistor can be suppressed.
- the N-type source region NS is formed on the side and the lower side of the P + -type impurity region BCR except for the portion where the P + -type contact implantation region PSAC is located. Is formed.
- the length in which the N-type source region NS and the N-type drain region ND face each other is longer than the length in the semiconductor device described in the first embodiment. As a result, the current drive capability of the field effect transistor can be further improved.
- the high-side high breakdown voltage N-type field effect transistor and the low-side high breakdown voltage N-type field effect transistor are individually described.
- a high-breakdown-voltage N-type field effect transistor and a low-side high-breakdown-voltage N-type field effect transistor may be mounted.
- the isolation region may be an isolation region by a trench isolation insulating film in addition to the insulating film by the LOCOS method.
- the present invention is effectively used for a semiconductor device provided with a high withstand voltage field effect transistor such as power supply control.
- SUB semiconductor substrate BRU isolation region, BRS isolation region, BRN isolation region, NW N-type well, ND N-type drain region, PW P-type well, GZ gate insulating film, G gate electrode, NS N-type source region, SS insulating film Spacer, NND N + type drain region, NNS N + type source region, BCR P + type impurity region, CPS contact plug, CPD contact plug, CPB contact plug, PSAC P + type contact injection region, DF interlayer insulating film, CHS contact hole, CHD contact Hole, CHB contact hole, MLS metal wiring, MLD metal wiring, MLB metal wiring, TNH field effect transistor, TNL field effect transistor, PM photoresist mask, PMS photoresist Mask.
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Abstract
Description
ここでは、ハイサイドの電界効果トランジスタを備えた半導体装置の第1の例について説明する。図2、図3、図4および図5に示すように、P型の半導体基板SUBにおける所定の領域に、ソース領域およびドレイン領域をそれぞれ形成するための素子形成領域を規定する分離領域BRU,BRSが形成されている。分離領域BRU,BRSは、たとえばLOCOS(LoCal Oxidation of Silicon)酸化膜等によって形成されている。
されている。
ここでは、ハイサイドの電界効果トランジスタを備えた半導体装置の第2の例について説明する。図21、図22、図23および図24に示すように、P型ウェルPWには、バックゲートコンタクト領域としてのP+型不純物領域BCRは、電流が流れる方向と交差(略直交)する方向(長手方向)に間隔を隔てて形成されている。そのP+型不純物領域BCRを平面的に取り囲むように、N+型ソース領域NNSが形成されている。平面的とはレイアウト的(2次元)にという意味である。N型ソース領域NSは、N+型ソース領域NNSの直下に位置する領域に形成されて、P+型不純物領域BCRの直下に位置する領域には形成されていない。なお、これ以外の構成については、図2、図3、図4および図5に示す半導体装置の構成と同様なので、同一部材には同一符号を付しその説明を繰り返さないこととする。
ここでは、ハイサイドの電界効果トランジスタを備えた半導体装置の第3の例について説明する。図25および図26に示すように、P型ウェルPWには、バックゲートコンタクト領域としてのP+型不純物領域BCRを取り囲むようにN+型ソース領域NNSが形成され、P+型不純物領域BCRとN+型ソース領域NNSとの間に分離領域BRNが形成されている。N型ソース領域NSはN+型ソース領域NNSの直下に位置する領域に形成されて、P+型不純物領域BCRの直下に位置する領域には形成されていない。なお、これ以外の構成については、図2、図3、図4および図5に示す半導体装置の構成と同様なので、同一部材には同一符号を付しその説明を繰り返さないこととする。
ここでは、ハイサイドの電界効果トランジスタを備えた半導体装置の第4の例について説明する。図30、図31、図32および図33に示すように、N型ソース領域NSは、N+型ソース領域NNSを側方と下方とから取り囲むように形成されている。さらに、そのN型ソース領域NSを貫通するように、N+型ソース領域NNSからP型ウェルPWに達する、突出部としてのP+型コンタクト注入領域PSACが形成されている。なお、これ以外の構成については、図2、図3、図4および図5に示す半導体装置の構成と同様なので、同一部材には同一符号を付しその説明を繰り返さないこととする。
ここでは、ローサイドの電界効果トランジスタを備えた半導体装置の第1の例について説明する。図40、図41、図42および図43に示すように、本実施の形態に係る半導体装置は、N型ウェルNW(図2等参照)が形成されていない点を除いて、図2、図3、図4および図5に示す半導体装置の構成と同様なので、同一部材には同一符号を付しその説明を繰り返さないこととする。
ここでは、ローサイドの電界効果トランジスタを備えた半導体装置の第2の例について説明する。図44、図45、図46および図47に示すように、本実施の形態に係る半導体装置は、N型ウェルNW(図1等参照)が形成されていない点を除いて、図21、図22、図23および図24に示す半導体装置の構成と同様なので、同一部材には同一符号を付しその説明を繰り返さないこととする。
ここでは、ローサイドの電界効果トランジスタを備えた半導体装置の第3の例について説明する。図48および図49に示すように、本実施の形態に係る半導体装置は、N型ウェルNW(図1等参照)が形成されていない点を除いて、図25および図26に示す半導体装置の構成と同様なので、同一部材には同一符号を付しその説明を繰り返さないこととする。
ここでは、ローサイドの電界効果トランジスタを備えた半導体装置の第4の例について説明する。図50、図51、図52および図53に示すように、本実施の形態に係る半導体装置は、N型ウェルNW(図2等参照)が形成されていない点を除いて、図30、図31、図32および図33に示す半導体装置の構成と同様なので、同一部材には同一符号を付しその説明を繰り返さないこととする。
Claims (14)
- 主表面を有する第1導電型の半導体基板と、
前記半導体基板の前記主表面から所定の深さにわたり形成され、第1不純物濃度を有する第1導電型の第1不純物領域と、
前記第1不純物領域によって側方と下方とから取り囲まれるように前記第1不純物領域の表面から所定の深さにわたり形成され、第2不純物濃度を有する第2導電型の第2不純物領域と、
前記第2不純物領域によって側方と下方とから取り囲まれるように前記第2不純物領域の表面から所定の深さにわたり形成され、前記第2不純物濃度よりも高い第3不純物濃度を有する第2導電型の第3不純物領域と、
前記第1不純物領域によって側方と下方とから取り囲まれるように前記第1不純物領域の表面から所定の深さにわたり形成されて前記第1不純物領域に直接接し、前記第1不純物濃度よりも高い第4不純物濃度を有する第1導電型の第4不純物領域と、
前記第1不純物領域と距離を隔てて前記半導体基板の前記主表面から所定の深さにわたり形成された第2導電型の第5不純物領域と、
前記第2不純物領域と前記第5不純物領域によって挟まれた領域の上に形成された電極部と
を備え、
前記第4不純物領域は複数形成され、
複数の前記第4不純物領域は、前記電極部に所定の電圧を印加することによって前記第2不純物領域と前記第5不純物領域との間を流れる電流の方向と交差する方向に間隔を隔てて配置された、半導体装置。 - 前記第3不純物領域は複数形成され、
複数の前記第3不純物領域と複数の前記第4不純物領域とは、前記電流の方向と交差する方向に交互に配置され、
前記第2不純物領域は、前記第3不純物領域の直下の領域から前記第4不純物領域の側方の領域に延在するように形成された、請求項1記載の半導体装置。 - 前記第3不純物領域は、間隔を隔てて配置された前記第4不純物領域を平面的に取り囲む態様で形成された、請求項1記載の半導体装置。
- 前記第2不純物領域は、前記第4不純物領域を側方と下方とから取り囲むように形成され、
前記第4不純物領域は、前記第2不純物領域を貫通して前記第1不純物領域に達する第1導電型の突出部を含む、請求項1記載の半導体装置。 - 前記第1不純物領域および前記第5不純物領域を側方と下方とから取り囲むように、前記半導体基板の前記主表面から所定の深さにわたり形成された第2導電型の第6不純物領域を備えた、請求項1記載の半導体装置。
- 主表面を有する第1導電型の半導体基板と、
前記半導体基板の前記主表面から所定の深さにわたり形成され、第1不純物濃度を有する第1導電型の第1不純物領域と、
前記第1不純物領域によって側方と下方とから取り囲まれるように前記第1不純物領域の表面から所定の深さにわたり形成され、第2不純物濃度を有する第2導電型の第2不純物領域と、
前記第2不純物領域によって側方と下方とから取り囲まれるように前記第2不純物領域の表面から所定の深さにわたり形成されて前記第1不純物領域に直接接し、前記第2不純物濃度よりも高い第3不純物濃度を有する第2導電型の第3不純物領域と、
前記第1不純物領域によって側方と下方とから取り囲まれるように前記第1不純物領域の表面から所定の深さにわたり形成され、前記第1不純物濃度よりも高い第4不純物濃度を有する第1導電型の第4不純物領域と、
前記第3不純物領域と前記第4不純物領域との間に形成され、前記第3不純物領域と前記第4不純物領域とを電気的に分離する分離領域と、
前記第1不純物領域と距離を隔てて前記半導体基板の前記主表面から所定の深さにわたり形成された第2導電型の第5不純物領域と、
前記第2不純物領域と前記第5不純物領域によって挟まれた領域の上に形成された電極部と
を備えた、半導体装置。 - 前記第1不純物領域および前記第5不純物領域を側方と下方とから取り囲むように、前記半導体基板の前記主表面から所定の深さにわたり形成された第2導電型の第6不純物領域を備えた、請求項6記載の半導体装置。
- 主表面を有する第1導電型の半導体基板を用意する工程と、
前記半導体基板の前記主表面から所定の深さにわたり、第1不純物濃度を有する第1導電型の第1不純物領域を形成する工程と、
前記第1不純物領域によって側方と下方とから取り囲まれるように前記第1不純物領域の表面から所定の深さにわたり、第2不純物濃度を有する第2導電型の第2不純物領域を形成する工程と、
前記第2不純物領域によって側方と下方とから取り囲まれるように前記第2不純物領域の表面から所定の深さにわたり、前記第2不純物濃度よりも高い第3不純物濃度を有する第2導電型の第3不純物領域を形成する工程と、
前記第1不純物領域によって側方と下方とから取り囲まれるように前記第1不純物領域の表面から所定の深さにわたり、前記第1不純物濃度よりも高い第4不純物濃度を有し前記第1不純物領域に直接接する第1導電型の第4不純物領域を形成する工程と、
前記第1不純物領域と距離を隔てて前記半導体基板の前記主表面から所定の深さにわたり、第2導電型の第5不純物領域を形成する工程と、
前記第2不純物領域と前記第5不純物領域によって挟まれた領域の上に電極部を形成する工程と
を備え、
前記第2不純物領域を形成する工程では、所定の注入マスクを介して第2導電型の不純物を前記半導体基板の表面に対して斜めに注入することによって前記第2不純物領域を形成し、
前記第4不純物領域を形成する工程では、複数の前記第4不純物領域を、前記電極部に所定の電圧を印加することによって前記第1不純物領域と前記第5不純物領域との間を流れる電流の方向と交差する方向に間隔を隔てて形成する、半導体装置の製造方法。 - 前記第3不純物領域を形成する工程では、前記第3不純物領域は複数形成され、
前記第3不純物領域を形成する工程および前記第4不純物領域とを形成する工程では、複数の前記第3不純物領域と複数の前記第4不純物領域とは、前記電流の方向と交差する方向に交互に配置され、
前記第2不純物領域を形成する工程では、前記第2不純物領域は、前記第3不純物領域の直下の領域から前記第4不純物領域の側方の領域に延在するように形成された、請求項8記載の半導体装置の製造方法。 - 前記第3不純物領域を形成する工程では、前記第3不純物領域は、間隔を隔てて配置された前記第4不純物領域を平面的に取り囲む態様で形成された、請求項8記載の半導体装置の製造方法。
- 前記第2不純物領域を形成する工程では、前記第2不純物領域は、前記第4不純物領域を側方と下方とから取り囲むように形成され、前記第4不純物領域を形成する工程では、前記第2不純物領域を貫通して前記第1不純物領域に達する第1導電型の突出部を形成する工程を含む、請求項8記載の半導体装置の製造方法。
- 前記第1不純物領域および前記第5不純物領域を側方と下方とから取り囲むように前記半導体基板の前記主表面から所定の深さにわたり、第2導電型の第6不純物領域を形成する工程を備えた、請求項8記載の半導体装置の製造方法。
- 主表面を有する第1導電型の半導体基板を用意する工程と、
前記半導体基板の前記主表面から所定の深さにわたり、第1不純物濃度を有する第1導電型の第1不純物領域を形成する工程と、
前記第1不純物領域によって側方と下方とから取り囲まれるように前記第1不純物領域の表面から所定の深さにわたり、第2不純物濃度を有する第2導電型の第2不純物領域を形成する工程と、
前記第2不純物領域によって側方と下方とから取り囲まれるように前記第2不純物領域の表面から所定の深さにわたり、前記第2不純物濃度よりも高い第3不純物濃度を有する第2導電型の第3不純物領域を形成する工程と、
前記第1不純物領域によって側方と下方とから取り囲まれるように前記第1不純物領域の表面から所定の深さにわたり、前記第1不純物濃度よりも高い第4不純物濃度を有し前記第1不純物領域に直接接する第1導電型の第4不純物領域を形成する工程と、
前記第3不純物領域と前記第4不純物領域との間に、前記第3不純物領域と前記第4不純物領域とを電気的に分離する分離領域を形成する工程と、
前記第1不純物領域と距離を隔てて前記半導体基板の前記主表面から所定の深さにわたり、第2導電型の第5不純物領域を形成する工程と、
前記第2不純物領域と前記第5不純物領域によって挟まれた領域の上に電極部を形成する工程と
を備えた、半導体装置の製造方法。 - 前記第1不純物領域および前記第5不純物領域を側方と下方とから取り囲むように前記半導体基板の前記主表面から所定の深さにわたり、第2導電型の第6不純物領域を形成する工程を備えた、請求項13記載の半導体装置の製造方法。
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JP2018046165A (ja) * | 2016-09-14 | 2018-03-22 | 富士電機株式会社 | 半導体装置 |
JP2019117883A (ja) * | 2017-12-27 | 2019-07-18 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
WO2021182211A1 (ja) * | 2020-03-13 | 2021-09-16 | ローム株式会社 | 半導体装置およびその製造方法 |
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