CN102347306B - 具有凹洞板互连的半导体封装 - Google Patents

具有凹洞板互连的半导体封装 Download PDF

Info

Publication number
CN102347306B
CN102347306B CN201110354530.2A CN201110354530A CN102347306B CN 102347306 B CN102347306 B CN 102347306B CN 201110354530 A CN201110354530 A CN 201110354530A CN 102347306 B CN102347306 B CN 102347306B
Authority
CN
China
Prior art keywords
source
gate
lead
area
patterned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201110354530.2A
Other languages
English (en)
Other versions
CN102347306A (zh
Inventor
孙明
石磊
刘凯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alpha and Omega Semiconductor Cayman Ltd
Original Assignee
Alpha and Omega Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alpha and Omega Semiconductor Inc filed Critical Alpha and Omega Semiconductor Inc
Publication of CN102347306A publication Critical patent/CN102347306A/zh
Application granted granted Critical
Publication of CN102347306B publication Critical patent/CN102347306B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/3701—Shape
    • H01L2224/37011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/3701—Shape
    • H01L2224/37012—Cross-sectional shape
    • H01L2224/37013—Cross-sectional shape being non uniform along the connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4007—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/40247—Connecting the strap to a bond pad of the item
    • H01L2224/40249—Connecting the strap to a bond pad of the item the bond pad protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
    • H01L2224/4101—Structure
    • H01L2224/4103—Connectors having different sizes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/8434—Bonding interfaces of the connector
    • H01L2224/84345—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01055—Cesium [Cs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明公开了一种具有凹洞板互连的半导体封装。此封装包含有引线框架、半导体芯片、图案化源极板、半导体芯片漏极区域与封装材料，引线框架具有漏极引脚、源极引脚和栅极引脚，半导体芯片耦合到引线框架上，并具有若干金属化源极区域和一个金属化栅极区域，图案化源极板上形成有若干个凹洞，并用以使栅极引脚至半导体芯片的金属化栅极区域连接，半导体芯片漏极区域耦接于漏极引脚，而封装材料覆盖于至少一部分的半导体芯片、漏极引脚、源极引脚与栅极引脚。

Description

具有凹洞板互连的半导体封装
本案是分案申请
原案发明名称：具有凹洞板互联的半导体封装
原案国际申请号：PCT/US2008/005563
原案国际申请日：2008年4月30日
原案国家申请号：200880001385.6
原案进入中国日：2009年6月17日
技术领域
本发明涉及一种半导体封装，尤其涉及一种具有在功率半导体装置的源极、栅极金属化区域与引线框架的源极引脚与栅极引脚之间的凹洞板互连的半导体封装。
背景技术
半导体装置通常使用内连接板或键合线来连接引线框架的引脚。举例来说，美国专利公告第5,821,611号专利，公开了一种半导体装置，其包含具有尖端(tip)并形成岛状区域的第一引线，通过焊锡层固定在第一引线的岛状区域上，且具有若干电极凸块，电极凸块由该岛状区域向外突出的半导体芯片单元和与若干个额外引线，每一个额外引线都具有通过各自的焊锡沉积来电连接电极凸块的尖端，且额外引线至少包含第二引线和第三引线，这些引线利用熔炉加热与电极凸块构成合金，焊锡凸块在加热过程中可能会喷溅，而产生无法预期的形状。
美国专利公告第6,040,626号专利，公开了一种半导体封装，其在MOSFET上表面之间使用混合连接，包括低电阻平板部分来连接源极和键合线来连接栅极。然而，由于装置介电层在键合线处理过程中的损坏将可能导致在装置内的短路现象。
美国专利公告第6,249,041号专利，公开一种直接连接引线的半导体封装。半导体装置包含在顶表面或底表面具有接触区域的半导体芯片。第一引线组件是由半硬式(semi-rigid)导体材料薄板构成，且具有引线组件触点(contact)，附着在半导体芯片的其中一个接触区域上。第一引线组件还具有至少一个引线，由引线组件触点延伸并与之连接。第二引线组件也是由半硬式导体材料薄板构成，并具有附着在半导体芯片的另外一个接触区域上。且第二引线组件也具有至少一个引线，由引线组件触点延伸并与之连接。而封装材料(encapsulant)围绕半导体芯片、第一导体组件的引线组件触点与第二引线组件的引线组件触点。由于引线组件直接连接芯片，故半导体装置具有较低的电性阻抗、热阻抗。通过电性导体黏胶层来维持引线组件触点区域接触半导体芯片的引线触点区域。电性导体黏胶层可为银填充的环氧化物(silver-filled epoxy)、聚亚酰胺(polyimide)或是焊锡凸块。如果必须的话，黏胶层可以在烤炉(curing even)中烘烤固化，因此，黏胶层并不包含软焊锡或焊接锡膏(solder paste)。
美国专利公告第6,479,888号专利公开了另外一种直接连接引线的半导体封装。金氧半场效应晶体管包含若干个内引线，电连接到半导体小球(pellet)的表面电极，并在半导体小球的主表面上具有一个场效应晶体管。通过由凸块构成的栅极连接部分和源极连接部分使内引线机电连接到主表面。
使用图案化板或夹(clip)来内连接所遭遇的一般问题是图案化板或夹可能在焊锡回流过程中漂移，而产生未对准(misalignment)的内连接。在某些情况下，未对准导致源极、漏极触点区域的短路，因而降低整体组件的产量。另外，要控制所需要的焊锡体积来避免这样的问题也是非常困难的。
使用图案化板或是夹来内连接所遭遇的另外一个问题，是半导体装置的硅材料与图案化板或夹的金属材料之间热膨胀的错误匹配。随着图案化板或夹的接触面积变大，其因为错误匹配而承受的压力也随之增大，而经常导致芯片的破裂。为了降低压力，会采用面积较小的图案化板或夹。然而，较小的接触面积会导致较高的电阻。
因此，本技术领域需要一种半导体封装，其包含有功率半导体装置，并通过图案化板来连接引线框架的源极与栅极引线框架接触区域，以克服现有技术中存在的问题。同时，也需要一种图案化内连接板，其不会在焊锡回流过程中漂移，来确保夹板位置、定点的准确性。并且，也需要一种半导体封装，具有金属化区域装置来限制焊锡在焊接过程中的流动；本领域也需要一种通过镍金合金构成的金属化区域；本领域也需要一种半导体封装制程，可增加生产率并提供简易的组件制程控制。同时，本领域亦需要一种半导体封装方法，可以提供设置在功率半导体装置上的图案化板的软附着制程(softattachment process)。本领域也需要一种具有裸露的源极板的半导体封装。本领域也需要一种降低的电性阻抗的半导体封装。本领域更进一步需要一种具有改善散热效果特性的半导体封装；本领域还需要一种具有改善的机械性能的半导体封装。
发明内容
本发明通过提供一种半导体器件封装，克服了现有技术存在的限制，该半导体器件封装在引线框架的源极、栅极区域和功率半导体功率器件的源极、栅极金属化区域之间具有平板连接。平板连接具有数个对应于源极、栅极金属化区域的凹洞。一部分的源极平板外露，以改善散热效果。
根据本发明的另外一个目的，本发明所公开的具内凹板内连接的半导体封装，包含引线框架、半导体芯片、图案化源极板、图案化栅极板、半导体芯片漏极区域以及封装材料(encapsulant)。引线框架具有漏极引脚、源极引脚与栅极引脚，半导体芯片耦合到引线框架，并具有若干个金属化源极区域与一个金属化栅极区域；图案化源极板上形成有若干个凹洞，用以使源极引脚与半导体芯片的金属化源极区域连接，其中，该些凹洞是被定位用以接触金属化源极区域；图案化栅极板上形成有一个凹洞，用以使栅极引脚与半导体芯片的金属化栅极区域连接，其中此些凹洞是被定位用以接触金属化栅极区域。半导体芯片漏极区域耦合到漏极引脚，封装材料至少覆盖半导体芯片、漏极引脚、源极引脚和栅极引脚的一部分。
根据本发明所提出的另一目的，半导体封装包含有引线框架、半导体芯片、图案化源极板、图案化栅极板、半导体漏极区域以及封装材料(encapsulant)。引线框架具有漏极引脚、源极引脚与栅极引脚，半导体芯片耦合到引线框架，并具有若干镍金金属化源极区域与一个镍金金属化栅极区域；图案化源极板上形成有若干个凹洞，以对应的关系使源极引脚与半导体芯片的金属化源极区域连接，且图案化源极板被焊接到半导体芯片金属化源极区域；图案化栅极板上形成有一个凹洞，以对应的关系使栅极引脚与半导体芯片的金属化栅极区域连接，且图案化栅极板被焊接在半导体芯片金属化栅极区域。半导体芯片漏极区域耦合到漏极引脚，封装材料至少覆盖半导体芯片、漏极引脚、源极引脚和栅极引脚的一部分。
以上概要的，非常粗略的描述了本发明的重要特征，为了使得随后对本发明的具体描述能够更好的理解，也为了使本发明对此领域的贡献更加明确。当然，本发明额外的特征将在下面实施方式中描述，且将形成附属权利要求的主题。
在这点上，在详细描述本发明的至少一个实施例之前，应该理解本发明在应用中并不局限于下列描述或附图所呈现的设计的细节和组件的排列。本发明可有其他的实施例且可以各种方式实施。而且，说明书连同摘要中所使用的语法、措辞或是技术用语，其目的仅仅在于描述，而不应该视为对本发明范围的限制。
因此，本技术领域中，熟悉该项技术的技术人员都可以根据本发明公开所基于的思路来作为以其它种方式、系统来实现本发明的数个目的的基础。因此，申请专利范围也包含了所有根据其技术精神、范围所衍生的等效方法、系统。
附图说明
图1是本发明半导体封装的示意图；
图2是本发明半导体封装根据图1沿着剖面线2-2的剖面示意图；
图3是本发明半导体封装根据图1沿着剖面线3-3的剖面示意图；
图3A是根据本发明的半导体封装设置在金属化栅极区域上的图案化栅极板的示意图；
图3B是本发明的半导体封装的栅极锁路(lock)的示意图；图3C是本发明半导体封装根据图1所显示金属化栅极区域的另一实施例的示意图；
图4是本发明的半导体封装根据图1的部分剖面示意图；图5是本发明半导体封装根据图1的另一实施例的部分剖面示意图；
图6是本发明半导体封装的另一实施例的示意图；
图7是本发明半导体封装根据图6沿着剖面线A-A的剖面示意图；
图8是本发明半导体封装根据图6沿着剖面线B-B的剖面示意图；
图9是本发明半导体封装根据图6的部分剖面示意图；
图10是本发明半导体封装的另一实施例的示意图；
图11是本发明半导体封装根据图10沿着剖面线A-A的剖面示意图；
图12是本发明半导体封装根据图10沿着剖面线B-B的剖面示意图；
图13是本发明具有凹洞板连接的半导体封装的实施例的示意图；
图14是本发明半导体封装根据图13的凹洞源极板的剖面示意图；
图15是本发明半导体封装根据图13的凹洞栅极板的剖面示意图；
图16是本发明半导体封装的半导体芯片的示意图；
图17是本发明具有凹洞板连接的半导体封装的另一实施例的示意图；
图18是本发明半导体封装根据图17的凹洞源极板的剖面示意图；以及
图19是本发明半导体封装根据图17的凹洞栅极板的剖面示意图。
具体实施方式
以下详细说明是本发明的最佳实施例。以下说明并非用以限制本发明的专利申请范围，仅为配合附图说明本发明的一般原则，因而，本发明的保护范围由权利要求来限定。
本发明提供一种半导体器件封装，该封装具有在引线框架的源极、漏极接触区域与功率半导体功率器件的金属化源极、漏极区域之间的平板连接。金属化源极、栅极区域最好是具有镍金电镀或喷涂的表面。金属化源极、栅极区域提供平板连接的较佳的结合，并且降低因为介电层在线的键合(wirebonding)过程中损坏所导致的过度键合(overbonding)而引发的短路现象。金属化源极、栅极区域更进一步排除需要使用焊锡凸块(solder bump)或是环氧化物黏胶层来作为软焊锡(soft solder)或是焊接锡膏(solder paste)来连接平板至金属化源极、栅极区域的情况。
根据本发明的第一方面且参考图1至图5所示，半导体封装100包含有引线框架105，引线框架105具有漏极接触部分107、源极接触部分110和栅极接触部分115。功率半导体芯片120具有金属化漏极区域(图中未显示)，并通过焊锡回流耦接到漏极接触部分107。
半导体源极、栅极金属化区域可以通过电镀(plating)或是喷涂(sputtering)镍金合金构成。如图3A所示，栅极金属化区域160可以是圆形(circular)配置。根据本发明公开，圆形金属化区域160有助于限制软焊锡与锡膏的流动，而能在焊锡回流过程中，定义圆形金属化区域160，因此降低不理想的形状或是短路的发生率。
图案化源极板120具有一个表面外露部分127以及一个内部部分130。内部部分130耦接到源极接触部分110。外露部分127则露在封装材料(encapsulant)135外面；图案化源极板125可通过使用软焊锡或锡膏而回流焊接到金属化源极区域。金属化源极区域可覆盖半导体芯片120的顶面的大部分，来增进散热效果并降低电阻系数和电感系数。
图案化栅极板137可将金属化栅极区域160连接到引线框架栅极接触区域115。图案化栅极板137包含位于其端部167的孔洞165。并且可以通过在回流焊接过程中形成的锁路球体155来提供图案化栅极板137(图3B所示)的机械稳固性。本发明的一个方面，软焊锡设置在孔洞165内，且允许在焊锡回流过程中，穿过孔洞165而流到金属化栅极区域160中。金属化栅极区域160提供了焊锡的键合表面，而能限制焊锡在圆形区域的流动。
参考图3C，是金属化栅极区域170的另一实施例，其包含有十字形区域。
根据本发明的另一方面，如图6～9所示，半导体封装600包含引线框架605，该引线框架605具有漏极接触部分607、源极接触部分610以与栅极接触部分615。功率半导体芯片620具有金属化漏极区域(图中未显示)，并通过回流焊锡耦接到漏极接触部分607。
半导体源极、栅极金属化区域可通过电镀或喷涂镍金合金构成。图案化源极板625包含有外露部分627与内部部分630。外露部分627外露在封装材料635外面，图案化源极板625通过软焊锡与锡膏回流焊接而耦接到金属化源极区域。
图案化栅极板637将金属化栅极区域640连接到引线框架栅极接触区域。图案化栅极板637也可通过焊锡回流而连接到金属化栅极区域640，而可提供图案化栅极板637的机械稳固性。
在本发明的另外一方面，如图10～12所示，半导体封装1000包含有引线框架1005，该引线框架1005具有漏极接触部分1007、源极接触部分1010以与栅极接触部分1015。功率半导体芯片1020具有金属化漏极区域(图中未显示)，并通过回流焊锡耦接到漏极接触部分1007。
半导体源极、栅极金属化区域可通过电镀或喷涂镍金合金构成。图案化源极板1025包含外露部分1027与内部部分1030，外露部分1027外露在封装材料1035外面。图案化源极板1025通过使用软焊锡或锡膏回流焊接而耦接到金属化源极区域。
图案化栅极板1037将金属化栅极区域1040连接到引线框架栅极接触区域。该图案化栅极板1037包含勾部(hook portion)1039来连接金属化栅极区域1040。图案化栅极板1037通过焊锡回流而连接到金属化栅极区域1040，以提供图案化栅极板1037的机械稳固性。
本发明有利地采用镍金器件图案化源极、漏极和栅极金属化区域。镍金合金使得图案化源极板与图案化栅极板之间的连结关系更佳，同时简化源极、栅极与漏极金属化在单一镍金合金制程中完成，从而增加了制程的生产率。
镍金制程也在金属区域提供了镍金属层，并通过金金属层来保护镍金属层。因为镍金属不会扩散到铝金属区域中，所以包含有镍金的内金属层可以提供高密度层来使图案化源极、栅极连接易于焊接。
根据本发明的另外一方面，参考图13、图14、图15与图16，源极板1300包含若干个形成在其上的凹洞1310。凹洞1310是一相对于源极板1300的上表面1320的凹面，且具有底表面1315在它的底部表面1330上延伸。栅极板1350包含有凹洞1360，凹洞1360是一相对于栅极板1350的上表面1370凹面，并且包含具有开口1367的穿孔1365，在栅极板1350的底表面1380上水平延伸。
源极板凹洞1310与栅极板凹洞1360在源极板1300与栅极板1360上定位且冲压(stamped or punched)成型，因此可以在焊锡回流过程中，使半导体芯片1600的源极金属化区域1620与栅极金属化区域1630对位。在此可以发现，因为与众不同的数个源极板1300的凹洞1310接触于源极金属化区域1630，故源极板1300不会漂移。进一步来说，金属化区域有利的将焊锡回流过程中软焊锡与锡膏的流动限制在金属化区域中，因此降低不理想的形状或是短路现象的发生率。穿孔1367、栅极凹洞1360允许在焊锡回流过程中锁路锡球的形成，以提高栅极板1350的机械稳固性。
本发明的另外一方面，参考图17、图18和图19，源极板1700包含有若干个形成在其上的凹洞1710。凹洞1710是一相对于源极板1700的上表面1715凹面，且包含一具有开口1725的穿孔1720，形成在源极板1700的底表面1730的水平方向上。栅极板1750包含有凹洞1760，凹洞1760是一为相对于栅极板1750的上表面1755的凹面，还包含一具有开口1775的穿孔1770，形成在栅极板1750的底表面1780的水平方向上。
如图13～16所示的实施例，源极板凹洞1710与栅极板凹洞1760在源极板1700与栅极板1750上定位且冲压成型，因此可在焊锡回流过程中，使半导体芯片1600的源极金属化区域1620与栅极金属化区域1630对位。源极板1700的凹洞1710的穿孔1720、栅极板1750的凹洞1760的穿孔1770允许在焊锡回流过程中形成锁路锡球，以分别提高栅极板1700与栅极板1750的机械稳固性。软焊锡设置在源极凹洞1710和栅极凹洞1760内，且可允许在焊锡回流过程中，分别穿过穿孔1720、1770而分别流至金属化源极区域1620和金属化栅极区域1630。因此，金属化源极区域1620、金属化栅极区域1630提供了焊锡的键合表面，而限制焊锡在圆形区域中的流动。
本发明有利地提供了具有凹洞设置在相应的源极金属化区域和栅极金属化区域的图案化源极板连接和图案化栅极板连接。凹洞源极板和凹洞栅极板确保源极板和栅极板在焊锡回流过程中不会漂移，因此确保夹紧固定的位置的精确性。
当然，应该理解，前述本发明的优选实施例和其所做的润色或修饰都未超出本发明的精神和范围。本发明的保护范围由权利要求限定。

Claims (9)

1.一种半导体封装，其特征在于，包含： 
一引线框架，所述的引线框架具有漏极引脚、源极引脚和栅极引脚； 
一半导体芯片，所述的半导体芯片耦合到该引线框架上，该半导体芯片具有若干金属化源极区域和一金属化栅极区域； 
一图案化源极板，所述的图案化源极板上形成有若干源极凹洞，用以将源极引脚耦合至半导体芯片的金属化源极区域，该些源极凹洞设置在用以和金属化源极区域连接的位置； 
所述的若干源极凹洞各包含有一源极穿孔，通过该源极穿孔使得图案化源极板焊接到金属化源极区域； 
一半导体芯片漏极区域，所述的半导体芯片漏极区域耦合至漏极引脚；以及 
一封装材料，所述的封装材料至少覆盖半导体芯片和该漏极引脚、源极引脚和栅极引脚的一部分；
所述图案化源极板的源极凹洞是相对于源极板的上表面的凹面，源极凹洞还具有底表面，该底表面延伸超出图案化源极板的底部表面。 
2.如权利要求1所述的半导体封装，其特征在于，还包含一图案化栅极板，所述的图案化栅极板上形成有若干栅极凹洞，用以将栅极引脚耦合到半导体芯片的金属化栅极区域，该些栅极凹洞设置在用以和金属化栅极区域连接的位置。 
3.如权利要求1所述的半导体封装，其特征在于，所述的金属化源极区域和金属化栅极区域包含有若干被钝化区域隔离的圆形金属化区域。 
4.如权利要求2所述的半导体封装，其特征在于，所述的若干栅极凹洞各包含有一栅极穿孔，通过该栅极穿孔使得图案化栅极板焊接到金属化栅极区域。 
5.如权利要求4所述的半导体封装，其特征在于，焊接时使用的焊锡在该图案化源极板与该图案化栅极板的顶部区域形成一锁路。 
6.如权利要求1所述的半导体封装，其特征在于，所述的金属化源极区域和金属化栅极区域包含一上镍金层。 
7.如权利要求1所述的半导体封装，其特征在于，所述的漏极区域包含有一金属化漏极区域。 
8.如权利要求7所述的半导体封装，其特征在于，所述的金属化漏极区域包含一上镍金层。 
9.如权利要求1所述的半导体封装，其特征在于，所述的漏极引脚的底部部分是通过封装材料暴露在外的。 
CN201110354530.2A 2007-04-30 2008-04-30 具有凹洞板互连的半导体封装 Active CN102347306B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/799,467 2007-04-30
US11/799,467 US7683464B2 (en) 2005-09-13 2007-04-30 Semiconductor package having dimpled plate interconnections

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN2008800013856A Division CN101720504B (zh) 2007-04-30 2008-04-30 具有凹洞板互联的半导体封装

Publications (2)

Publication Number Publication Date
CN102347306A CN102347306A (zh) 2012-02-08
CN102347306B true CN102347306B (zh) 2014-07-02

Family

ID=39944391

Family Applications (2)

Application Number Title Priority Date Filing Date
CN2008800013856A Active CN101720504B (zh) 2007-04-30 2008-04-30 具有凹洞板互联的半导体封装
CN201110354530.2A Active CN102347306B (zh) 2007-04-30 2008-04-30 具有凹洞板互连的半导体封装

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN2008800013856A Active CN101720504B (zh) 2007-04-30 2008-04-30 具有凹洞板互联的半导体封装

Country Status (4)

Country Link
US (2) US7683464B2 (zh)
CN (2) CN101720504B (zh)
TW (1) TWI378543B (zh)
WO (1) WO2008137001A2 (zh)

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7683464B2 (en) 2005-09-13 2010-03-23 Alpha And Omega Semiconductor Incorporated Semiconductor package having dimpled plate interconnections
US7622796B2 (en) * 2005-09-13 2009-11-24 Alpha And Omega Semiconductor Limited Semiconductor package having a bridged plate interconnection
US7804131B2 (en) * 2006-04-28 2010-09-28 International Rectifier Corporation Multi-chip module
US7859089B2 (en) * 2006-05-04 2010-12-28 International Rectifier Corporation Copper straps
US20090057869A1 (en) * 2007-08-31 2009-03-05 Alpha & Omega Semiconductor, Ltd. Co-packaged high-side and low-side nmosfets for efficient dc-dc power conversion
TWI456707B (zh) * 2008-01-28 2014-10-11 Renesas Electronics Corp 半導體裝置及其製造方法
US20090212405A1 (en) * 2008-02-26 2009-08-27 Yong Liu Stacked die molded leadless package
US8680658B2 (en) * 2008-05-30 2014-03-25 Alpha And Omega Semiconductor Incorporated Conductive clip for semiconductor device package
US8373257B2 (en) * 2008-09-25 2013-02-12 Alpha & Omega Semiconductor Incorporated Top exposed clip with window array
US20100164078A1 (en) * 2008-12-31 2010-07-01 Ruben Madrid Package assembly for semiconductor devices
US8222088B2 (en) * 2009-09-21 2012-07-17 Alpha And Omega Semiconductor Incorporated Semiconductor package with adhesive material pre-printed on the lead frame and chip, and its manufacturing method
TWI427752B (zh) * 2009-09-25 2014-02-21 Alpha & Omega Semiconductor 在引線框架和晶圓上印刷粘接材料的半導體封裝及其製造方法
TWI418005B (zh) * 2009-10-16 2013-12-01 Powertech Technology Inc 非對稱式導線架之多晶片堆疊封裝結構
JP5473733B2 (ja) * 2010-04-02 2014-04-16 株式会社日立製作所 パワー半導体モジュール
CN103314437B (zh) * 2011-03-24 2016-03-30 三菱电机株式会社 功率半导体模块及电源单元装置
EP2720263A4 (en) * 2011-06-09 2015-04-22 Mitsubishi Electric Corp SEMICONDUCTOR COMPONENT
JP5796520B2 (ja) * 2012-03-16 2015-10-21 株式会社豊田自動織機 半導体装置
JP2013197365A (ja) * 2012-03-21 2013-09-30 Toshiba Corp 半導体装置
DE102012216280A1 (de) 2012-09-13 2014-04-10 Robert Bosch Gmbh Kontaktbrücke und Anordnung mit Bauelement, Leiterstrukturträger und Kontaktbrücke
JP5943795B2 (ja) * 2012-09-26 2016-07-05 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
KR102071078B1 (ko) * 2012-12-06 2020-01-30 매그나칩 반도체 유한회사 멀티 칩 패키지
JP2015056638A (ja) * 2013-09-13 2015-03-23 株式会社東芝 半導体装置およびその製造方法
JP6238121B2 (ja) * 2013-10-01 2017-11-29 ローム株式会社 半導体装置
JP2015142077A (ja) * 2014-01-30 2015-08-03 株式会社東芝 半導体装置
JP2015142072A (ja) * 2014-01-30 2015-08-03 株式会社東芝 半導体装置
JP2015144217A (ja) * 2014-01-31 2015-08-06 株式会社東芝 コネクタフレーム及び半導体装置
EP2930747A1 (en) * 2014-04-07 2015-10-14 Nxp B.V. Lead for connection to a semiconductor device
US9640465B2 (en) 2015-06-03 2017-05-02 Infineon Technologies Ag Semiconductor device including a clip
US10163762B2 (en) * 2015-06-10 2018-12-25 Vishay General Semiconductor Llc Lead frame with conductive clip for mounting a semiconductor die with reduced clip shifting
US9941193B1 (en) * 2016-09-30 2018-04-10 Infineon Technologies Americas Corp. Semiconductor device package having solder-mounted conductive clip on leadframe
JP6827776B2 (ja) * 2016-11-15 2021-02-10 ローム株式会社 半導体デバイス
US10825757B2 (en) * 2016-12-19 2020-11-03 Nexperia B.V. Semiconductor device and method with clip arrangement in IC package
CN108807316B (zh) * 2017-08-14 2020-07-10 苏州捷芯威半导体有限公司 半导体封装结构及半导体器件
CN109757119B (zh) * 2017-09-05 2022-12-23 新电元工业株式会社 半导体装置
WO2019049214A1 (ja) * 2017-09-05 2019-03-14 新電元工業株式会社 半導体装置
JP6808849B2 (ja) * 2017-10-26 2021-01-06 新電元工業株式会社 半導体装置
US11088046B2 (en) * 2018-06-25 2021-08-10 Semiconductor Components Industries, Llc Semiconductor device package with clip interconnect and dual side cooling
EP3671829B1 (en) 2018-12-17 2023-09-27 Nexperia B.V. Leadframe assembly for a semiconductor device
CN110164831A (zh) * 2019-05-31 2019-08-23 无锡电基集成科技有限公司 利于焊接的大电流半导体功率器件及其制造方法
CN112259516A (zh) * 2019-07-22 2021-01-22 无锡华润华晶微电子有限公司 半导体封装结构
CN110364503B (zh) * 2019-07-25 2020-11-27 珠海格力电器股份有限公司 一种新型无引线贴片封装结构及其制造方法
CN112530894A (zh) * 2020-11-25 2021-03-19 通富微电子股份有限公司技术研发分公司 功率模块及具有其的电子设备、键合金属片的制备方法
EP4290571A1 (en) * 2022-06-10 2023-12-13 Nexperia B.V. Electronic package with heatsink and manufacturing method therefor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6040626A (en) * 1998-09-25 2000-03-21 International Rectifier Corp. Semiconductor package
CN1511346A (zh) * 2001-04-18 2004-07-07 ��ʽ���綫֥ 半导体器件及其制造方法
US6849930B2 (en) * 2000-08-31 2005-02-01 Nec Corporation Semiconductor device with uneven metal plate to improve adhesion to molding compound

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2003003A (en) * 1931-11-11 1935-05-28 Westinghouse Electric & Mfg Co Dishwasher
US3737738A (en) 1970-09-22 1973-06-05 Gen Electric Continuous strip processing of semiconductor devices and novel bridge construction
US3735017A (en) 1971-04-12 1973-05-22 Amp Inc Lead frames and method of making same
US3842189A (en) 1973-01-08 1974-10-15 Rca Corp Contact array and method of making the same
US4083063A (en) 1973-10-09 1978-04-04 General Electric Company Gate turnoff thyristor with a pilot scr
US4063272A (en) 1975-11-26 1977-12-13 General Electric Company Semiconductor device and method of manufacture thereof
US4418470A (en) 1981-10-21 1983-12-06 General Electric Company Method for fabricating silicon-on-sapphire monolithic microwave integrated circuits
US4996582A (en) 1988-09-14 1991-02-26 Mitsubishi Denki Kabushiki Kaisha Field effect transistor for microstrip mounting and microstrip-mounted transistor assembly
US5399902A (en) 1993-03-04 1995-03-21 International Business Machines Corporation Semiconductor chip packaging structure including a ground plane
JPH08279562A (ja) 1994-07-20 1996-10-22 Mitsubishi Electric Corp 半導体装置、及びその製造方法
KR100206555B1 (ko) 1995-12-30 1999-07-01 윤종용 전력용 트랜지스터
DE19734509C2 (de) 1997-08-08 2002-11-07 Infineon Technologies Ag Leistungstransistorzelle
DE19735379B4 (de) 1997-08-14 2008-06-05 Perkinelmer Optoelectronics Gmbh Sensorsystem und Herstellungsverfahren
JP3147048B2 (ja) 1997-09-12 2001-03-19 日本電気株式会社 半導体装置
US6249041B1 (en) 1998-06-02 2001-06-19 Siliconix Incorporated IC chip package with directly connected leads
US6287126B1 (en) 1999-06-25 2001-09-11 International Business Machines Corporation Mechanical attachment means used as electrical connection
US6292140B1 (en) 1999-11-03 2001-09-18 Hypres, Inc. Antenna for millimeter-wave imaging and bolometer employing the antenna
US6136702A (en) 1999-11-29 2000-10-24 Lucent Technologies Inc. Thin film transistors
JP3865573B2 (ja) * 2000-02-29 2007-01-10 アンリツ株式会社 誘電体漏れ波アンテナ
CN1181546C (zh) 2000-03-28 2004-12-22 皇家菲利浦电子有限公司 带可编程存储器单元的集成电路
US6724067B2 (en) 2001-04-13 2004-04-20 Anadigics, Inc. Low stress thermal and electrical interconnects for heterojunction bipolar transistors
JP3819840B2 (ja) 2002-07-17 2006-09-13 大日本スクリーン製造株式会社 メッキ装置およびメッキ方法
US8089097B2 (en) 2002-12-27 2012-01-03 Momentive Performance Materials Inc. Homoepitaxial gallium-nitride-based electronic devices and method for producing same
US6881074B1 (en) 2003-09-29 2005-04-19 Cookson Electronics, Inc. Electrical circuit assembly with micro-socket
US7633140B2 (en) 2003-12-09 2009-12-15 Alpha And Omega Semiconductor Incorporated Inverted J-lead for power devices
US7148149B2 (en) * 2003-12-24 2006-12-12 Matsushita Electric Industrial Co., Ltd. Method for fabricating nitride-based compound semiconductor element
JP4058007B2 (ja) 2004-03-03 2008-03-05 株式会社東芝 半導体装置
US7320898B2 (en) * 2004-06-17 2008-01-22 Matsushita Electric Industrial Co., Ltd. Semiconductor laser device and method for fabricating the same
US20060012055A1 (en) 2004-07-15 2006-01-19 Foong Chee S Semiconductor package including rivet for bonding of lead posts
US7439595B2 (en) 2004-11-30 2008-10-21 Matsushita Electric Industrial Co., Ltd. Field effect transistor having vertical channel structure
EP1739736A1 (en) 2005-06-30 2007-01-03 Interuniversitair Microelektronica Centrum ( Imec) Method of manufacturing a semiconductor device
US20070057368A1 (en) 2005-09-13 2007-03-15 Yueh-Se Ho Semiconductor package having plate interconnections
US7683464B2 (en) 2005-09-13 2010-03-23 Alpha And Omega Semiconductor Incorporated Semiconductor package having dimpled plate interconnections
US20070075406A1 (en) * 2005-09-30 2007-04-05 Yueh-Se Ho Wafer-level method for metallizing source, gate and drain contact areas of semiconductor die
KR100756038B1 (ko) 2005-10-26 2007-09-07 삼성전자주식회사 멀티루프형 트랜스포머
US7285849B2 (en) 2005-11-18 2007-10-23 Fairchild Semiconductor Corporation Semiconductor die package using leadframe and clip and method of manufacturing
US7495323B2 (en) 2006-08-30 2009-02-24 Semiconductor Components Industries, L.L.C. Semiconductor package structure having multiple heat dissipation paths and method of manufacture

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6040626A (en) * 1998-09-25 2000-03-21 International Rectifier Corp. Semiconductor package
US6849930B2 (en) * 2000-08-31 2005-02-01 Nec Corporation Semiconductor device with uneven metal plate to improve adhesion to molding compound
CN1511346A (zh) * 2001-04-18 2004-07-07 ��ʽ���綫֥ 半导体器件及其制造方法

Also Published As

Publication number Publication date
US8053874B2 (en) 2011-11-08
TW200843062A (en) 2008-11-01
TWI378543B (en) 2012-12-01
US20070290336A1 (en) 2007-12-20
WO2008137001A3 (en) 2010-03-11
CN101720504B (zh) 2012-01-04
CN101720504A (zh) 2010-06-02
CN102347306A (zh) 2012-02-08
WO2008137001A2 (en) 2008-11-13
US20090218673A1 (en) 2009-09-03
US7683464B2 (en) 2010-03-23

Similar Documents

Publication Publication Date Title
CN102347306B (zh) 具有凹洞板互连的半导体封装
CN211238167U (zh) 半导体器件
CN101399245B (zh) 具有桥式互连平板的半导体封装结构
CN101834166B (zh) 具有支架触点以及管芯附垫的无引脚集成电路封装
US6492252B1 (en) Method of connecting a bumped conductive trace to a semiconductor chip
CN100590860C (zh) 具有薄板内连接的半导体封装
CN100409443C (zh) 含侧向电气连接的半导体管芯的半导体管芯封装
CN100444371C (zh) 功率半导体封装
KR20170086828A (ko) 메탈범프를 이용한 클립 본딩 반도체 칩 패키지
JP2005191240A (ja) 半導体装置及びその製造方法
CN102629598B (zh) 具有金属化源极、栅极与漏极接触区域的半导体芯片的封装
KR20150089609A (ko) 전력반도체 모듈
TWI227051B (en) Exposed pad module integrated a passive device therein
CN108496249A (zh) 半导体装置
CN101383294A (zh) 制造一种直接芯片连接装置及结构的方法
CN201435388Y (zh) 一种用于mosfet封装的引线框架
CN216413056U (zh) 一种大电流地与散热片一体化的芯片陶瓷封装结构
CN102339762B (zh) 无载具的半导体封装件及其制造方法
CN105206594B (zh) 单面蚀刻水滴凸点式封装结构及其工艺方法
CN105355567B (zh) 双面蚀刻水滴凸点式封装结构及其工艺方法
CN105226040B (zh) 一种硅基模块的封装结构及其封装方法
CN106711100A (zh) 一种半导体封装结构及加工方法
CN101894811A (zh) 具有散热块外露的四面扁平封装结构、电子组装体与制程
CN111834238A (zh) 一种采用凸块与倒装的大功率半导体器件封装方法
CN213583808U (zh) 一种高温漏电特小的肖特基二极管

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20200715

Address after: Ontario, Canada

Patentee after: World semiconductor International L.P.

Address before: 475 oakmead Park Road, Sunnyvale, California, USA

Patentee before: Alpha and Omega Semiconductor Inc.