JP4058007B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4058007B2 JP4058007B2 JP2004058948A JP2004058948A JP4058007B2 JP 4058007 B2 JP4058007 B2 JP 4058007B2 JP 2004058948 A JP2004058948 A JP 2004058948A JP 2004058948 A JP2004058948 A JP 2004058948A JP 4058007 B2 JP4058007 B2 JP 4058007B2
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- Prior art keywords
- electrode pad
- semiconductor
- semiconductor device
- gate electrode
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 130
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 239000000945 filler Substances 0.000 claims description 4
- 230000005484 gravity Effects 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 26
- 238000004519 manufacturing process Methods 0.000 description 16
- 238000010586 diagram Methods 0.000 description 13
- 239000011347 resin Substances 0.000 description 12
- 229920005989 resin Polymers 0.000 description 12
- 230000015556 catabolic process Effects 0.000 description 9
- 230000000052 comparative effect Effects 0.000 description 9
- 238000000034 method Methods 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 5
- 238000007789 sealing Methods 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- HBBGRARXTFLTSG-UHFFFAOYSA-N Lithium ion Chemical compound [Li+] HBBGRARXTFLTSG-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910001416 lithium ion Inorganic materials 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005491 wire drawing Methods 0.000 description 1
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Description
すなわち、DTMOS10は、n++型シリコン基板11の上にn型ピラー領域12とp型ピラー領域14とが並列して設けられた構造を有する。そして、これらn型ピラー領域に隣接して、絶縁体により充填されたトレンチ16が設けられている。トレンチ16の深さDは、例えば、60マイクロメータ程度である。また、一対のトレンチ16により挟まれたn型ピラー領域12及びp型ピラー領域14の幅Wは、例えば10マイクロメータ程度である。
DTMOS10のチップ一辺のサイズLは、例えば、5ミリメートル程度である。トレンチ16を、図25に例示した如く互いに平行に隣接して設けることにより、素子の電流密度を上げて大電流のスイッチングが可能となる。
一方、素子の耐圧は、n型ピラー領域12とp型ピラー領域14との間のpn接合から横方向に伸びる空乏層と、絶縁体を埋め込んだトレンチ16と、によって維持できる。つまり、絶縁体を埋め込んだトレンチ16を設けることにより、n型ピラー領域12とp型ピラー領域14の幅を狭くして、これらを完全に空乏化させることができる。その結果として、空乏化領域と絶縁領域とで素子の電流経路を完全に遮断し、高い耐圧を実現できる。つまり、図24に例示したようなDTMOSは、オン抵抗の低下と耐圧の上昇を両立できるパワーMOSFETである。
第1及び第2の主面を有する半導体基板と、
前記半導体基板の前記第1の主面上に形成された半導体層と、
前記半導体層に互いに平行に第1の方向に延在してなる複数のトレンチと、
前記複数のトレンチを充填する充填体と、
前記半導体層の上方に設けられ、第1主電極に電気的に接続された第1電極パッドと、
前記第2の主面上に設けられた第2主電極と、
前記半導体層の上方に設けられ、前記第1主電極と前記第2主電極との間の導通を制御するゲート電極に接続されたゲート電極パッドと、
を有する半導体素子と、
前記第1電極パッドと前記ゲート電極パッドの少なくともいずれかに接続され、その引き出し方向が前記第1の方向と略平行な導電部材と、
を備えたことを特徴とする半導体装置が提供される。
第1及び第2の主面を有する半導体基板と、
前記半導体基板の前記第1の主面上に形成された半導体層と、
前記半導体層に互いに平行に第1の方向に延在してなる複数のトレンチと、
前記複数のトレンチを充填する充填体と、
前記半導体層の上方に設けられ、第1主電極に電気的に接続された第1電極パッドと、
前記第2の主面上に設けられた第2主電極と、
前記半導体層の上方に設けられ、前記第1主電極と前記第2主電極との間の導通を制御するゲート電極に接続されたゲート電極パッドと、
を有する半導体素子と、
前記第1電極パッドと前記ゲート電極パッドの少なくともいずれかに接続され、その引き出し方向と前記第1の方向との間の角度が45度以下である導電部材と、
を備えたことを特徴とする半導体装置が提供される。
また、前記半導体素子と離間して設けられたリードをさらに備え、前記導電部材は、前記リードに接続されてなるものとすることができる。
また、前記金属板は、前記第1電極パッドと前記ゲート電極パッドの前記少なくともいずれかに接続され前記引き出し方向に延在する引き出し部と、前記引き出し部から延伸する延伸部と、を有し、前記延伸部は、前記引き出し方向とは異なる方向に延伸してなるものとすることができる。
また、前記導電部材は、前記第1電極パッドと前記ゲート電極パッドの前記少なくともいずれかに対して半田付けされてなるものとすることができる。
この場合、前記金属板は、銅を主成分とする金属からなるものとすることができる。
図1は、本発明の実施の形態にかかる半導体装置の要部構造を例示する模式平面図である。
また、図2は、この半導体装置の全体構造を例示する模式平面図である。
さらに、図3乃至図5はそれぞれ、図2のA−A線、B−B線、C−C線断面図である。
なお、図1においては、理解を容易にするためにトレンチ16を模式的に表したが、実際の半導体素子10においては、表面には保護膜が形成されている。
なお、本発明における「引き出し方向」とは、ソース板80やゲート板90の長手方向とは限らない。例えば、後に図23を参照しつつ説明するように、ソース板80やゲート板90が屈曲した形状を有するような場合がある。このような場合には、ソース板80やゲート板90のうちで、それらとソース電極パッド44またはゲート電極パッド45との接続部の形態によって「引き出し方向」を判断する。つまり、この接続部において、ソース板80やゲート板90と、ソース電極パッド44やゲート電極パッド45と、の接触部から延在している方向を「引き出し方向」とすることができる。
これに対して、図1に表したようにトレンチ16の長手方向とソース板80及びゲート板90の引き出し方向を略平行とすると、半導体素子10に対する負荷を低減し、信頼性や製造歩留まりの点で有利となる。この点については、後に詳述する。
図7は、ゲート配線の平面形態を例示する一部透視模式平面図である。
また、図8は、図7のA部の拡大断面図である。
なお、図7においては、理解の容易のために、複数のゲート電極32のうちの一部のみを表した。
ゲート電極32は、図24に関して前述したように、トレンチ16の上において略平行に延在している。これらゲート電極32からの配線の引き出しのために、図7に表したように、素子の周辺部にゲート配線42を形成し、延在するゲート電極の両端(符号Aの部分)にゲートコンタクトを設けることができる。ゲートコンタクトの部分においては、図8に表したように、層間絶縁層34にコンタクト開口が設けられ、バリアメタル層38を介してゲート配線層42が接続されている。ゲート配線層42の上には、ポリイミドなどからなる保護膜48が設けられている。ゲート配線層42は、図7に表したように、半導体素子10の周辺部に沿って形成され、ゲート電極パッド45に接続されている。
すなわち、この部分においては、層間絶縁層34によってソース電極とは絶縁され、ゲート配線42の上に、ゲート電極パッド45が積層されている。ゲート電極パッド45の周囲は、ポリイミドなどからなる保護膜48により覆われている。ゲート電極パッド45は、例えば、メッキにより形成できる。ゲート電極パッド45の上には、半田47を介して銅(Cu)などからなるゲート板90が接続される。
すなわち、この部分においては、ゲート電極32は層間絶縁層34により覆われ、ソース領域24にソース配線層40が接続されている。ソース配線層40の上には、ソース電極パッド44が設けられ、その周期は、保護膜48により覆われている。ソース電極パッド44の上には、半田46を介して銅(Cu)などからなるソース板80が接続される。
図11は、比較例の半導体装置において、ソース電極パッドやゲート電極パッドの下に見られるクラックを例示する模式断面図である。
すなわち、比較例の場合、電極パッド44、45の下において、トレンチ16に隣接したn型ピラー領域12の上端部付近にクラックCが発生する傾向が認められた。これは、ソース板80やゲート板90を電極パッドに接続する工程や、その後に樹脂200により封止する工程などにおいて、機械的な負荷が印加されるためであると考えられる。
図13は、本発明者が試作したサンプルを例示する模式図である。
すなわち、ソース板80の引き出し方向を半導体メサMの長手方向に対して角度θだけ傾斜させたサンプルを試作した。その結果、傾斜角度θを45度以下とすると、概ね良好な特性と製造歩留まりが得られることが判明した。
図14は、ソース板80及びゲート板90を超音波ボンディングにより接続した実施例を表す模式平面図である。
図15は、本実施例の半導体装置のゲート板90の接続部の断面構造を表す模式図である。
また、図16は、本実施例の半導体装置のソース板80の接続部の断面構造を表す模式図である。
図17は、ソース電極パッド及びゲート電極パッドにワイアをボンディングした半導体装置を表す模式平面図である。
すなわち、本実施例においては、ソース電極パッド44とインナーリード60Aとの間は、ワイア92により接続されている。また、ゲート電極パッド45とインナーリード70Aとの間も、ワイア94により接続されている。
本実施例の場合、ソース電極パッド44及びゲート電極パッド45において、ワイア92、94の接続部の形状は、ワイアの直径方向に延伸した楕円状である。このような場合も、ワイア92、94の「引き出し方向」は、それぞれの軸心方向であるC−C線方向であるものとする。
すなわち、本実施例においては、ワイア92、94の引き出し方向、すなわち接続部における軸心方向であるC−C線の方向は、トレンチ16の長手方向に対して角度θだけ傾斜している。このような場合も、図13に関して前述したように、傾斜角度θを45度以内とすると、ワイア92、94をボンディングする際の圧力や超音波の振動、あるいは樹脂200を封止・硬化させる際に印加される引っ張り応力などを半導体メサMの長手方向に逃がすことができる。その結果として、半導体メサMにおけるクラックなどの発生を抑制でき、優れた初期特性、高い信頼性、高い製造歩留まりを実現できる。
本実施例においては、ひとつのパッケージの中に複数の半導体素子10が搭載されている。すなわち、インナーリード50Aの上には、ふたつの半導体素子10がマウントされている。これら半導体素子10の裏面側のドレイン電極は、インナーリード50Aに共通接続されている。
また、それぞれの半導体素子10には、ソース電極パッド44とゲート電極パッド45が設けられ、これらとインナーリード60A、70Aとが、ソース板80及びゲート板90により接続されている。接続方法は、図9及び図10に表した如く半田を用いてもよく、図14乃至図16に関して前述したように、超音波ボンディングを用いてもよい。また、ソース板80、ゲート板90の代わりに、図17乃至図19に表したように、ワイア92、94を用いてもよい。
図21は、本実施例の半導体装置の等価回路を表す模式図である。
すなわち、ふたつのトランジスタTr1、Tr2がドレインを共通接続されている。この回路において、例えば、トランジスタTr1を充電回路を開閉するためのスイッチング素子として用い、トランジスタTr2を放電回路を開閉するためのスイッチング素子として用いることができる。本実施例によれば、オン抵抗が低く、耐圧も高いDTMOSを搭載することにより、消費電力の低い電池駆動型システムを実現できる。
本実施例においては、ひとつの半導体素子10の中に複数の半導体素子部が集積されている。すなわち、半導体素子10には、第1の素子部10Aと第2の素子部10Bとが設けられている。これら素子部10A、10Bは、裏面側のドレイン電極はインナーリード50Aに共通接続されている。
そして、本実施例においても、ソース板80、ゲート板90の引き出し方向をトレンチ16の長手方向と略平行とすることにより、これらの接続の際あるいは、その後の樹脂封止や硬化の工程において、半導体メサMに負荷される圧力、振動、衝撃などをメサMの長手方向に逃がすことができる。その結果として、優れた初期特性、高い信頼性、高い製造歩留まりなどを得ることができる。
本実施例においては、ソース板80、ゲート板90がそれぞれまっすぐなストライプ状ではなく、屈曲した形状を有する。すなわち、ソース板80は、ソース電極パッド44に接続されている引き出し部80Aと、引き出し部80Aから延伸する延伸部80Bと、を有する。延伸部80Bは、引き出し部80Aからまず横方向に延伸し、しかる後に、引き出し方向と平行に延伸してインナーリード60Aに接続されている。
10A、10B 素子部
11 基板
12 n型ピラー領域
14 p型ピラー領域
16 トレンチ
20 p型ベース領域
22 p+型ベース領域
24 n++ソース領域
30 ゲート絶縁膜
32 ゲート電極
34 層間絶縁層
38 バリアメタル層
40 ソース配線層
42 ゲート配線層
44 ソース電極パッド
45 ゲート電極パッド
46、47 半田
48 保護膜
50A、60A、70A インナーリード
50B、60B、70B アウターリード
80 ソース板
90 ゲート板
92、94 ワイア
200 樹脂
M 半導体メサ
Claims (5)
- 第1及び第2の主面を有する半導体基板と、
前記半導体基板の前記第1の主面上に形成された半導体層と、
前記半導体層に互いに平行に第1の方向に延在してなる複数のトレンチと、
前記複数のトレンチを充填する充填体と、
前記半導体層の上方に設けられ、第1主電極に電気的に接続された第1電極パッドと、
前記第2の主面上に設けられた第2主電極と、
前記半導体層の上方に設けられ、前記第1主電極と前記第2主電極との間の導通を制御するゲート電極に接続されたゲート電極パッドと、
を有する半導体素子と、
前記第1電極パッドと前記ゲート電極パッドの少なくともいずれかに接続され、その引き出し方向が前記第1の方向と略平行な導電部材と、
を備えたことを特徴とする半導体装置。 - 第1及び第2の主面を有する半導体基板と、
前記半導体基板の前記第1の主面上に形成された半導体層と、
前記半導体層に互いに平行に第1の方向に延在してなる複数のトレンチと、
前記複数のトレンチを充填する充填体と、
前記半導体層の上方に設けられ、第1主電極に電気的に接続された第1電極パッドと、
前記第2の主面上に設けられた第2主電極と、
前記半導体層の上方に設けられ、前記第1主電極と前記第2主電極との間の導通を制御するゲート電極に接続されたゲート電極パッドと、
を有する半導体素子と、
前記第1電極パッドと前記ゲート電極パッドの少なくともいずれかに接続され、その引き出し方向と前記第1の方向との間の角度が45度以下である導電部材と、
を備えたことを特徴とする半導体装置。 - 前記半導体層は、前記トレンチに隣接して設けられた第1導電型の第1のピラー領域と、前記第1のピラー領域に隣接して設けられた第2導電型の第2のピラー領域と、を有し、
前記第2のピラー領域の表面に形成された第2導電型のベース領域と、
前記ベース領域の表面に形成され、前記第1主電極と電気的に接続された第1導電型の拡散領域と、が設けられたことを特徴とする請求項1または2に記載の半導体装置。 - 前記半導体素子と離間して設けられたリードをさらに備え、
前記導電部材は、前記リードに接続されてなり、
前記第1電極パッドと前記ゲート電極パッドの前記少なくともいずれかと前記導電部材との接続領域の重心点と、前記リードと前記導電部材との接続領域の重心点と、を結ぶ方向は、前記第1の方向と略平行であることを特徴とする請求項1〜3のいずれか1つに記
載の半導体装置。 - 前記導電部材は、金属板であることを特徴とする請求項1〜4のいずれか1つに記載の半導体装置。
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US10/975,356 US7253507B2 (en) | 2004-03-03 | 2004-10-29 | Semiconductor device |
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JP2004058948A JP4058007B2 (ja) | 2004-03-03 | 2004-03-03 | 半導体装置 |
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US20070057368A1 (en) * | 2005-09-13 | 2007-03-15 | Yueh-Se Ho | Semiconductor package having plate interconnections |
US7683464B2 (en) * | 2005-09-13 | 2010-03-23 | Alpha And Omega Semiconductor Incorporated | Semiconductor package having dimpled plate interconnections |
US7622796B2 (en) * | 2005-09-13 | 2009-11-24 | Alpha And Omega Semiconductor Limited | Semiconductor package having a bridged plate interconnection |
JP2007088264A (ja) * | 2005-09-22 | 2007-04-05 | Toshiba Components Co Ltd | 樹脂封止型半導体装置 |
US8237268B2 (en) | 2007-03-20 | 2012-08-07 | Infineon Technologies Ag | Module comprising a semiconductor chip |
US8680658B2 (en) * | 2008-05-30 | 2014-03-25 | Alpha And Omega Semiconductor Incorporated | Conductive clip for semiconductor device package |
JP6063629B2 (ja) | 2012-03-12 | 2017-01-18 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
CN105378932B (zh) * | 2014-01-16 | 2017-10-31 | 富士电机株式会社 | 半导体装置 |
JP6573005B1 (ja) * | 2018-07-04 | 2019-09-11 | 富士電機株式会社 | 半導体装置 |
JP7147859B2 (ja) | 2018-10-05 | 2022-10-05 | 富士電機株式会社 | 半導体装置、半導体モジュールおよび車両 |
JP7194855B2 (ja) * | 2021-03-18 | 2022-12-22 | ローム株式会社 | 半導体装置 |
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JP3993458B2 (ja) | 2002-04-17 | 2007-10-17 | 株式会社東芝 | 半導体装置 |
TWI287805B (en) * | 2005-11-11 | 2007-10-01 | Ind Tech Res Inst | Composite conductive film and semiconductor package using such film |
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