CN211238167U - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN211238167U
CN211238167U CN201922329704.4U CN201922329704U CN211238167U CN 211238167 U CN211238167 U CN 211238167U CN 201922329704 U CN201922329704 U CN 201922329704U CN 211238167 U CN211238167 U CN 211238167U
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conductive
semiconductor chip
package
lead frame
clip
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F·G·齐格利奥利
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STMicroelectronics SRL
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STMicroelectronics SRL
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    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract

本公开的实施例涉及半导体器件。半导体芯片被安装在引线框架上。用于半导体芯片的绝缘封装的第一部分由被模制到半导体芯片上的激光直接成型(LDS)材料来形成。传导性构造(通过激光钻孔LDS材料和镀制提供)在绝缘封装的第一部分的外表面与半导体芯片之间延伸。导电夹子被应用到绝缘封装的第一部分的外表面上，其中导电夹子被电耦合到传导性构造和引线框架。绝缘封装的第二部分由封装模制材料(环氧混合物)制成，其被模制到导电夹子上并且被应用到绝缘封装的第一部分的外表面上。

Description

半导体器件
技术领域
本说明书涉及诸如集成电路(IC)的半导体器件。
一个或多个实施例可以被应用到半导体封装，例如，QFN(四方扁平无引线)类型的半导体封装。
使用QFN封装的用于在汽车、工业与消费领域中的功率IC(例如，所谓的“智能”功率IC)是实施例的示例性的可能应用领域。
背景技术
例如，功率QFN电路可以使用利用软焊料附接的夹子(clip)。
诸如铜夹的夹子可以被采用来替代常规的线接合互连件，其目的是促进降低电阻和电感，同时改进热学性能。
针对某些器件类型“经定制”的夹子可以被直接安装在半导体焊盘上。
在存在多个裸片(堆叠或并排)、或者在混合的封装还包括布线的情况下(诸如在智能功率技术应用中的用于栅极或触发功能的线接合，或者用于数字信号的线接合)，依靠该解决方案可能结果是复杂的。
定制夹子可以表示封装成本的显著部分。
一般的夹子已经被提出，但它们非常昂贵且组装复杂。
并且，经由软焊料附接夹子可能结果是本质上“脏的”处理，该处理可能需要附加的清洁步骤。
在本领域中存在克服常规解决方案的前述缺陷的需要。
实用新型内容
本申请人已经发现在传统的半导体器件中，夹子的成本昂贵且其组装复杂。
因此，本实用新型提供了一种半导体器件(例如，QFN功率封装)。
在一个方面中，提供了一种半导体器件，其特征在于，包括：引线框架，引线框架具有被安装在引线框架上的至少一个半导体芯片；绝缘封装的至少一个部分，在引线框架上的至少一个半导体芯片之上，至少一个部分由激光直接成型材料制成，激光直接成型材料被模制到被安装在引线框架上的至少一个半导体芯片上，绝缘封装的至少一个部分具有外表面；至少一个导电构造，在绝缘封装的至少一个部分的外表面与至少一个半导体芯片之间延伸；以及导电夹子，被应用到绝缘封装的至少一个部分的外表面上，导电夹子被电耦合到至少一个导电构造并且电耦合到引线框架，其中至少一个半导体芯片被定位在介于引线框架和导电夹子之间。
在一些实施例中，该半导体器件包括：绝缘封装的至少一个另外部分，至少一个另外部分在至少一个半导体芯片之上，至少一个另外部分包括被模制到导电夹子上的封装模制材料，导电夹子被应用到绝缘封装的至少一个部分的外表面上。
在一些实施例中，该半导体器件包括：至少一个接触柱凸，至少一个接触柱凸被提供在至少一个半导体芯片上，至少一个接触柱凸在面向至少一个导电构造的位置中；开口，开口在激光直接成型材料中，开口延伸到至少一个接触柱凸；以及导电材料，导电材料填充开口以形成至少一个导电构造的至少部分。
在一些实施例中，该半导体器件包括：安装叶片，安装叶片用于在绝缘封装的至少一个部分的外表面处的导电夹子。
在一些实施例中，该半导体器件包括：至少一个导电线和/或带接合构造，至少一个导电线和/或带接合构造在引线框架与至少一个半导体芯片之间，至少一个导电线和/或带接合构造被嵌入在绝缘封装的至少一个部分中。
因为可以被应用于智能功率技术(例如，双极-CMOS-DMOS或BCD技术)，本公开的实施例提供的半导体器件促进了通过依靠基于LDS方案的成本的减少。
附图说明
现在将参考附图仅通过示例的方式描述一个或多个实施例，其中：
图1是根据本说明书的实施例的跨器件的横截面视图，
图2是根据本说明书的实施例的例示了器件的某些部分的平面图，其中为了易于说明位于图1的II-II平面的上方的某些部分被移除，
图3和图4是与图2的视图相似的另外视图，并且例示了根据本说明书的实施例的器件的某些部分，
图5例示了本说明书的实施例到器件的多个条带的可能扩展，以及
图6至图13例示了根据本说明书的实施例的方法中的步骤，其中图7A、图7B和图7C表示过孔的提供的细节，并且图9是以流程图的形式。
具体实施方式
在接下来的描述中，一个或多个具体细节被说明，其目的是提供本说明书的实施例的示例的深入理解。实施例可以在不具有一个或多个具体的细节的情况下，或是利用其他方法、部件、材料等，而被获取。在其他情况下，已知的结构、材料或操作可以不被详细图示或描述，以便实施例的某些方面将不会被掩盖。
在本说明书中对“实施例”或“一个实施例”的引用旨在指示与实施例相关描述的特定的配置、结构、或特点被包括在至少一个实施例中。因此，可以在本说明书的一个或多个地方存在的诸如“在实施例中”或“在一个实施例中”的短语不一定指代一个且相同的实施例。另外，特定的配置、结构、或特点可以在一个或多个实施例中以任何适当的方式组合。
在本文中使用的引用仅出于方便而被提供，并且因此不限定保护的范围或实施例的范围。
将以其他方式理解的是，本文中单独地或组合地结合附图的任何一个附图所讨论的细节和特征，不一定被限制为在如该附图中例示的实施例中使用；事实上，这样的细节和特征可以单独地或组合地被应用在附属于本文的附图中的任何其他附图所例示的实施例中。
如前所述，功率QFN电路可以使用夹子(例如用软焊料附接)作为常规线接合互连件的替代，其目的是促进低电阻和电感，同时还改进热学性能。
诸如美国专利号为7,663,211B2和8,049,312B2，以及美国专利申请公开号为2007/0114352A1和2008/0173991A1的美文档，是可能遭受如在前文中讨论的各种缺点的已知布置的示例，以上所有文档通过引用被并入本文。
图1是根据本说明书的实施例的跨(例如，以集成电路或IC的形式的)器件10的横截面视图。
如本文中例示的，器件10包括被布置在引线框架14的裸片焊盘部分140处的一个或多个半导体芯片或裸片12。
用于(多个)芯片或(多个)裸片12的电连接线(例如，信号和功率)可以以如下方式被提供(例如，在芯片或裸片的前表面或顶表面处)：
-经由线接合/带(ribbon)接合16、160(到引线框架14的外部分)和/或
-经由柱凸(stud bump)18和过孔20到用于夹子24的布线网络和叶片(paddle)22。
如本文所例示的，夹子24在(多个)芯片或(多个)裸片12的前表面或顶表面的上方延伸，夹子24具有延伸部240，该延伸部促进到引线框架14的外部分的电(和机械)耦合。
如先前所讨论的，通过诸如铜夹的夹子来替代(整体地或部分地)线接合/带接合互连件在本领域中是常规的，本文不必要对其提供更详细的描述。
如在图1中例示的(单个)器件10还具有器件封装，包括：
-第一封装材料261，其范围由虚线示出，第一封装材料261包括激光直接成型(LDS)材料，其被布置在介于引线框架14(具有(多个)芯片或(多个)裸片12)和夹子24(具有关联的叶片22)之间，使得过孔20(以及线接合16)延伸通过第一封装材料261；以及
-第二封装材料262，包括常规封装材料(例如，环氧材料)，其通过在夹子24(与(多个)芯片或(多个)裸片12相对)之上、以及在引线框架14的外部分之上延伸来完成器件封装。
如本领域技术人员众所周知的，激光直接成型(LDS)是在各种领域中被采用的技术，其可以涉及包含添加剂的树脂模制(例如，注塑模制)。激光束可以被应用到被模制部分的表面，以便将期望的图案转移到被模制部件的表面。然后，涉及诸如铜的金属的金属化处理(诸如无电镀制处理)可以被使用以在经激光处理的表面上镀制期望的传导性图案。LDS处理也已知以适合用于提供过孔或接触焊盘。
在图2至图5中，与结合图1已经讨论了的部件或元件类似的部件或元件由类似的附图标记来指示，并且对应的描述将出于简洁而不被重复。
本质上，图2例示了根据本说明书的实施例的器件10的某些部分的平面图，其中为了易于说明，位于图1的II-II平面上方的某些部分被移除。
图2进一步例示了混合(即，使用)如在160处例示的带、连同线接合16和柱凸18一起的可能。
柱凸18可以被用作用于激光钻孔的基础(如在下文中讨论的)，并且柱凸18可以是单个或多个堆叠。
图2还在附图标记142处突出显示了在引线框架14中可以利用回(back)蚀刻来移除的区域，并且突出显示了引线框架14的焊盘区域140A的提供，其用于与夹子延伸部240耦合。
通过突出显示提供在裸片焊盘140中的多个区域(岛)以容纳其他芯片或裸片12的可能，图3在图2上进一步扩展。
图4是引线框架14的底层表示。这样的表示将在裸片焊盘岛140处、焊盘区域140A、以及在引线框架14的外部分的引线处的无蚀刻区域(被共同地指示为144)，与引线框架14的蚀刻区域(例如，Cu蚀刻区域)对比。
图5一般地例示了延伸器件10的基础结构的可能，以及在下文中讨论的制造过程中的、到“多个”条带布置的步骤。
为了简便，图5中仅指示了引线框架14处的单独器件10的可能位置(被示出的八个这种位置仅仅是示例)以其他方式应理解的是，图3和图4中示出的单个位置的相同附图标记/表示适用于图5中的复数个位置。
在图1至图5中例示的夹子-QFN器件可以利用双重模制(doublemolding)过程来制造。
在本文所例示的处理中的第一步骤(或步骤的集合)可以涉及为器件/位置10或每个器件/位置10提供图3的基础结构，即：被布置在引线框架14的裸片焊盘部分140处的一个或多个半导体芯片或裸片12、连同朝向相应的外引线框架部分的线接合16和/或带连接16。
这样的第一步骤(或步骤的集合)涉及常规条件和技术，这使得不必要在本文中对其提供更详细的描述。
这还适用于在如下位置处创建(在(多个)芯片或(多个)裸片12的顶表面处的)柱凸18，在该位置处，如在下文中讨论的，过孔20将被激光钻孔。
提供柱凸18还被发现对保护对应的硅部位(焊盘)免受用于钻孔的激光束是有益的(例如，取决于被使用的激光束和/或在(多个)芯片或(多个)裸片12之上的LDS混合物261的厚度)。
图6例示了LDS材料到图5的条状布置上的第一模制步骤，其目的是创建嵌入(多个)芯片或(多个)裸片12的、图1的(电绝缘)LDS封装材料261的第一块(mass)，以及与其相关联的朝向相应的外引线框架部分的线接合16和/或带连接16。
诸如环氧基模制混合物或者液晶聚合物可以例示可以被用在实施例中的LDS材料，环氧基模制混合物具有被适配于由激光辐射激活的填料。
图7A至图7C例示了过孔20的创建，该过孔20在焊盘位置处延伸通过LDS封装材料261的第一块，在该焊盘位置处，与夹子22、24的连接是被期望的。
这可以涉及在如下位置处激光钻孔LDS材料461：在该位置，作为18的柱凸被提供在(多个)芯片或(多个)裸片12的顶表面处。
如在图7A至图7C中例示的，LDS材料261的激光钻孔可以涉及从LDS材料261的外表面2610开始，钻通LDS封装材料261的厚度：
-针对每个柱凸18一个过孔(图7A)；
-在某个柱凸区域上的一个共用开孔，以及单独的短过孔，单独的短过孔向下延伸至相应的柱凸18(图7B)；
-一个共用开孔向下延伸至柱凸18(图7C)。
无论采用何种选项，在LDS由激光激活之后，因此形成的(多个)开孔的壁可以通过依靠常规镀制技术而被镀制(例如，铜(Cu)镀制)，以便通过将在(多个)芯片或(多个)裸片12上的焊盘(例如，柱凸18)连接到用于焊接夹子的叶片22，来完成该结构，该叶片22被创建在LDS主体261的“顶部上”，LDS主体261具有延伸通过LDS主体261的过孔20。
这样的步骤在图8中被示意性地表示，其中柱凸18/过孔20的示例位置被示出对应于在图5和图6中例示的柱凸18/过孔20的位置。
图8还例示了通过提供叶片形状来执行镀制过程的可能，该叶片形状根据所期望的形状来选择。
图9的流程图例示了对应的可能的步骤序列，包括：通过激光处理创建期望的布线/形状(框100)；在柱凸18的区域之上创建过孔20(框102)；以及镀制(例如，电化学镀(galvanic plating)-框104)。
如在图10中例示的，夹子24可以随后被附接到顶叶片24，并且(经由延伸部240在140A处)被附接到引线框架14。在一个或多个实施例中，夹子24可以通过焊料焊或激光焊接而被附接到叶片22。
将意识到的是，夹子24可以是标准化类型的，该标准化类型的夹子24被适配于被容纳在模具腔体大小中，其用于LDS材料261的第一模制步骤。
如在图11中例示的，在焊接夹子之后，在常规封装材料(任何已知类型的适合于该目的的封装材料，例如，环氧混合物)的次级(在其之上)模制步骤中，图1的封装材料262的第二块可以被应用到图10中示出的结构上，用于最终密封该封装。
图12和图13一般地例示了回蚀刻(图12)的最终步骤(涉及常规技术的使用)以暴露引线框架、以及焊盘限定(图13)，其例如涉及：抗蚀剂覆盖以在器件底表面创建焊盘开口。然后，切割(再次通过依靠常规技术)可以导致如在图1中例示的个体器件10的分离。
根据本文例示的方法可以包括：
-提供引线框架(例如14)，在引线框架上具有至少一个半导体芯片(例如12)，
-将激光直接成型(LDS)材料模制到引线框架上的至少一个半导体芯片上，以提供针对引线框架上的至少一个半导体芯片的(电)绝缘封装的至少一个部分(例如261)，绝缘封装的至少一个部分具有外表面(例如2610)。
-提供至少一个电传导性构造(例如，一个或多个过孔20)，该导电构造在绝缘封装的至少一个部分的外表面和在引线框架上的至少一个半导体芯片之间延伸。
将导电夹子(例如24)应用到绝缘封装的至少一个部分的外表面上，该夹子被电耦合到至少一个导电构造和引线框架(例如在140A处)，其中至少一个半导体芯片被定位介于引线框架和夹子之间。
本文例示的方法可以包括：将模制材料模制到夹子上，该夹子被应用到绝缘封装的至少一个部分的外表面上，以提供针对引线框架上的至少一个半导体芯片的封装的至少一个另外部分(例如262)。
根据本文例示的方法可以包括：在至少一个半导体芯片上提供至少一个接触柱凸(例如18)，该接触柱凸面向所述至少一个导电构造。
根据本文例示的方法可以包括：在绝缘封装的至少一个部分的外表面处提供用于所述夹子的安装叶片(例如22)。
在本文例示的方法中，提供所述至少一个导电构造可以包括：
-激光钻孔(例如102)激光直接成型材料以提供通过激光直接成型材料至少一个孔，以及
-镀制(例如104)所述至少一个孔的内壁。
根据本文例示的方法可以包括：通过镀制绝缘封装的至少一个部分的外表面提供用于所述夹子的安装叶片。
根据本文例示的方法可以包括：通过焊料焊或激光焊，将导电夹子应用到绝缘封装的至少一个部分的外表面上。
根据本文例示的方法，其中该夹子旨在仅部分地替代线接合/带接合，该方法可以包括：在引线框架和至少一个芯片之间提供至少一个导电线(例如16)和/或带(例如160)接合构造，其中提供至少一个导电线和/或带构造是在将激光直接成型材料模制到引线框架上的至少一个半导体芯片之前，其中至少一个导电线和/或带接合构造被嵌入在绝缘封装的至少一个部分中。
根据本文例示的半导体器件(例如10)，可以包括：
-引线框架，在该引线框架上具有至少一个半导体芯片；
-激光直接成型材料，被模制到引线框架上的至少一个半导体芯片上，以提供针对引线框架上的至少一个半导体芯片的绝缘封装的至少一个部分，该绝缘封装的至少一个部分具有外表面；
-至少一个导电构造，其在绝缘封装的至少一个部分的外表面与引线框架上的至少一个芯片之间延伸；
-导电夹子，其被应用到绝缘封装的至少一个部分的外表面上，该夹子被电耦合到至少一个导电构造、以及被电耦合到引线框架，其中至少一个半导体芯片被定位为介于引线框架与夹子之间。
根据本文例示的半导体器件可以包括：针对引线框架上的至少一个半导体芯片的封装的至少一个另外部分，该至少一个另外封装部分包括被模制到夹子上的封装模制材料，该夹子被应用到绝缘封装的至少一个部分的外表面上。
根据本文例示的半导体器件可以包括以下特征的一个或多个特征：
-至少一个接触柱凸，其被提供在引线框架上的至少一个半导体芯片上，该至少一个接触柱凸面向至少一个导电构造；和/或
-安装叶片，用于在绝缘封装的至少一个部分的外表面处的所述夹子；和/或
-至少一个导电线和/或带接合构造，其在引线框架和至少一个半导体芯片之间，至少一个导电线和/或带接合构造被嵌入在绝缘封装的至少一个部分中。
在不损害基本原理的情况下，细节和实施例可以相对于仅作为示例公开的内容变化，甚至是显著地变化，而不背离保护的范围。
权利要求是本文所提供的本实用新型公开的不可或缺的部分。

Claims (5)

1.一种半导体器件，其特征在于，包括：
引线框架，所述引线框架具有被安装在所述引线框架上的至少一个半导体芯片；
绝缘封装的至少一个部分，在所述引线框架上的所述至少一个半导体芯片之上，所述至少一个部分由激光直接成型材料制成，所述激光直接成型材料被模制到被安装在所述引线框架上的所述至少一个半导体芯片上，所述绝缘封装的至少一个部分具有外表面；
至少一个导电构造，在所述绝缘封装的所述至少一个部分的外表面与所述至少一个半导体芯片之间延伸；以及
导电夹子，被应用到所述绝缘封装的所述至少一个部分的所述外表面上，所述导电夹子被电耦合到所述至少一个导电构造并且电耦合到所述引线框架，其中所述至少一个半导体芯片被定位在介于所述引线框架和所述导电夹子之间。
2.根据权利要求1所述的半导体器件，其特征在于，包括：所述绝缘封装的至少一个另外部分，所述至少一个另外部分在所述至少一个半导体芯片之上，所述至少一个另外部分包括被模制到所述导电夹子上的封装模制材料，所述导电夹子被应用到所述绝缘封装的所述至少一个部分的所述外表面上。
3.根据权利要求1所述的半导体器件，其特征在于，包括：
至少一个接触柱凸，所述至少一个接触柱凸被提供在所述至少一个半导体芯片上，所述至少一个接触柱凸在面向所述至少一个导电构造的位置中；
开口，所述开口在所述激光直接成型材料中，所述开口延伸到所述至少一个接触柱凸；以及
导电材料，所述导电材料填充所述开口以形成所述至少一个导电构造的至少部分。
4.根据权利要求1所述的半导体器件，其特征在于，包括：
用于在所述绝缘封装的所述至少一个部分的所述外表面处的所述导电夹子的安装叶片。
5.根据权利要求1所述的半导体器件，其特征在于，包括：
至少一个导电线和/或带接合构造，所述至少一个导电线和/或带接合构造在所述引线框架与所述至少一个半导体芯片之间，所述至少一个导电线和/或带接合构造被嵌入在所述绝缘封装的所述至少一个部分中。
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