CN102197483A - 具有氮化硅电荷陷阱层的非挥发性内存 - Google Patents

具有氮化硅电荷陷阱层的非挥发性内存 Download PDF

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CN102197483A
CN102197483A CN2009801424516A CN200980142451A CN102197483A CN 102197483 A CN102197483 A CN 102197483A CN 2009801424516 A CN2009801424516 A CN 2009801424516A CN 200980142451 A CN200980142451 A CN 200980142451A CN 102197483 A CN102197483 A CN 102197483A
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silicon nitride
nitride layer
silicon
layer
process gas
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M·巴尔塞努
V·佐泊考伏
夏立群
A·诺利
R·阿尔加瓦尼
D·R·威蒂
A·奥-巴亚缇
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Applied Materials Inc
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Applied Materials Inc
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Abstract

本发明提供一种闪存装置及形成该闪存装置的方法。在一版本中，该闪存装置包括一掺杂氮化硅层，其具有包含碳、硼或氧的一掺杂剂。该掺杂氮化硅层在该层中产生较高数目且较高浓度的氮及硅悬键且提供一非挥发性内存装置的单位单元的电荷固持能力及电荷保持时间的增加。

Description

具有氮化硅电荷陷阱层的非挥发性内存
背景技术
非挥发性内存装置(诸如闪存)能够在没有来自外部功率源的功率的情况下保持所储存的电荷。闪存包含内存单元的数组，每一内存单元经配置以储存与电荷或门极临限电压相对应的一或多个位的讯息。举例而言，新近的闪存装置可在每单元储存若干位，且利用可呈现两个以上不同位准的参数。闪存装置通常视其用于储存电荷的结构而具有两种类型。浮动栅极型闪存将电荷储存在一安置于控制栅电极下的浮动栅电极中。然而，导电浮动栅电极需电隔离以便保留数据，且栅极结构具有较难制造的高深宽比。又，此闪存装置的密度增加，相邻内存单元之间的间距减少，因而在相邻浮动栅极单元之间产生降低电荷保留时间的电耦合。
与浮动栅极内存装置相比，电荷陷阱型闪存(charge trap type flash memory)可用更少更简易的步骤制造。电荷陷阱内存使用由诸如氮化硅的材料形成的栅极绝缘层，其提供电荷陷阱位点。然而，随着此类装置变小，基板上可用以建立个别电荷陷阱单元的净面积减少。因此，可加载至电荷陷阱层上的电子数目亦减少。电荷陷阱单元容量的减少将导致每一单位单元能储存的讯息量的减少。
鉴于包括此等及其它缺陷的各种原因，尽管各种闪存装置已取得诸多发展，人们仍在不断寻求内存装置及电荷陷阱装置的进一步改良。
发明内容
一种闪存装置经由在基板上形成二氧化硅层来生产。在二氧化硅层上形成掺杂氮化硅层，该掺杂氮化硅层包含掺杂剂(包含碳、硼或氧)。将介电材料沉积于该掺杂氮化硅层上，且将导电栅极沉积于该介电材料上。
该闪存装置包含一含硅的基板、该基板上的二氧化硅层、及该二氧化硅层上的掺杂氮化硅层。该掺杂氮化硅层包含掺杂剂(包含碳、硼及氧)。在该掺杂氮化硅层上形成介电材料，且在该介电材料上形成导电栅极。
在另一方法中，在一基板上形成二氧化硅层，且在该二氧化硅层上形成氮化硅层。该氮化硅层包含一成分梯度，在其中硅氮比是沿层厚度而变化。将介电材料沉积于该氮化硅层上，且将导电栅极层沉积于该介电材料上。
另一种闪存装置包含一含硅的基板、该基板上的二氧化硅层、及该二氧化硅层上的氮化硅层。该氮化硅层包含一成分梯度，在其中硅氮比是沿着层厚度而变化。将介电材料沉积于该氮化硅层上，且将导电栅极沉积该介电材料上。
另一方法包含在一基板上形成二氧化硅层且在该二氧化硅层上形成氮化硅层。将该氮化硅层暴露于具有约150nm至约1200nm的波长的紫外辐射。将介电材料沉积于该氮化硅层上，且将导电栅极沉积于该介电材料上。
在又一方法中，在一基板上形成二氧化硅层且在该二氧化硅层上形成氮化硅层。将该氮化硅层暴露于电子束。将介电材料沉积于该氮化硅层上，且将导电栅极沉积于该介电材料上。
在另一方法中，在一基板上形成二氧化硅层。经由以下步骤在该二氧化硅层上形成经等离子体处理的氮化硅层：(1)将该基板置放在工艺区中；(2)经由以下步骤将氮化硅层沉积于该基板上(i)将第一工艺气体引入该工艺区中，该第一工艺气体包含含硅组份及含氮组份，及在该工艺区中产生该第一工艺气体的等离子体；及(3)经由以下步骤形成经等离子体处理的氮化硅层(i)停止或改变第一工艺气体的流动以将第二工艺气体提供至工艺区中，该第二工艺气体包含惰性或不反应的气体，及(ii)在工艺区中产生第二工艺气体的等离子体以处理经沉积的氮化硅层，将介电材料沉积于该氮化硅层上，且将介电栅极沉积于该介电材料上。
附图说明
经由参考以下描述、随附申请专利范围及图标本发明实例的随附图式，本发明的此等特征、方面及优点将变得更易于理解。然而，应理解，每一个特征结构可广泛用于本发明中而并非仅用于特定图式的情形下，且本发明包括此等特征结构的任何组合，其中：
图1为展示一基板的示意横截面图，其具有经处理的氮化硅特征结构的闪存装置；
图2为作为PE-CVD沉积腔室的一基板处理腔室的一实施例的示意图；
图3为用于将氮化硅材料暴露于适合的能量束源的暴露腔室的示意图；
图4A为展示基态及激态键的键能作为原子间距离的函数的模型；及
图4B为展示对于基态及激态键而言拉伸(H3Si)N-H的N-H键所需的能量的模型。
具体实施方式
在一实施例中，闪存装置20制造于包含半导体的基板22(诸如硅晶圆、化合物半导体或介电质)上。硅晶圆包含硅、锗或硅锗的单晶体或大晶体。示范性化合物半导体包含砷化镓。适合的介电质包含玻璃板或显示器，且可包括(例如)硼磷硅酸盐玻璃、磷硅酸盐玻璃、硼硅酸盐玻璃及磷硅酸盐玻璃，以及其它材料。
在基板22上形成二氧化硅层24以充当穿隧氧化膜。穿隧氧化膜可接触源极/汲极32、34，其由形成于半导体基板22中的杂质区域所组成。二氧化硅层24可用适当方法(包括CVD或PECVD)使用包括含硅化合物及含氧化合物(诸如四乙氧基硅烷(TEOS)、硅烷、氧及其它类似气体)的工艺气体来形成。二氧化硅层24亦可经由氧化一硅晶圆的表面来制成。通常，二氧化硅层24具有约1至约6nm的厚度。
在二氧化硅层24上形成氮化硅层26。使用氮化硅层26作为用于闪存装置20的电荷捕捉层。电荷捕捉或储存层包括陷阱位点，其储存通过穿隧氧化膜的电荷。在氮化硅层26的沉积之前、期间或之后，如本文所描述，处理氮化硅层以增加层的电荷保持能力。
氮化硅之外的介电材料28经沉积于氮化硅层26上。介电材料28充当电荷阻挡层，其减少电荷陷阱层中捕捉的电子泄漏至栅电极30。阻挡层亦可防止或阻挡来自其它方向的电荷通过，即，自栅电极30进入电荷陷阱捕捉层中。介电材料28可为高k介电质，诸如Al2O3、SiO2、HfO2、ZrO2、LaO、LaAlO、LaHfO、HfAlO、HfAlON、HfSiOx、HfSiON及其组合。一种适合的高k介电材料包含氧化铝，其具有约9至11的介电常数值(k)。介电材料28可用物理气相沉积(PVD)、原子层沉积(ALD)或化学气相沉积(CVD)来沉积。
在介电材料28上形成栅电极30。栅电极30由一种具有适合于单位单元的功函数的导电材料形成。举例而言，栅电极30可为由金属栅极，其由元素金属、金属合金或金属化合物(诸如Mo、Ta、Ti、W、HfN、NiTa、Mo2N、TaN、TiN、WN及WSi及其组合)所制成。栅电极30亦可为金属化合物，其包含与氮或硅组合的金属。栅电极30可进一步为具有适当功函数的非金属导体(诸如多晶硅)。可用习知PVD、ALD及CVD方法沉积栅电极30。
栅电极30、顶部介电层28、氮化硅层26及氧化硅层24经图案化以形成如图1中所示的堆栈结构。此后，将掺杂剂植入半导体基板22的暴露于堆栈结构两侧上的表面中以形成掺杂区域。此掺杂区域经热处理以形成源极32及汲极34，从而完成闪存装置20的单位单元。在闪存装置20中，氮化硅层26充当捕捉且储存电荷的电荷陷阱。穿隧通过二氧化硅层24的电子可被捕捉于氮化硅层26中。临界电压视电子是否已经被捕捉于电荷陷阱层中而变化。
在不受解释限制的情况下，已经发现可经由以若干不同方法中的一者及此等方法的组合来处理氮化硅层26而获得较佳电荷保持性质。已经确定，氮化硅层26中的电荷陷阱浓度及分布取决于其成分及结构。特定而言，氮化硅层26中硅悬键与氮悬键的浓度比率据信将影响该层的电荷保持性质。进而可相信，可经由增加或最大化硅悬键的浓度可增加电荷保持时间。增加氮化硅层26中的硅悬键的数目显现可增加载体陷阱浓度。然而，硅悬键在能带隙中建立非常浅的陷阱。浅陷阱包含不够深的电位能阶。因此，具有高浓度的硅悬键的氮化硅层26加大了电荷损失的可能性。甚至少量热能亦可能导致所保持的电荷的热散逸(de-trapping)，且因此导致电荷损失。
据信，现在所描述的处理氮化硅层26的方法可增加带隙中较深能级的悬键浓度，以减少电荷的热散逸或其它散逸的可能性。另外，当电荷被捕捉至较深能量井相对应的特定位点中时，由于电荷倾向于隔离于能量井内且在施加外部能量的情况下不容易迁移或扩散出陷阱位点之外，故将实质性地增加电荷保持。因此，电荷陷阱位点的数目以及在氮化硅层26中建立的电位能量井的深度皆可显著改良且增加电荷保持。
一种增加具有较深能量井的可用电荷陷阱位点数目的方法包含增加氮化硅层26中的氮悬键的数目。氮悬键与硅悬键相比而言通常具有较深电位井。一种增加氮悬键的数目的方法为自氮化硅层26移除氢原子。此外，对氮化硅层26添加掺杂剂材料亦可导致网络内电子向掺杂剂位点重新分配，此进一步增加氮悬键的数目。
然而，仍需要维持硅悬键的基本数目。此因为硅悬键的结构较易于诱发，且亦可改良电荷保持速度。特定而言，由于硅悬键具有较宽、较浅的能量井，故只需较少能量来将电荷移送至由于硅悬键的存在而建立的电荷陷阱中。因此，希望使用某一比率的硅悬键与氮悬键，以最佳化电荷保持速度同时仍能延长电荷保持时间。据信，现在描述的沉积及处理氮化硅层26的方法可理想地引入硅、氮悬键的最佳比率。
在本工艺的一方面中，已经确定可经由控制氮化硅层26的沉积期间的处理参数来增加电荷陷阱保持时间。在PECVD工艺中，使用包含含硅组份及含氮组份或同时含硅与氮的单一组份的工艺气体来沉积氮化硅。含硅组份可为(例如)硅烷、乙硅烷、三甲基硅烷基(TMS)、三(二甲胺基)硅烷(TDMAS)、双(第三丁胺基)硅烷(BTBAS)、二氯硅烷(DCS)及其组合。适合的硅烷流速为约5至约200sccm。含氮组份可为(例如)氨、氮及其组合。氨的适合流速为约10至约600sccm。除非另有具体说明，否则在此等工艺中，电极功率位准通常经维持在约100至约400瓦特；电极间距为约5mm(200密耳)至约12mm(600密耳)；工艺气体压力为约1托至约4托；且基板温度为约300至约600℃。
工艺气体亦可包括以较反应气体组份大的体积提供的稀释气体，其充当稀释剂且至少部分地充当含氮气体反应物。举例而言，可以约5000至约30,000sccm的流速添加氮。当沉积氧氮化硅材料时，工艺气体亦可含有诸如含氧气体(例如氧气)的额外气体。可包括约100至约5,000sccm的流速的惰性气体(诸如氦或氩)的其它气体。
在一方面中，在沉积工艺期间改变沉积条件以形成一具有硅氮比沿层厚度变化的成分梯度的氮化硅层26。工艺条件中的调整经选择以提供一包含一成分梯度的氮化硅层，在该成分梯度中硅氮比沿层厚度而变化足够高的量，用以相对于均匀氮化硅层而言增加氮化硅层的电荷保持时间。
在此工艺的一版本中，将具有第一硅氮比的氮化硅沉积于基板上。在此工艺中，将工艺气体引入工艺区中，该工艺气体包含本文所描述的含硅组份与含氮组份。工艺区中工艺气体的等离子体是经由将第一功率位准的能量施加至工艺区周围的电极来产生。此后，经由将施加至电极的能量改变为第二功率位准来沉积具有第二硅氮比的氮化硅。在一版本中，第一功率位准比第二功率位准高至少约200W。举例而言，第一功率位准可包含300瓦特以下，第二功率位准包含至少约10瓦特。
在此工艺的另一版本中，经由在工艺区中产生工艺气体的等离子体的同时维持进入工艺区的工艺气体的第一压力，将具有第一硅氮比的氮化硅沉积于基板上。此后，经由维持工艺区中工艺气体的第二压力来沉积具有第二硅氮比的氮化硅。举例而言，第一压力可比第二压力高至少约0.1托。在一版本中，第一压力为约20托以下，第二压力为至少约1托。
在又一版本中，经由改变引入工艺区中的工艺气体的成分在基板上形成具有第一及第二硅氮比的氮化硅。举例而言，可使用包含含硅的气体组份(包含硅烷(SiH4))、氮气体组份(包含氨(NH3))及稀释气体组份(包含氮(N2))的工艺气体来沉积氮化硅。最初，使用含硅组份与含氮组份呈第一比率的第一工艺气体，且在工艺区中产生该工艺气体的等离子体。此后，使用含硅组份与含氮组份呈第二比率的第二工艺气体，且在工艺区中产生该工艺气体的等离子体。含硅组份与含氮组份的第一比率为100∶1以下，且含硅组份与含氮组份的第二比率为至少约1。举例而言，硅烷与氨的比率可介于约1∶1至约1∶3的范围中。
在一实例中，NH3的流速可维持在500sccm，同时SiH4的流速可自25sccm至50sccm而变化；且可保持工艺条件恒定在20,000sccm的N2流速；6托的压力；30瓦特的功率位准；430℃的温度及12mm(480密耳)的工艺电极间距。
在另一实例中，NH3的流速可自50sccm至500sccm而变化，而SiH4为25或50sccm的恒定流速。
通常，SiH4流速与NH3流速的较低比率将提供富含氮的膜。因此，当SiH4与NH3的流速比率为1∶10时，工艺将沉积具有0.6的Si/N配比的氮化硅材料。
在以上所述的版本中，所得闪存装置20包含一具有硅氮比沿层厚度变化的成分梯度的氮化硅层26。举例而言，氮化硅层26可具有硅氮比沿层厚度而变化足够高的量以相对于非掺杂氮化硅层而言增加氮化硅层的电荷保持时间的成分梯度。在一版本中，氮化硅层包含一硅氮比沿层厚度变化至少约1％的成分梯度。氮化硅层亦可具有一硅氮比沿层厚度变化约0.4至约1.5的成分梯度。如下文描述，亦可用包含碳、硼或氧的掺杂剂来掺杂变化氮化硅层的成分。
图2中图示了可用以执行以上所述的氮沉积工艺的基板处理腔室40的一实施例。腔室40经提供以说明一示范性腔室，然而，对于熟习此项技术者而言，显而易见亦可使用其它腔室。因此，本发明的范畴不应限于本文所描述的示范性腔室。
通常，腔室40为适于处理基板22(诸如硅晶圆)的等离子体增强化学气相沉积(PE-CVD)腔室，一适合的腔室为可由位于圣大克劳拉市的应用材料公司所购得的Producer
Figure BPA00001350205000071
SE型腔室。腔室40包含外壳壁48，其包括封闭工艺区42的顶部52、侧壁54及下壁56。腔室40亦可包含衬垫(未图示)，其里衬围绕工艺区42的外壳壁48的至少一部分。为了处理300mm硅晶圆，腔室通常具有约20,000至约30,000cm3的体积，且更通常而言约24,000cm3。
在工艺循环期间，降低基板支撑件58并用基板运输件64(诸如机器人臂)使基板22通过入口端62并将其置放在支撑件58上。可在一用于负载及卸载的低位与一用于基板22的处理的可调高位之间移动基板支撑件58。基板支撑件58可包括封闭的电极44a，用以自引入腔室40中的工艺气体产生等离子体。基板支撑件58可由加热器68加热，该加热器68可为电阻性加热组件(如图所示)、加热灯(未图示)及等离子体本身。基板支撑件47通常包含陶瓷结构，该陶瓷结构具有一接收表面以接收基板22，且可保护电极44a及加热器68免受腔室环境影响。在使用中，对电极44a施加射频(RF)电压且对加热器68施加直流(DC)电压。基板支撑件58中的电极44a亦可用以将基板22电夹持至支撑件58。基板支撑件58亦可包含一或多个环(未图示)，其至少部分地围绕支撑件58上的基板22的周边。
在将基板22负载至支撑件58上之后，将支撑件58升高至一较接近气体分配器72的处理位置并在其间提供所要之间隙距离ds。该间距距离可为约2mm至约12mm。气体分配器72位于工艺区42上方，用于在整个基板22上均匀分散工艺气体。气体分配器72可分别将第一及第二工艺气体的两个独立流传送至工艺区42而不会在其引入工艺区42之前混合气体流，或者可在将工艺气体预混合之后将预混合的工艺气体提供给工艺区42。气体分配器72包含具有孔76的面板74，孔76允许工艺气体经其通过。面板74通常由金属制成以允许对其施加电压或电位，且藉此充当腔室40中的电极44a。适合的面板74可由具有阳极化涂层的铝所制成。
基板处理腔室40亦包含第一及第二气体供应器80a、b以将第一及第二工艺气体传送至气体分配器72，气体供应器80a、b各包含一气源82a、b、一或多个气体管道84a、b及一或多个气体阀86a、b。举例而言，在一版本中，第一气体供应器80a包含第一气体管道84a及第一气体阀86a以将第一工艺气体自气源80a传送至气体分配器72的第一入口78a，且第二气体供应器80b包含第二气体管道84b及第二气体阀86b以将第二工艺气体自第二气源80b传送至气体分配器72的第二入口78b。
可经由将电磁能量(例如高频电压能量)耦合至工艺气体以激发工艺气体，以自工艺气体形成等离子体。为了激发第一工艺气体，在(i)第一电极44a(其可为气体分配器72、顶部52或腔室侧壁54)与(ii)支撑件58中的电极44b之间施加电压。在一对电极44a、44b上施加的电压将能量电容性地耦合至工艺区42中的工艺气体。通常，施加至电极44a、b的电压为以一射频振荡的交流电压。通常，射频涵盖约3kHz至约300GHz的范围。为了本申请案的目的，低射频为低于约1MHz，更佳为约100KHz至1MHz的射频(诸如约300KHz的频率)。同样为了本申请案的目的，高射频为约3MHz至约60MHz，且更佳为约13.56MHz的射频。以约10W至约1000W的功率位准将所选射频电压施加至第一电极44a，且第二电极44b通常接地。然而，所使用的特定射频范围及所施加电压的功率位准视待沉积的材料类型而定。
腔室40亦包含气体排气装置90，用以自腔室40移除废工艺气体及副产物并维持工艺区42中的工艺气体于一预定压力。在一版本中，气体排气装置90包括泵送信道92，其接收来自工艺区42的废工艺气体、排气端94、节流阀96及一或多个排气泵98以控制腔室40中的工艺气体压力。排气泵98可包括涡轮分子泵、低温泵、粗抽泵及具有一个以上功能的组合功能泵中的一或多者。腔室40亦可包含入口端或管道(未图示)，其通过腔室40的下壁56以将冲洗气体传送的腔室40中。冲洗气体通常自入口端向上流过基板支撑件58到达环形泵送通道。在处理期间，使用冲洗气体用以保护基板支撑件58及其它腔室部件的表面免受不需要的沉积。冲洗气体亦可用以以所要方式影响工艺气体的流动。
亦提供控制器102以控制腔室40的操作及操作参数。控制器102可包含(例如)处理器及内存。处理器执行腔室控制软件，诸如储存在内存中的计算机程序。内存可为硬盘驱动机、只读存储器、闪存或其它类型的内存。控制器102亦可包含其它部件，诸如软盘驱动机及插卡框架。插卡框架可含有单板计算机、模拟及数字输入/输出板、接口板及步进马达控制器板。腔室控制软件包括指示时序、气体的混合、腔室压力、腔室温度、微波功率位准、高频功率位准、支撑件位置及特定工艺的其它参数的指令组。
腔室40亦包含功率源104以将功率传送至各腔室部件，诸如基板支撑件58中的第一电极44a及腔室中的第二电极44b。为了将功率传送至腔室电极44a，44b，功率源104包含射频电压源，其提供具有所选射频及所要可选功率位准的电压。功率源104可包括单一射频电压源或高低射频皆有提供的多个电压源。功率源104亦可包括RF匹配电路。功率源104可进一步包含静电充电源以对基板支撑件58中的电极(常为静电夹盘)提供静电电荷。当在基板支撑件58内使用加热器68时，功率源104亦包括将适当可控电压提供至加热器68的加热器功率源。当要向气体分配器72或基板支撑件58施加DC偏压时，功率源104亦包括DC偏压源，其连接至气体分配器72的面板74的导电金属部分。功率源104亦可包括用于其它腔室部件(例如腔室的马达或机器人)的功率源。
基板处理腔室40亦包含诸如热电偶或干涉仪的温度传感器(未图标)，用以侦测腔室40内的表面(诸如部件表面或基板表面)的温度。温度传感器能够将其数据中继至腔室控制器102，腔室控制器102随后可使用温度数据(例如)经由控制基板支撑件58中的电阻性加热组件来控制处理腔室40的温度。
掺杂剂材料
在另一版本中，以建立较佳电荷陷阱位点的材料来掺杂氮化硅层26。适合的材料包含(例如)碳、硼、氧或其混合物。在此方法中，在二氧化硅层24上形成掺杂氮化硅层。掺杂氮化硅层包含碳、硼或氧的任一者的一掺杂剂含量。以足够高的的百分比来提供掺杂剂，以相对于未掺杂氮化硅层而言增加氮化硅层26的电荷保持时间。在一版本中，掺杂剂含量(其为氮化硅中的掺杂剂百分比)为足够高，用以相对于未掺杂氮化硅层而言将氮化硅层26的电荷保持时间增加至少约5％。举例而言，相对于氮化硅材料而言，适合的掺杂剂含量包含约1％至约50％的百分比。在沉积期间，经由将含掺杂剂之前体添加至沉积化学品，用以将掺杂剂引入膜中。举例而言，为达成5％B掺杂，将100sccm B2H6添加至SiH4(40sccm)及NH3(1000sccm)的等离子体。
若干方法可用以用包含碳、硼或氧的掺杂剂来掺杂氮化硅层26。在一方法中，使用习知方法来沉积氮化硅层26。举例而言，如以上所描述，可使用包含SiH4、NH3及N2的工艺气体来沉积氮化硅层26。在氮化硅层26的沉积期间或之后，将该层暴露于一掺杂剂工艺气体，其包含含碳物质、含硼物质或含氧物质中至少一者。激发掺杂剂工艺气体以形成等离子体进而用包含碳、硼或氧的掺杂剂来掺杂所沉积的氮化硅层26。掺杂剂工艺气体的适合的实例包括含碳物质(诸如TMS、C2H4)、含硼物质(诸如乙硼烷)及/或含氧物质(诸如N2O)或其混合物。使用由维持在100与1200密耳之间的距离的电极供以功率的等离子体来激发掺杂剂工艺气体。
在另一方法中，沉积氮化硅层26且随后将其暴露于包含碳、硼或氧中至少一者的工艺气体，同时加热基板以用包含碳、硼或氧的掺杂剂来掺杂所沉积的氮化硅层26。适合的掺杂剂工艺气体的实例包括含碳物质(诸如CH4、TMS)、含硼物质(诸如B2H6)及/或含氧物质(诸如N2O)或其的混合物。在掺杂工艺期间，基板经加热至至少约50℃，或甚至约300℃至约550℃的温度。
上文描述且图2中展示的腔室亦可用以处理氮化硅层26以形成如所描述的掺杂氮化硅层。所得闪存装置20包含一含硅的基板、该基板上的二氧化硅层24及该二氧化硅层上的掺杂氮化硅层26，该掺杂氮化硅层包含一含碳、硼或氧的掺杂剂。
紫外辐射暴露
在形成闪存装置的另一方法中，在氮化硅层26的沉积期间或之后，将该层暴露于能量束(诸如紫外辐射或电子束)。据信，紫外辐射及电子束均可将氮化硅层中的电荷陷阱深度增加至少5％。将所沉积的氮化硅材料暴露于紫外辐射或电子束，可经由使非想要的氢键(诸如吸收宽带UV辐射的Si-H及N-H键)破裂从而导致减少所沉积的材料的氢含量。剩余硅原子与可用氮原子结合形成Si-N键。自FTIR光谱可见，在以紫外辐射处理之后，N-H拉伸峰值(stretch peak)与Si-H拉伸峰值的尺寸皆显著减少，而Si-N拉伸峰值的尺寸增加。此证明在紫外处理之后，所得氮化硅材料含有更少N-H及Si-H键及更多数目的Si-N键(此为所要的)。
可在沉积腔室40本身内或在一独立腔室中执行紫外线或电子能量束暴露。举例而言，在基板22上沉积氮化硅层26的期间或紧随其后，可将氮化硅层26暴露于沉积腔室40中的紫外线或电子束辐射。可在CVD腔室中原位施加紫外线或电子束。据信，沉积期间的紫外线或电子束暴露使非所要的键一经形成即破裂，从而增加形成于氮化硅层26中的电荷陷阱的深度。
图4A中展示一模型，该模型显示R-H键的键能作为原子间距离的函数，R为基原子，诸如在(H3Si)N-H的状况下R为N。图标的键能曲线针对一基态(ground state)键与一受激(excited)键。如垂直箭头所示，将受激键拉伸一初始距离所需要的能量远小于基态键拉伸相同初始距离所需要的能量。因此，将键自受激态分裂较直接自基态分裂要更为容易，且因此自激态键获得由键分裂形成的所要悬键亦更为容易。
图4B中展示一模型，该模型显示对于激态N-H键及基态N-H键二者而言拉伸(H3Si)N-H的N-H键所需的能量。此进一步说明了激态键的拉伸比基态键的拉伸需要较少能量。因此可相信，键分裂及悬键形成即为增加形成于氮化硅层26中的电荷陷阱的深度的机制。
图3展示暴露腔室106的示范性实施例，其可用以将基板22暴露于紫外辐射或电子束处理。在所示版本中，腔室106包括基板支撑件58，其可在暴露源108远侧的释放位置与源108附近的提升位置之间移动，以允许其间之间距调整。基板支撑件58将基板22支撑在腔室106中。在基板22的插入暴露腔室106及自暴露腔室106的移除期间，基板支撑件58可移动至加载位置，且此后，在具有所沉积的氮化硅材料的基板22暴露于紫外辐射或电子束期间，支撑件58升高至举升位置以最大化暴露位准。腔室106进一步包含加热器110(诸如电阻性组件)，其可用以在基板22的暴露期间将基板22加热至所要温度。气体入口112经提供以将气体引入暴露腔室106中，且气体出口114经提供以自腔室106排出气体。
暴露腔室106进一步包括提供适合的能量束(诸如紫外辐射或电子束)的暴露源108。适合的紫外辐射源可发出单一紫外波长或一宽带段的紫外波长。适合的单波长紫外源包含提供172nm或222nm的单紫外波长的准分子紫外源。适合的宽带源产生具有波长约200至约400nm的紫外辐射。此类紫外源可自USA的Fusion Company或USA的Nordson Company获得。氮化硅材料可经暴露于具有其它波长的紫外辐射，其经由灯具所产生，该灯具含有在受电刺激时以特定波长辐射的气体。举例而言，适合的紫外灯可包含Xe气体，其产生具有172nm的波长的紫外辐射。在其它版本中，灯具可包含其它具有不同相应波长的气体，例如，243nm波长的汞灯辐射，140nm波长的氘辐射及222nm波长的KrCl2辐射。经由改变气体的相对浓度，自辐射源输出的波长含量可经选择以同时暴露所有所需波长，从而最小化必需的暴露时间。在另一版本中，汞灯可用以产生具有200与600nm间的最高强度的宽带光谱。
CVD沉积腔室40及暴露腔室106亦可共同整合于一由单个机器人臂服务的多腔室处理平台(未图示)上。暴露腔室106及CVD沉积腔室40的部件(可包括暴露源108、基板支撑件58、马达、阀或流量控制器、气体传送系统、节流阀、高频功率源及加热器)以及整合处理系统的机器人臂全部可由一系统控制器经由适当控制线来控制。系统控制器依来自光学传感器的反馈来判定可移动机械组件的位置，诸如在控制器的控制下由适当马达移动的节流阀96及基板支撑件58。。
对于独立暴露腔室106中的暴露处理，将具有根据前述沉积工艺或此项技术中已知的其它沉积工艺中任一者所沉积的氮化硅层26的基板插入至暴露腔室106中且置放在位于低位的基板支撑件58上。随后将基板支撑件58升高至提升位置，将支撑件中的光学加热器110通电，并启动暴露源108。在暴露期间，可使气体(诸如氦)循环通过暴露腔室106，以改善基板与支撑件之间的热传递速率。亦可使用其它气体。在辐射暴露的周期之后，停用暴露源108且将基板支撑件58降低回释放位置。随后自暴露腔室106移除带有经暴露的氮化硅层26的基板。或者当工艺腔室配备有所需的暴露源108时，可在工艺腔室40中原位执行此工艺。
适合的沉积工艺条件如以上所描述。在400℃执行紫外线处理，其中总暴露时间为5至10分钟。可经由包含以下条件的工艺气体来沉积氮化硅层26：60sccm流速的硅烷；900sccm流速的氨；10,000sccm流速的氮；及6托的工艺气体压力；100瓦特的电极功率位准；及11mm的电极间距。宽带紫外辐射的波长为约200至约1200nm。举例而言，Fusion H UV光源提供约200至400nm的UV波长；且Excimer UV源提供约172nm的UV波长。
亦确知，可经由在沉积工艺期间在工艺气体中提供最佳范围的稀释气体含量来增强紫外暴露的效应。此经进行以减少经沉积的材料中氮-氢键的数目，该等氮-氢键通常比硅-氢键更难以藉紫外处理移除。因此，在一实施例中，在略微不同的工艺条件下沉积随后经受紫外暴露的氮化硅层26，其中稀释气流经减少至约5000至约15,000sccm的范围中且更佳为约10,000sccm。硅烷及氨体积流动比率及流速为约1∶2至约1∶15，且更佳为约1∶10。
电子束暴露
氮化硅材料亦可经由暴露于暴露腔室106中的电子束来处理。包含电子束源的暴露源108可包含(例如)在经沉积的材料上扫描的直线电子源、或甚至较大面积的电子束暴露系统(诸如，授予Livesay的美国专利第5,003,178号中所描述，其全文以引用的方式并入本文中)。在一版本中，用覆盖约4平方时至约256平方时的面积的电子束来进行电子束暴露。电子束暴露条件包括所施加的总剂量、施加至经沉积的材料的电子束能量及电子束电流密度。
在一版本中，在约10-5至约10-2托的真空中执行电子束暴露，且其中基板温度介于约100℃至约400℃的范围中。暴露能量可介于约0.1至约100keV的范围中，且电子束电流通常为约1至约100mA。电子束剂量属于约1至约100,000μC/cm2的范围中。所选剂量及能量将与待处理的经沉积材料的厚度成比例。通常，电子束暴露将为约0.5分钟至约10分钟。在一预期实例中，可以4KV、6mA的电流、在400℃的基板温度下执行电子束处理以提供200至1500的剂量。
氮化硅的沉积及电子束处理亦可在一丛集平台工具中进行，该丛集平台工具具有CVD腔室、电子束照射腔室及用于将基板自CVD腔室移送至电子束(e-beam)腔室的机器人。CVD及电子束腔室中的处理以及移送操作在真空条件中进行。
等离子体处理
氮化硅层26亦可经等离子体处理以增加电荷保持时间。在等离子体处理的一方法中，经由将第一工艺气体引入含有基板的工艺区中来将一或多个氮化硅层沉积于CVD工艺腔室中，该工艺气体包含含硅组份及含氮组份。举例而言，经由将功率电导性或电容性地耦合至第一工艺气体来由该工艺气体产生等离子体。经激发的工艺气体将氮化硅层沉积于基板上。
经沉积的层经由停止或改变第一工艺气体的流动以将第二工艺气体引入工艺区中来进行等离子体处理。第二工艺气体包含惰性或不反应气体(其可为第一工艺气体的组份或一不同气体)。第二工艺气体经由将功率电导性或电容性地耦合至工艺气体来加以激发以产生等离子体。经激发的等离子体处理经沉积的氮化硅层以增加层的电荷保持时间。
进一步可相信，经由用氮等离子体处理循环来处理经沉积的氮化硅膜，可将电荷陷阱层的电位能量井制造得更深。氮等离子体处理可经由将氮化硅沉积工艺改为两个工艺循环来执行。第一循环用以使用包含第一组份(包含含硅的气体及含氮的气体)及第二组份(包含稀释氮气)的第一工艺气体来将氮化硅层沉积于基板上，且形成等离子体。在第二氮等离子体处理循环中，关闭包括含硅气体及含氮气体的工艺气体的第一组份的流动，仅提供包含稀释氮气的第二组份的流动。两个循环中皆可将高频电压供应至电极44a、b以形成等离子体。在氮化硅材料的沉积期间，将该等工艺循环重复若干次。
在不受建议解释限制的情况下，可相信氮等离子体循环经由移除硅-氢键可减少氮化硅层26中的氢含量且促进硅-氮键的形成。然而，由于氮等离子体处理仅可影响经沉积的氮化硅膜的一薄表面区域，故在基板上仅沉积了一薄氮化硅膜的短暂沉积工艺循环之后执行氮处理循环。初始膜的厚度足够薄以允许氮等离子体处理，而能实质穿透经沉积的材料的整个厚度。若在沉积氮化硅膜26的整个厚度之后执行氮等离子体处理，则经沉积材料仅有一薄表面区域可得到适当处理。
因此，等离子体处理工艺在等离子体处理循环后包含足够数目的沉积循环以达成所要的膜厚度。举例而言，包含二十(20)个工艺循环(每一循环包含第一沉积循环及第二氮等离子体处理循环)的沉积工艺可用以沉积及等离子体处理氮化硅材料至500埃的厚度。每一沉积循环执行约2至约10秒且更通常而言约5秒；且每一氮等离子体处理循环执行约10至约30秒且更通常而言约20秒。
若干沉积工艺参数可经调整以改良经沉积及等离子体处理的氮化硅层26的电荷保持时间。举例而言，较高温度的沉积据信可在约400至约500℃基板温度下改良氮悬键的数目。另外，可经由将高射频电压施加至电极44a并将第二电极44b接地来形成等离子体，其中该高射频为约3MHz至约60MHz(诸如13.56MHz的频率)。与热启动的CVD工艺相比，由等离子体启动的CVD反应将允许使用相对较低的基板温度。又，应在约20至约100瓦特及少于约200瓦特的相对低的功率位准下施加高RF电压。
亦可使施加至腔室40的电极44a、b的射频电压经脉冲以产生脉冲等离子体。据信，脉冲等离子体可提供经沉积的材料的较均匀厚度。经由将射频电压的电压脉冲施加至定界工艺区的电极来产生脉冲等离子体。电压脉冲各具有一工作循环，其为脉冲持续时间(T1)与脉冲周期(T2)的比率。在脉冲波形中，脉冲持续时间为(a)在第一跳变期间脉冲振幅达到其最终振幅的一特定分率(位准)的时间与(b)在最后转变中脉冲振幅下降至相同位准的时间之间的时间间隔。通常，最终振幅的50％点之间的时间间隔用以判定或界定脉冲持续时间。较佳地，电压脉冲为矩形脉冲，但是其亦可具有其它形状，诸如正方形或正弦波脉冲。在约100至约500瓦特的功率位准下提供脉冲RF功率。所选功率位准为相对高，因为据信在高功率位准下，SiH4及NH3将更完全分离且因此减少经沉积膜的总体氢含量。
电压脉冲的工作循环亦可经选择以控制经沉积的氮化硅层26的电荷保持性质。不同脉冲类型、射频位准、瓦特数及比率T2/T1可经选择以提供所要性质。发现减少脉冲持续时间(T1)及/或增加脉冲周期(T2)的较小工作循环可提供较佳电荷保持。较佳地，工作循环小于约60％。工作循环范围较佳为约10％至约50％，且更佳为约20％。对于此等工作循环而言，脉冲频率介于10至1000Hz的范围中。在一较佳实施例中，对于50Hz的脉冲串而言工作循环为20％(例如0.25)，其中脉冲持续时间为4ms(例如1μs)且脉冲周期为20ms(例如4μs)。在脉冲等离子体工艺中，在约100至约1000瓦特的功率位准下于电极44a、b上施加具有约3MHz至约60MHz的范围的频率的高RF电压。适合的工艺气体包含在本文所述的流率范围内的硅烷、氨、氮及可选的氩。
如本文提供的示范性工艺中所述的包含沉积于腔室40中的氮化硅层26的闪存装置具有较高电荷保持时间，且相信此由氮悬键的较高浓度所导致。
尽管展示且描述了本发明的示范性实施例，但是熟习此项技术者可设计出并入本发明且亦在本发明的范畴内的其它实施例。另外，术语下方、上方、底部、顶部、上、下、第一及第二以及其它相对或位置术语参照图中的示范性实施例展示且可互换。因此，随附的权利要求书不应限于本文为说明本发明所描述的较佳版本、材料或空间排列的描述。

Claims (20)

1.一种形成一闪存装置的方法，该方法包含以下步骤：
(a)在一基板上形成一二氧化硅(silicon dioxide)层；
(b)在该二氧化硅层上形成一掺杂氮化硅层，该掺杂氮化硅层包含一掺杂剂，其包含碳、硼或氧；
(c)将一介电材料沉积于该掺杂氮化硅层上；及
(d)将一导电栅极沉积于该介电材料上。
2.如权利要求1所述的方法，其中(b)步骤包含以以下各掺杂剂所形成的一掺杂氮化硅层的步骤：
(i)相对于该未掺杂氮化硅层而言以一足够高的百分比来增加该氮化硅层的电荷保持时间；
(ii)以相对于未掺杂氮化硅层而言以一足够高的百分比将该氮化硅层的该电荷保持时间增加至少约1％；及
(iii)以一约1％至约50％的百分比。
3.如权利要求1所述的方法，其中(b)步骤包含以下步骤：
(i)沉积一氮化硅层；
(ii)将该氮化硅层暴露于一工艺气体，其包含含碳物质、含硼物质或含氧物质中至少一者；及
(iii)激发该工艺气体以形成一等离子体以用包含碳、硼或氧的一掺杂剂来掺杂该经沉积的氮化硅层。
4.如权利要求3所述的方法，其中该工艺气体包含SiH4、NH3及N2。
5.如权利要求1所述的方法，其中(b)步骤包含以下步骤：
(i)沉积一氮化硅层；
(ii)将该氮化硅层暴露于一工艺气体，其包含碳、硼或氧中至少一者；及
(iii)加热该基板以用包含碳、硼或氧的一掺杂剂来掺杂该经沉积的氮化硅层。
6.如权利要求1所述的方法，其包含以下特征中至少一者：
(i)该介电材料包含一高k介电质或氧化铝；及
(ii)该导电栅极包含钛或钽。
7.一种闪存装置，其包含：
(a)一基板，其包含硅；
(b)一二氧化硅(silicon dioxide)层，其在该基板上；
(c)一掺杂氮化硅层，其在该二氧化硅层上，该掺杂氮化硅层包含一掺杂剂，其包含碳、硼或氧；
(d)一介电材料，其在该掺杂氮化硅层上；及
(e)一导电栅极，其在该介电材料上。
8.一种形成一闪存装置的方法，该方法包含以下步骤：
(a)在一基板上形成一二氧化硅(silicon dioxide)层；
(b)在该二氧化硅层上形成一氮化硅层，该氮化硅层包含硅氮比沿该层厚度变化的一成分梯度；
(c)将一介电材料沉积于该氮化硅层上；及
(d)将一导电栅极沉积于该介电材料上。
9.如权利要求1所述的方法，其中(b)步骤包含形成包含以下至少一者的一成分梯度的步骤：
(i)沿该厚度变化的量足够高以相对于未掺杂氮化硅层而言增加该氮化硅层的电荷保持时间的一硅氮比；
(ii)沿该厚度变化至少约1％的一硅氮比；
(iii)沿该厚度变化约0.4至约1.2的一硅氮比。
10.如权利要求8所述的方法，其中(b)步骤包含以下步骤：
(i)经由将一工艺气体引入该工艺区中来沉积具有一第一硅氮比的氮化硅，该工艺气体包含一含硅组份与一含氮组份，且经由将一第一功率位准的能量施加至该工艺区周围的电极在该工艺区中产生该工艺气体的一等离子体；及
(ii)经由将一第二功率位准的能量施加至该工艺区周围的该等电极来沉积具有一第二硅氮比的氮化硅，
其中该第一功率位准比该第二功率位准高至少约200W。
11.如权利要求8所述的方法，其中(b)步骤包含以下步骤：
(i)经由维持进入该工艺区中的一工艺气体的一第一压力来沉积具有一第一硅氮比的氮化硅，该工艺气体包含一含硅组份及一含氮组份，且在该工艺区中产生该工艺气体的一等离子体；及
(ii)经由维持该工艺区中的该工艺气体的一第二压力来沉积具有一第二硅氮比的氮化硅，
其中该第一压力比该第二压力高至少约0.1托。
12.如权利要求8所述的方法，其中(b)步骤包含以下步骤：
(i)经由将一第一工艺气体引入该工艺区中来沉积具有一第一硅氮比的氮化硅，该第一工艺气体包含含硅组份与含氮组份的一第一比率，且在该工艺区中产生该工艺气体的一等离子体；及
(ii)经由将一第二工艺气体引入该工艺区中来沉积具有一第二硅氮比的氮化硅，该第二工艺气体包含含硅组份与含氮组份的一第二比率，且在该工艺区中产生该工艺气体的一等离子体。
13.一种闪存装置，其包含：
(a)一基板，其包含硅；
(b)一二氧化硅(silicon dioxide)层，其在该基板上；
(c)一氮化硅层，其在该二氧化硅层上，该氮化硅层包含硅氮比沿该层厚度变化的一成分梯度；
(d)一介电材料，其在该氮化硅层上；及
(e)一导电栅极，其在该介电材料上。
14.一种形成一闪存装置的方法，该方法包含以下步骤：
(a)在一基板上形成一二氧化硅(silicon dioxide)层；
(b)在该二氧化硅层上形成一氮化硅层；
(c)将该氮化硅层暴露于具有波长约150nm至约1200nm的一紫外辐射；
(d)将一介电材料沉积于该氮化硅层上；及
(e)将一导电栅极沉积于该介电材料上。
15.一种根据权利要求14所述的方法制造的装置，其中该氮化硅层包含贯穿其的一氢浓度梯度。
16.一种形成一闪存装置的方法，该方法包含以下步骤：
(a)在一基板上形成一二氧化硅(silicon dioxide)层；
(b)在该二氧化硅层上形成一氮化硅层；
(c)将该氮化硅层暴露于一电子束；
(d)将一介电材料沉积于该氮化硅层上；及
(e)将一导电栅极沉积于该介电材料上。
17.一种根据权利要求16所述的方法制造的装置，其中该氮化硅层包含贯穿其的一氢浓度梯度。
18.一种形成一闪存装置的方法，该方法包含以下步骤：
(a)在一基板上形成二氧化硅层；
(b)经由以下步骤在该二氧化硅层上形成一经等离子体处理的氮化硅层：
(1)将该基板置放于一工艺区中；
(2)经由以下步骤将一氮化硅层沉积于该基板上：(i)将一第一工艺气体引入该工艺区，该第一工艺气体包含一含硅组份及一含氮组份，及在该工艺区中产生该第一工艺气体的一等离子体；及
(3)经由以下步骤形成一经等离子体处理的氮化硅层：(i)停止或改变该第一工艺气体的流动以将一第二工艺气体提供至该工艺区中，该第二工艺气体包含一惰性或不反应的气体，及(ii)在该工艺区中产生该第二工艺气体的一等离子体以处理该经沉积的氮化硅层；
(c)将一介电材料沉积于该氮化硅层上；及
(d)将一导电栅极沉积于该介电材料上。
19.如权利要求18所述的方法，其中对数个工艺循环重复(b)的(2)及(3)步骤。
20.如权利要求18所述的方法，其中该含硅的气体包含硅烷且该含氮的气体包含氨。
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CN108417481B (zh) * 2018-03-22 2021-02-23 京东方科技集团股份有限公司 氮化硅介电层的处理方法、薄膜晶体管和显示装置

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US20100096688A1 (en) 2010-04-22
CN103280446A (zh) 2013-09-04
KR101553554B1 (ko) 2015-09-17
US20100096687A1 (en) 2010-04-22
US8252653B2 (en) 2012-08-28
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