CN102142398B - 制造半导体器件的方法 - Google Patents

制造半导体器件的方法 Download PDF

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Publication number
CN102142398B
CN102142398B CN201110002450.0A CN201110002450A CN102142398B CN 102142398 B CN102142398 B CN 102142398B CN 201110002450 A CN201110002450 A CN 201110002450A CN 102142398 B CN102142398 B CN 102142398B
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semiconductor chip
chip
bonding
wire
semiconductor
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CN102142398A (zh
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武藤修康
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Renesas Electronics Corp
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Renesas Electronics Corp
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    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
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    • H10P72/7412—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H10P72/7414—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support the auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support
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    • H10W72/07531—Techniques
    • H10W72/07532—Compression bonding, e.g. thermocompression bonding
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  • Wire Bonding (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
CN201110002450.0A 2010-01-08 2011-01-07 制造半导体器件的方法 Active CN102142398B (zh)

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JP2010-002957 2010-01-08
JP2010002957A JP5512292B2 (ja) 2010-01-08 2010-01-08 半導体装置の製造方法

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WO2012057823A2 (en) * 2010-10-27 2012-05-03 The Regents Of The University Of California, Santa Cruz Methods for scribing of semiconductor devices with improved sidewall passivation
KR20120055717A (ko) * 2009-09-08 2012-05-31 스미토모 베이클리트 컴퍼니 리미티드 반도체 장치
JP5667381B2 (ja) * 2010-06-01 2015-02-12 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置及びその製造方法
KR20130042267A (ko) * 2011-10-18 2013-04-26 삼성전자주식회사 반도체 패키지 및 이를 제조하는 방법
WO2014083805A1 (ja) * 2012-11-28 2014-06-05 パナソニック株式会社 半導体装置およびワイヤボンディング配線方法
CN103943535B (zh) * 2013-01-22 2018-05-11 晶元光电股份有限公司 半导体元件翻转装置
JP2014167973A (ja) * 2013-02-28 2014-09-11 Toshiba Corp 半導体装置およびその製造方法
KR20140109134A (ko) * 2013-03-05 2014-09-15 삼성전자주식회사 멀티-채널을 갖는 반도체 패키지 및 관련된 전자 장치
JP6408394B2 (ja) * 2015-02-06 2018-10-17 株式会社ジェイデバイス 半導体装置、半導体装置の製造方法、及び製造装置
CN106816412B (zh) * 2017-01-19 2019-05-24 吉林麦吉柯半导体有限公司 晶圆的切割工艺及晶圆的生产方法
US10181456B2 (en) * 2017-03-16 2019-01-15 Intel Corporation Multi-package integrated circuit assembly with package on package interconnects
CN109755182A (zh) * 2017-11-07 2019-05-14 中芯国际集成电路制造(上海)有限公司 芯片堆叠封装结构及其形成方法
JP2019165046A (ja) * 2018-03-19 2019-09-26 東芝メモリ株式会社 半導体装置およびその製造方法
CN110391218A (zh) 2018-04-23 2019-10-29 晟碟半导体（上海）有限公司 具有裸芯翘起控制的半导体装置
CN110660809B (zh) * 2018-06-28 2023-06-16 西部数据技术公司 包含分支存储器裸芯模块的垂直互连的半导体装置
CN110444528B (zh) * 2018-05-04 2021-04-20 晟碟信息科技（上海）有限公司 包含虚设下拉式引线键合体的半导体装置
CN112018093B (zh) 2019-05-31 2025-03-28 桑迪士克科技股份有限公司 具有定位成减少模片开裂的顶部模片的半导体器件
CN110692135B (zh) * 2019-06-14 2021-03-19 深圳市汇顶科技股份有限公司 芯片封装结构和电子设备
JP7302658B2 (ja) * 2019-06-18 2023-07-04 株式会社ソシオネクスト 半導体装置
JP1686546S (https=) * 2020-05-13 2021-05-31
KR20220015066A (ko) * 2020-07-30 2022-02-08 삼성전자주식회사 멀티-칩 패키지
CN116093037B (zh) * 2023-01-03 2025-10-03 长鑫存储技术有限公司 一种封装结构及其形成方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1383215A (zh) * 2001-03-21 2002-12-04 佳能株式会社 半导体器件及其制造方法
US20070035002A1 (en) * 2005-07-11 2007-02-15 Renesas Technology Corp. Semiconductor device and a manufacturing method of the same
US20070170573A1 (en) * 2006-01-20 2007-07-26 Kuroda Soshi Semiconductor device, interposer chip and manufacturing method of semiconductor device
US20090108470A1 (en) * 2007-10-29 2009-04-30 Kabushiki Kaisha Toshiba Semiconductor device

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5689135A (en) * 1995-12-19 1997-11-18 Micron Technology, Inc. Multi-chip device and method of fabrication employing leads over and under processes
JP4034073B2 (ja) * 2001-05-11 2008-01-16 株式会社ルネサステクノロジ 半導体装置の製造方法
JP2003243435A (ja) * 2002-02-14 2003-08-29 Hitachi Ltd 半導体集積回路装置の製造方法
US20060267173A1 (en) * 2005-05-26 2006-11-30 Sandisk Corporation Integrated circuit package having stacked integrated circuits and method therefor
CN100543982C (zh) * 2006-11-01 2009-09-23 南茂科技股份有限公司 具有非对称式导线架的多芯片堆叠封装结构
US8723332B2 (en) * 2007-06-11 2014-05-13 Invensas Corporation Electrically interconnected stacked die assemblies
CN101364593B (zh) * 2007-08-09 2011-03-23 南茂科技股份有限公司 导线架中具有多段式汇流条的交错偏移堆叠封装结构
JP4498403B2 (ja) * 2007-09-28 2010-07-07 株式会社東芝 半導体装置と半導体記憶装置
JP5178213B2 (ja) 2008-01-23 2013-04-10 株式会社東芝 積層型半導体装置と半導体記憶装置
US8004071B2 (en) 2007-12-27 2011-08-23 Kabushiki Kaisha Toshiba Semiconductor memory device
JP5150243B2 (ja) 2007-12-27 2013-02-20 株式会社東芝 半導体記憶装置
CN101615587A (zh) * 2008-06-27 2009-12-30 桑迪士克股份有限公司 半导体装置中的导线层叠式缝线接合
JP4776675B2 (ja) * 2008-10-31 2011-09-21 株式会社東芝 半導体メモリカード
JP5579982B2 (ja) * 2008-12-15 2014-08-27 ピーエスフォー ルクスコ エスエイアールエル 半導体装置の中間構造体及び中間構造体の製造方法
US20100193930A1 (en) * 2009-02-02 2010-08-05 Samsung Electronics Co., Ltd. Multi-chip semiconductor devices having conductive vias and methods of forming the same
KR20100109243A (ko) * 2009-03-31 2010-10-08 삼성전자주식회사 반도체 패키지
JP2010287592A (ja) * 2009-06-09 2010-12-24 Renesas Electronics Corp 半導体装置、半導体ウェハおよびその製造方法
KR20100134354A (ko) * 2009-06-15 2010-12-23 삼성전자주식회사 반도체 패키지, 스택 모듈, 카드 및 전자 시스템
CN102473697B (zh) * 2009-06-26 2016-08-10 伊文萨思公司 曲折配置的堆叠裸片的电互连
WO2011056668A2 (en) * 2009-10-27 2011-05-12 Vertical Circuits, Inc. Selective die electrical insulation additive process
KR101676620B1 (ko) * 2010-02-05 2016-11-16 에스케이하이닉스 주식회사 적층 반도체 패키지
KR101686553B1 (ko) * 2010-07-12 2016-12-14 삼성전자 주식회사 반도체 패키지 및 패키지 온 패키지

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1383215A (zh) * 2001-03-21 2002-12-04 佳能株式会社 半导体器件及其制造方法
US20070035002A1 (en) * 2005-07-11 2007-02-15 Renesas Technology Corp. Semiconductor device and a manufacturing method of the same
US20070170573A1 (en) * 2006-01-20 2007-07-26 Kuroda Soshi Semiconductor device, interposer chip and manufacturing method of semiconductor device
US20090108470A1 (en) * 2007-10-29 2009-04-30 Kabushiki Kaisha Toshiba Semiconductor device

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