CN101515554B - 半导体器件的制造方法、半导体器件以及配线基板 - Google Patents
半导体器件的制造方法、半导体器件以及配线基板 Download PDFInfo
- Publication number
- CN101515554B CN101515554B CN2009100069877A CN200910006987A CN101515554B CN 101515554 B CN101515554 B CN 101515554B CN 2009100069877 A CN2009100069877 A CN 2009100069877A CN 200910006987 A CN200910006987 A CN 200910006987A CN 101515554 B CN101515554 B CN 101515554B
- Authority
- CN
- China
- Prior art keywords
- semiconductor device
- semiconductor chip
- modification
- terminal electrode
- metal film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
- H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/099—Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/65—Shapes or dispositions of interconnections
- H10W70/654—Top-view layouts
- H10W70/655—Fan-out layouts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/0198—Manufacture or treatment batch processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/241—Dispositions, e.g. layouts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/29—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
- H10W72/9413—Dispositions of bond pads on encapsulations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008036235A JP5224845B2 (ja) | 2008-02-18 | 2008-02-18 | 半導体装置の製造方法及び半導体装置 |
| JP2008-036235 | 2008-02-18 | ||
| JP2008036235 | 2008-02-18 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101515554A CN101515554A (zh) | 2009-08-26 |
| CN101515554B true CN101515554B (zh) | 2012-11-07 |
Family
ID=40954338
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009100069877A Active CN101515554B (zh) | 2008-02-18 | 2009-02-18 | 半导体器件的制造方法、半导体器件以及配线基板 |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US8217509B2 (https=) |
| JP (1) | JP5224845B2 (https=) |
| KR (1) | KR101602958B1 (https=) |
| CN (1) | CN101515554B (https=) |
| TW (1) | TWI497617B (https=) |
Families Citing this family (31)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5355363B2 (ja) * | 2009-11-30 | 2013-11-27 | 新光電気工業株式会社 | 半導体装置内蔵基板及びその製造方法 |
| KR101141209B1 (ko) * | 2010-02-01 | 2012-05-04 | 삼성전기주식회사 | 단층 인쇄회로기판 및 그 제조방법 |
| US8319318B2 (en) * | 2010-04-06 | 2012-11-27 | Intel Corporation | Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages |
| US8618652B2 (en) | 2010-04-16 | 2013-12-31 | Intel Corporation | Forming functionalized carrier structures with coreless packages |
| JP2012146963A (ja) * | 2010-12-20 | 2012-08-02 | Shinko Electric Ind Co Ltd | 半導体パッケージの製造方法及び半導体パッケージ |
| JP2013114415A (ja) | 2011-11-28 | 2013-06-10 | Elpida Memory Inc | メモリモジュール |
| KR101333893B1 (ko) * | 2012-01-03 | 2013-11-27 | 주식회사 네패스 | 반도체 패키지 및 그 제조 방법 |
| TWI515841B (zh) * | 2013-08-02 | 2016-01-01 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
| TWI582913B (zh) * | 2013-08-02 | 2017-05-11 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
| US20150035163A1 (en) * | 2013-08-02 | 2015-02-05 | Siliconware Precision Industries Co., Ltd. | Semiconductor package and method of fabricating the same |
| EP3075006A1 (de) | 2013-11-27 | 2016-10-05 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Leiterplattenstruktur |
| AT515101B1 (de) | 2013-12-12 | 2015-06-15 | Austria Tech & System Tech | Verfahren zum Einbetten einer Komponente in eine Leiterplatte |
| US11523520B2 (en) | 2014-02-27 | 2022-12-06 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Method for making contact with a component embedded in a printed circuit board |
| TWI557853B (zh) * | 2014-11-12 | 2016-11-11 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
| WO2016084768A1 (ja) * | 2014-11-27 | 2016-06-02 | 国立研究開発法人産業技術総合研究所 | 表面実装型パッケージおよびその製造方法 |
| US9659863B2 (en) | 2014-12-01 | 2017-05-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices, multi-die packages, and methods of manufacture thereof |
| JP6511695B2 (ja) * | 2015-01-20 | 2019-05-15 | ローム株式会社 | 半導体装置およびその製造方法 |
| US10083888B2 (en) * | 2015-11-19 | 2018-09-25 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package |
| US10115668B2 (en) | 2015-12-15 | 2018-10-30 | Intel IP Corporation | Semiconductor package having a variable redistribution layer thickness |
| JP6669586B2 (ja) | 2016-05-26 | 2020-03-18 | 新光電気工業株式会社 | 半導体装置、半導体装置の製造方法 |
| JP6716363B2 (ja) * | 2016-06-28 | 2020-07-01 | 株式会社アムコー・テクノロジー・ジャパン | 半導体パッケージ及びその製造方法 |
| JP6971052B2 (ja) * | 2017-04-20 | 2021-11-24 | 京セラ株式会社 | 半導体装置の製造方法および半導体装置 |
| KR102185706B1 (ko) * | 2017-11-08 | 2020-12-02 | 삼성전자주식회사 | 팬-아웃 반도체 패키지 |
| US10643919B2 (en) | 2017-11-08 | 2020-05-05 | Samsung Electronics Co., Ltd. | Fan-out semiconductor package |
| TWI649795B (zh) * | 2018-02-13 | 2019-02-01 | 友達光電股份有限公司 | 顯示面板 |
| JP6921794B2 (ja) * | 2018-09-14 | 2021-08-18 | 株式会社東芝 | 半導体装置 |
| JP2019208045A (ja) * | 2019-07-17 | 2019-12-05 | 太陽誘電株式会社 | 回路基板 |
| JP2020141152A (ja) * | 2020-06-10 | 2020-09-03 | 株式会社アムコー・テクノロジー・ジャパン | 半導体アセンブリおよび半導体アセンブリの製造方法 |
| TWI808618B (zh) * | 2022-01-20 | 2023-07-11 | 大陸商廣東則成科技有限公司 | 用於嵌入式晶片的封裝製程 |
| KR102907829B1 (ko) * | 2023-02-09 | 2026-01-07 | 하나 마이크론(주) | 팬아웃 반도체 패키지 및 이의 제조방법 |
| CN116721978A (zh) * | 2023-06-29 | 2023-09-08 | 上海纳矽微电子有限公司 | 一种半导体封装结构及其制造方法 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6271469B1 (en) * | 1999-11-12 | 2001-08-07 | Intel Corporation | Direct build-up layer on an encapsulated die package |
| US6309912B1 (en) * | 2000-06-20 | 2001-10-30 | Motorola, Inc. | Method of interconnecting an embedded integrated circuit |
| CN1650410A (zh) * | 2002-04-29 | 2005-08-03 | 先进互联技术有限公司 | 部分构图的引线框架及其制造方法以及在半导体封装中的使用 |
| CN1716587A (zh) * | 2004-06-30 | 2006-01-04 | 新光电气工业株式会社 | 内插器及其制造方法以及使用该内插器的半导体器件 |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6274391B1 (en) * | 1992-10-26 | 2001-08-14 | Texas Instruments Incorporated | HDI land grid array packaged device having electrical and optical interconnects |
| JPH08240904A (ja) * | 1995-03-01 | 1996-09-17 | Hoya Corp | 転写マスクおよびその製造方法 |
| DE19546443A1 (de) * | 1995-12-13 | 1997-06-19 | Deutsche Telekom Ag | Optische und/oder elektrooptische Verbindung und Verfahren zur Herstellung einer solchen |
| US6350706B1 (en) * | 1998-09-03 | 2002-02-26 | Micron Technology, Inc. | Process for using photo-definable layers in the manufacture of semiconductor devices and resulting structures of same |
| WO2001000508A1 (en) * | 1999-06-25 | 2001-01-04 | Toyo Kohan Co., Ltd. | Semiconductor package clad material and semiconductor package using the same |
| JP3277997B2 (ja) * | 1999-06-29 | 2002-04-22 | 日本電気株式会社 | ボールグリッドアレイパッケージとその製造方法 |
| JP2001217359A (ja) * | 2000-01-31 | 2001-08-10 | Shinko Electric Ind Co Ltd | 放熱用フィン及びその製造方法並びに半導体装置 |
| JP2002016173A (ja) * | 2000-06-30 | 2002-01-18 | Mitsubishi Electric Corp | 半導体装置 |
| JP4243922B2 (ja) | 2001-06-26 | 2009-03-25 | イビデン株式会社 | 多層プリント配線板 |
| TW557521B (en) * | 2002-01-16 | 2003-10-11 | Via Tech Inc | Integrated circuit package and its manufacturing process |
| US6680529B2 (en) * | 2002-02-15 | 2004-01-20 | Advanced Semiconductor Engineering, Inc. | Semiconductor build-up package |
| JP2005203390A (ja) * | 2004-01-13 | 2005-07-28 | Seiko Instruments Inc | 樹脂封止型半導体装置の製造方法 |
| JP4445351B2 (ja) * | 2004-08-31 | 2010-04-07 | 株式会社東芝 | 半導体モジュール |
| TWI299248B (en) * | 2004-09-09 | 2008-07-21 | Phoenix Prec Technology Corp | Method for fabricating conductive bumps of a circuit board |
-
2008
- 2008-02-18 JP JP2008036235A patent/JP5224845B2/ja active Active
-
2009
- 2009-02-17 KR KR1020090013080A patent/KR101602958B1/ko active Active
- 2009-02-17 US US12/372,198 patent/US8217509B2/en active Active
- 2009-02-18 TW TW098105083A patent/TWI497617B/zh active
- 2009-02-18 CN CN2009100069877A patent/CN101515554B/zh active Active
-
2011
- 2011-06-16 US US13/162,071 patent/US9048242B2/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6271469B1 (en) * | 1999-11-12 | 2001-08-07 | Intel Corporation | Direct build-up layer on an encapsulated die package |
| US6309912B1 (en) * | 2000-06-20 | 2001-10-30 | Motorola, Inc. | Method of interconnecting an embedded integrated circuit |
| CN1650410A (zh) * | 2002-04-29 | 2005-08-03 | 先进互联技术有限公司 | 部分构图的引线框架及其制造方法以及在半导体封装中的使用 |
| CN1716587A (zh) * | 2004-06-30 | 2006-01-04 | 新光电气工业株式会社 | 内插器及其制造方法以及使用该内插器的半导体器件 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP5224845B2 (ja) | 2013-07-03 |
| KR20090089267A (ko) | 2009-08-21 |
| CN101515554A (zh) | 2009-08-26 |
| US8217509B2 (en) | 2012-07-10 |
| TWI497617B (zh) | 2015-08-21 |
| KR101602958B1 (ko) | 2016-03-11 |
| US9048242B2 (en) | 2015-06-02 |
| TW200945461A (en) | 2009-11-01 |
| JP2009194322A (ja) | 2009-08-27 |
| US20110244631A1 (en) | 2011-10-06 |
| US20090206470A1 (en) | 2009-08-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101515554B (zh) | 半导体器件的制造方法、半导体器件以及配线基板 | |
| TWI650846B (zh) | 內建散熱座之散熱增益型面朝面半導體組體及製作方法 | |
| US7078788B2 (en) | Microelectronic substrates with integrated devices | |
| US5796164A (en) | Packaging and interconnect system for integrated circuits | |
| JP2000164765A (ja) | 電源及び接地ラップを具備したクロスト―クノイズ低減形の高密度信号介挿体、並びに、介挿体の製造方法 | |
| JP2010521818A (ja) | 半導体デバイスパッケージ化装置、パッケージ化された半導体部品、半導体デバイスパッケージ化装置の製造方法、及び半導体部品の製造方法 | |
| CN103270587A (zh) | 用于与上IC封装耦合以形成封装体叠层(PoP)组件的下IC封装结构以及包括这种下IC封装结构的PoP组件 | |
| JP2007535156A (ja) | 埋込み構成要素からの熱伝導 | |
| CN106409777A (zh) | 底部元件限制于介电材凹穴内的封装叠加半导体组件 | |
| JP2014531756A (ja) | 低cteインターポーザ | |
| JP4521251B2 (ja) | 配線性が高いマイクロビア基板 | |
| CN105789173B (zh) | 整合中介层及双布线结构的线路板及其制作方法 | |
| US10154594B2 (en) | Printed circuit board | |
| US6596620B2 (en) | BGA substrate via structure | |
| CN100524717C (zh) | 芯片内埋的模块化结构 | |
| CN111933532A (zh) | 扇出型封装工艺和扇出型封装结构 | |
| KR20100082551A (ko) | 인터포저 및 집적회로 칩 내장 인쇄회로기판 | |
| US20050258533A1 (en) | Semiconductor device mounting structure | |
| US7239024B2 (en) | Semiconductor package with recess for die | |
| CN103650652A (zh) | 印刷电路板及其制造方法 | |
| TWI614855B (zh) | 具有電磁屏蔽及散熱特性之半導體組體及製作方法 | |
| CN108109974B (zh) | 具有电磁屏蔽及散热特性的半导体组件及制作方法 | |
| TWI611530B (zh) | 具有散熱座之散熱增益型面朝面半導體組體及製作方法 | |
| CN107437537A (zh) | 层叠型基板及其制造方法 | |
| CN107958883A (zh) | 具有散热座的散热增益型面对面半导体组件及制作方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |