CN103270587A - 用于与上IC封装耦合以形成封装体叠层(PoP)组件的下IC封装结构以及包括这种下IC封装结构的PoP组件 - Google Patents

用于与上IC封装耦合以形成封装体叠层(PoP)组件的下IC封装结构以及包括这种下IC封装结构的PoP组件 Download PDF

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CN103270587A
CN103270587A CN201180060795XA CN201180060795A CN103270587A CN 103270587 A CN103270587 A CN 103270587A CN 201180060795X A CN201180060795X A CN 201180060795XA CN 201180060795 A CN201180060795 A CN 201180060795A CN 103270587 A CN103270587 A CN 103270587A
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encapsulation
substrate
sealant
tube core
interconnection
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CN103270587B (zh
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S·F·王
W·K·罗
K·E·翁
A·S·王
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Intel Corp
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Abstract

公开了用于封装体叠层(PoP)组件的下集成电路(IC)封装结构的实施例。下IC封装结构包括具有与上IC封装的端子配合的焊盘的插入体。将密封剂材料设置到下IC封装中,可以将这一密封剂设置为邻近一个或多个IC管芯。可以使上IC封装与下IC封装耦合以形成PoP组件。可以将这种PoP组件设置到主板或其他电路板上,或者其可以形成计算系统的部分。还描述了其他实施例,并要求对其进行保护。

Description

用于与上IC封装耦合以形成封装体叠层(PoP)组件的下IC封装结构以及包括这种下IC封装结构的PoP组件
技术领域
所公开的实施例总体上涉及集成电路器件,更具体而言,涉及集成电路封装的叠置。
背景技术
具有小形状因子的集成电路(IC)器件可以用于很多种类型的计算系统,例如,蜂窝电话、智能电话、平板电脑、电子阅读器件、笔记本电脑和膝上电脑以及其他手持或移动计算系统。一种用于实现小形状因子IC器件的解决方案是采用封装体叠层(PoP)架构,该架构大体包括叠置在下IC封装之上并与之电耦合的上IC封装。下IC封装可以包括设置在第一衬底或者其他管芯载体上的一个或多个IC管芯,也可能包括一个或多个额外部件。类似地,所述上IC封装可以包括设置在第二衬底上的一个或多个IC管芯(并且可能包括一个或多个其他部件)。在一些情况下,下IC封装可能是在一个制造设施处制造的,而上IC封装是在另一制造设施处制造的,之后需要将这两个IC封装机械及电气接合到一起。通过一个或多个互连将下IC封装电耦合到上IC封装,这些互连还可以提供这两个IC封装之间的机械耦合。
附图说明
图1A是示出了下IC封装结构的实施例的顶视图的示意图。
图1B是示出了沿图1A的B-B线截取的图1A的下IC封装的截面立视图的示意图。
图1C是示出了下IC封装结构的另一实施例的顶视图的示意图。
图1D是示出了下IC封装结构的另一实施例的截面立视图的示意图。
图1E是示出了下IC封装结构的另一实施例的截面立视图的示意图。
图1F是示出了下IC封装结构的另一实施例的截面立视图的示意图。
图1G是示出了下IC封装结构的另一实施例的截面立视图的示意图。
图1H是示出了下IC封装结构的另一实施例的截面立视图的示意图。
图1I是示出了下方IC封装结构的另一实施例的截面立视图的示意图。
图1J是示出了下IC封装结构的另一实施例的截面立视图的示意图。
图1K是示出了下IC封装结构的另一实施例的截面立视图的示意图。
图1L是示出了下IC封装结构的另一实施例的截面立视图的示意图。
图2A是示出了包括流动屏障的下IC封装的实施例的局部截面立视图的示意图。
图2B是示出了包括流动屏障的下IC封装的另一实施例的局部截面立视图的示意图。
图2C是示出了包括流动屏障的下IC封装的另一实施例的局部截面立视图的示意图。
图2D是示出了包括流动屏障的下IC封装的又一实施例的顶视图的示意图。
图2E是示出了包括流动屏障的下IC封装的又一实施例的顶视图的示意图。
图3是示出了封装体叠层(PoP)组件的实施例的截面立视图的示意图。
图4是示出了包括PoP组件的计算系统的实施例的截面立视图的示意图。
图5是示出了制造下IC封装结构以及封装体叠层组件的方法的实施例的方框图。
具体实施方式
公开了封装体叠层(PoP)组件的下集成电路(IC)封装结构的实施例。根据一些实施例,下IC封装结构包括插入体,其具有用于与上IC封装的配合端子耦合的焊盘。在其他实施例中,将密封剂材料设置到下IC封装内,可以将这一密封剂设置为邻近一个或多个IC管芯。在一些实施例中,可以使上IC封装与下IC封装耦合以形成PoP组件。在其他实施例中,将这样的PoP组件设置到主板或其他电路板上,或者其可以形成计算系统的一部分。还公开了制造上述下IC封装以及PoP组件的方法的实施例。
现在来看图1A和1B,其示出了下IC封装100的实施例。图1A中示出了下IC封装100的顶视图,而图1B中则示出了沿图1A的B-B线截取的截面立视图。可以使下IC封装100与上IC封装耦合以形成PoP组件,下文将更为详细地描述这样的PoP组件的实施例(例如,参考图3和所附文字)。
继续参考图1A和1B,下IC封装100包括具有第一面112和相对的第二面114的衬底110。将IC管芯120设置到衬底110的第一面112上,并使其通过若干互连125与衬底电耦合。插入体130也设置到该衬底的第一面112上,若干互连140将插入体130电耦合(也可能机械附着)到下层衬底110上。根据一个实施例,将密封剂材料150设置到IC封装100内,并使密封剂150邻近IC管芯120设置。在一个实施例中,可以在IC管芯120和衬底110之间设置一层底部填充材料160。此外,可以将多个导电端子170(例如,连接盘、焊料凸起、金属柱或台柱等)设置到衬底110的第二面114上,可以采用这些端子形成与诸如主板或其他电路板的下一级部件的电连接。
衬底110有时被称为“封装衬底”,其可以包括任何适当类型的能够在IC管芯120与IC封装100要耦合到的下一级部件(例如,电路板)之间提供电连通的衬底。在另一实施例中,衬底110可以包括任何适当类型的能够在IC管芯120与上IC封装之间提供电连通的衬底,所述上IC封装与下IC封装耦合,并且在另一实施例中,衬底110可以包括任何适当类型的能够在上IC封装与IC封装100要耦合到的下一级部件之间提供电连通的衬底。衬底110还可以为管芯120提供结构支撑。例如,在一个实施例中,衬底110包括围绕核心层(电介质核心或金属核心)构建的具有交错的电介质材料层和金属层的多层衬底。在另一实施例中,衬底110包括无核多层衬底。还发现可以将其他类型的衬底和衬底材料用于所公开的实施例(例如,陶瓷、蓝宝石、玻璃等)。此外,根据一个实施例,衬底110可以包括在管芯120本身之上构建的交错的电介质材料层和金属层,有时将这一过程称为“无凸起构建过程”。在利用这样的方案的情况下,可能不需要互连125(因为可以将所述构建层直接设置到管芯120之上)。
IC管芯120可以包括任何类型的集成电路器件。在一个实施例中,IC管芯120包括处理系统(单核或多核)。例如,所述IC管芯可以包括微处理器、图形处理器、信号处理器、网络处理器、芯片组等。在一个实施例中,IC管芯120包括芯片上系统(SoC),其具有多个功能单元(例如,一个或多个处理单元、一个或多个图形单元、一个或多个通信单元、一个或多个信号处理单元、一个或多个安全单元等)。然而,应当理解,所公开的实施例不受任何特定类型或种类的IC器件的限制。
IC管芯120包括正面122和相对的背面124。在一些实施例中,可以将所述正面122称为管芯的“有源表面”。若干互连125从管芯的正面122延伸到下层衬底110,这些互连125使管芯和衬底电耦合。互连125可以包括任何类型的能够在管芯120和衬底110之间提供电连通的结构和材料。根据一个实施例,互连125包括在管芯120和衬底110之间延伸的焊料凸起阵列(可能与设置在管芯120和/或衬底110上的铜柱和/或铜焊盘的阵列结合),可以利用焊料回流工艺形成互连125。当然,应当理解,很多其他类型的互连和材料都是可能的(例如,在管芯120和衬底110之间延伸的引线键合)。在一个实施例中,互连125将管芯120电耦合至衬底110,互连125还有助于将管芯机械固定到衬底上。在另一实施例中,在互连125周围以及在IC管芯120和衬底110之间设置一层底部填充材料160,这一底部填充层160还可以有助于将管芯120机械固定到衬底110上,下文将对此予以说明。底部填充材料160可以包括任何适当的材料,例如,液体或者预先涂覆的环氧化合物。
插入体130具有第一面132和相对的第二面134,其中第二面134面对衬底110的第一面112。在一个实施例中,如图1A-1B所示,插入体130包括具有开口或窗口136的框架形状。开口136可以包围IC管芯120的外围126;然而,在其他实施例中,开口136和管芯外围126可以不对准和/或可以非同心,管芯外围126的部分可以延伸到窗口136外。
应当理解,所公开的实施例不限于框架形插入体,此外所述插入体130可以具有任何适当的形状和构造。例如,在另一实施例中,如图1C所示,插入体130包括不具有开口的固体矩形板。根据一个实施例,图1C的固体矩形板插入体130包括用于插入密封剂150的小孔径138。
返回图1A和1B,多个导电端子180设置在插入体130的第一面132上。导电端子180中的每一个可以包括任何适当的结构和材料,其能够形成与上IC封装的配合端子的电连接,所述配合端子将与下IC封装100接合。在一个实施例中,端子180中的每一个包括适于与从上IC封装延伸的对应导电凸起配合的焊盘或连接盘,可以通过焊料回流工艺使这些配合结构接合。然而,应当理解,端子180可以包括任何类型的结构(例如,柱、凸起等)。此外,在一个实施例中,端子180中的一些端子与其他端子相比可以具有不同的尺寸和/或结构(例如,用于功率传输的端子可以不同于用于进行信号传输的端子等)。
如上文指出的,若干互连140在插入体的第二面134和衬底110的第一面112之间延伸,这些互连使插入体130与衬底110电耦合,由此使耦合至插入体的上IC封装与衬底110电耦合。互连140可以包括任何类型的能够在插入体130和衬底110之间提供电连通的结构和材料。根据一个实施例,互连140包括在插入体130和衬底110之间延伸的焊料凸起阵列(可能与设置在插入体130和/或衬底110上的铜柱和/或铜焊盘相结合),可以利用焊料回流工艺形成互连140。当然,应当理解,很多其他类型的互连和材料都是可能的。在一个实施例中,互连140还有助于将插入体130机械固定到衬底110上。在下文将更加详细地描述的另一实施例中,密封剂材料150可以延伸到插入体130和衬底110之间的缝隙190内,并且密封剂可以围绕一个或多个互连140的至少一部分延伸。因而,密封剂150还可以有助于将插入体130机械固定到衬底110上。
如前所述,将密封剂150设置到IC封装100内。密封剂150可以包括任何适当的材料或材料组合。在一个实施例中,密封剂材料包括液体环氧树脂,在另一实施例中,所述环氧树脂包括一种或多种填充材料,以改变环氧树脂的一个或多个特性(例如,固化温度、硬度、屈服强度、弹性模量、热膨胀系数等)。根据一个实施例,所述密封剂层增大下IC封装100的刚度,并且降低封装对翘曲的敏感性。例如,在下IC封装100的组装过程中,以及在与上IC封装的接合过程中,IC封装100可能受到多个高温循环(例如,在回流过程中,在环氧树脂固化过程中等),这种温度的循环变化可能导致翘曲(例如,由于管芯120和下层衬底110之间的差异热膨胀),这样的翘曲可能导致可靠性降低和/或结构损坏。密封剂150提供的提高的刚性可以缓解上述因翘曲诱发的损坏。
尽管文中称为密封剂,但是应当理解,可以采用替代术语称呼这一元件。例如,可以将密封剂称为模具、模制、包覆模压或顶部包封。
可以根据需要将密封剂150放置到下IC封装100中的任何一个或多个位置上,从而为封装组件提供预期的机械特性。根据一个实施例,如图1A和1B所示,将密封剂150设置到IC管芯120的背面124的至少一部分之上,在一些实施例中,所述密封剂基本上覆盖管芯背面124的全部(参考图1B)。在另一实施例中,还是如图1A和1B所示,密封剂150被设置到衬底110的第一面112的至少一部分之上。如果底部填充材料160被设置到IC管芯120和衬底110之间,那么密封剂150也可以与底部填充材料的一部分接触(参考图1B)。在一个实施例中,如图1B所示,密封剂延伸到管芯120的外围126之外,但是未延伸至衬底110上被互连140占据的区域。根据一个实施例,如图1B所示,密封剂150的形状在管芯的背面124之上基本上是平的,但是在管芯外围附近是圆化的。而且,在一个实施例中,如图1B所示,密封剂150不延伸到插入体130的正面132之上,但是在图1B的实施例中,密封剂延伸到插入体的第二面134之上并进入窗口136中。
应当理解,图1A和1B示出了下IC封装100和密封剂150的单个示范性实施例。然而,密封剂150和下IC封装100的很多其他构造也是可能的。例如,在其他实施例中,密封剂可以不延伸到窗口136中,并且可以位于插入体130的第二面134的下面。在另一实施例中,密封剂150可以延伸到插入体的第一面132之上。而且,密封剂可以具有任何其他适当的形状,此外在一些实施例中,密封剂可以延伸至衬底110的被互连140占据的区域。图1D到1L示出了具有密封剂150的替代构造以及额外特征的下IC封装150的额外实施例。
首先参考图1D,在一个实施例中,密封剂150延伸至插入体130的第一面132之上。而且,在图1D的实施例中,密封剂具有带圆角的矩形截面轮廓。参考图1E,在一个实施例中,密封剂150具有上部基本圆化的形状。在另一实施例中,如图1F所示,密封剂150具有在通过如图所示的截面观察时近似为正弦波轮廓的形状。在图1D、1E和1F的实施例中,密封剂基本上被设置到管芯的整个背面表面124上,并且还使之与底部填充材料160接触。而且,在图1D到1F的实施例中,密封剂150不延伸至设置互连140的位置。
现在转至图1G,在一个实施例中,密封剂延伸至插入体130和下层衬底110之间的缝隙190内。此外,密封剂150延伸至被互连140占据的区域内。在图1G的实施例中,密封剂基本上围绕互连140中的一个或多个互连。在另一实施例中,还是如图1G所示,密封剂充分填充缝隙190,并从衬底的第一表面112延伸至插入体的第二表面134。然而,在其他实施例中,密封剂可以被设置为邻近互连140,并与这些互连中的一个或多个接触,但是可以不充分填充缝隙190。在衬底110和插入体130之间的缝隙190内以及一个或多个互连140的周围放置密封剂150可以增强插入体130和衬底110之间的机械附着,以及提高电互连140的强度和可靠性。在图1G的实施例中,密封剂150的上部具有近似截棱锥的形状(例如,可以通过模制工艺实现这样的形状)。
在图1B到1G所示的实施例中,密封剂150被设置到管芯120的背面124之上。然而,在其他实施例中,可以使管芯的背面124露出。例如,如图1H所示,密封剂150接触管芯外围126的边缘,但是管芯120的背面124基本上没有密封剂。作为另一示例,如图1I所示,密封剂150可以延伸到缝隙190内以及一个或多个互连140周围,但是管芯背面124的至少一部分保持基本上无密封剂。在图1I的实施例中,密封剂可以延伸到管芯背面124之上并且延伸到这一表面的邻近管芯外围126的部分上,而管芯背面124的邻近管芯120的中心的其他部分则保持无密封剂。在一个实施例中,使管芯120的背面124的至少一部分露出可以有助于使冷却解决方案与管芯的背面124耦合,例如,所述冷却解决方案是热界面材料层、散热块、热扩散器等(图中未示出)。在另一实施例中,管芯背面124的露出部分可以有助于在管芯120的顶部叠置一个或多个额外管芯,在图1H和1I的每者中用虚线示出了这样的管芯121。可以通过任何适当的互连结构(例如,贯穿硅通孔或TSV、引线键合等)使管芯121与管芯120耦合。
在到现在为止描述的实施例中,通过若干互连125使管芯120与衬底110耦合。然而,在其他实施例中,可以利用替代结构和/或方法使管芯120与衬底110耦合。例如,如图1J所示,可以直接在管芯120之上构建形成衬底110的电介质和金属构建层,在这种情况下,可以直接在管芯120的正面122上形成电介质和随后的金属层,所述金属层与所述管芯上的一个或多个接合焊盘形成电接触。在这样的实施例中,分立的互连125可能是没有必要的,因为衬底内的金属化可以与管芯接合焊盘直接接触。可以利用前述技术的过程的例子包括无凸起构建层(BBUL)、管芯嵌入和晶片级封装。
在又一实施例中,可以利用引线键合使管芯120与衬底110电耦合。参考图1K,可以通过一条或多条接合线127使管芯120与衬底110电耦合,每一接合线在管芯正面122上的接合焊盘和衬底110的接合焊盘之间延伸。应注意,在图1K的实施例中,已经使管芯120发生了翻转,从而使管芯背面124处于与衬底110的第一面112相邻的位置,并且可以通过粘合剂(图中未示出)附着至衬底110。在图1K的实施例中,密封剂150在管芯122的正面之上延伸,并延伸至外围126,此外还延伸到了引线键合127之上。而且,在这一实施例中,密封剂150具有在管芯120上基本平坦的形状,但是所述密封剂在管芯外围126处以及引线键合127上是圆化的。
转至图1L,在另一实施例中,可以将两个或更多管芯按照层叠关系设置到衬底110上,可以采用引线键合在这些管芯中的每一个之间和/或与衬底110之间形成电连接。例如,如图1L所示,可以将三个管芯120a、120b、120c布置成层叠结构,并设置在衬底110的第一面112上。一个或多个引线键合127可以使管芯120a、120b、120c中的每一个电耦合至任何一个或多个其他管芯和/或与衬底110电耦合。在图1L的实施例中,密封剂150通过插入体130的窗口136延伸,并且延伸到插入体的第一表面132之上。此外,所述密封剂还延伸到插入体130和衬底110之间的缝隙190内以及一个或多个互连140周围。
如上所述,在一些实施例中,密封剂150可以不延伸到下IC封装100的设置互连140的区域内。根据一个实施例,希望防止密封剂流入到互连140所处的区域内(或者下IC封装100的任何其他区域内),因而可以利用一个或多个流动屏障或其他流动控制器件或结构控制密封剂150在IC封装100内的流动。可以利用任何适当的流动屏障或者屏障的组合来控制密封剂150的流动,例如,拦截堤(dams)、非浸润涂层和沟槽以及这些和/或其他特征件的任何适当组合。图2A到2E示出了流动屏障的各种示范性实施例。
参考图2A,在一个实施例中,拦截堤205a被设置到衬底110的第一表面112上。可以将拦截堤205a根据预期设置到下IC封装100的任何适当的位置上,以禁止密封剂150的流动。在图2A的实施例中,例如,拦截堤205a被设置到IC管芯120的外围126和该组互连140之间。因而,拦截堤205a将阻止密封剂150流入到IC封装100的被互连140占据的区域内。拦截堤205可以由任何适当的材料(例如,金属、聚合物、复合材料等)构造而成,并且可以通过任何适当的技术(例如,通过粘合剂、回流焊料、扩散接合等)接合至衬底110。在另一实施例中,使拦截堤205a与插入体130耦合而不是与衬底110耦合,在另一实施例中,使拦截堤205a与衬底110和插入体130二者耦合。根据另一实施例,将拦截堤205a与衬底110一体形成(或者替代地与插入体130一体形成)。
接下来参考图2B,在另一实施例中,将非浸润涂层或层205b设置到衬底的第一表面112上,其中,所述非浸润层包括相对于密封剂材料150非浸润的材料。可以根据预期将非浸润层205b设置到下IC封装100中的任何适当的位置(或多个位置)上,以阻止密封剂150的流动。在一个实施例中,将非浸润层205b设置到IC管芯120的外围126和互连140的阵列之间,因此,非浸润层205b将禁止密封剂150流入到IC封装100的被互连140占据的区域内。所述非浸润层205b可以包括任何适当的相对于密封剂材料150非浸润的材料或材料组合(例如,含氟聚合物等),其可以通过任何适当的技术(例如,通过利用掩模的旋涂、光刻法、利用针或注射器的配发等)将其设置到衬底110上。在另一实施例中,将所述非浸润层b设置到插入体130上而非衬底110上,在另一实施例中,将非浸润层205b设置到衬底110和插入体130中的每者上。
转至图2C,在另一实施例中,将沟槽205c设置到衬底110的第一表面112上。可以根据预期将沟槽205c设置到下IC封装100的任何适当位置(或多个位置)上,从而阻止密封剂150的流动。在图2C的实施例中,例如,将沟槽205c设置到IC管芯120的外围126和互连140组之间,因此,沟槽205c将阻止密封剂150流入IC封装100的被互连140占据的区域内。可以采用任何适当的技术(例如,通过蚀刻、机械加工、激光消融等)形成沟槽205c。在另一实施例中,将沟槽205c设置到插入体130上而不是衬底110上,在另一实施例中,在衬底110和插入体130中的每者上形成沟槽205c。
在一个实施例中,流动屏障或结构可以围绕管芯120的外围延伸或者通过管芯120和互连140之间的区域延伸。例如,在一个实施例中,如图2D所示,将屏障(例如,205a或205b或205c)设置到衬底110的第一表面112上,并且其在所述衬底第一表面112上处于管芯120和被互连140占据的区域145之间。根据一个实施例,流动屏障(205a或205b或205c)完全围绕管芯外围126延伸;然而,在其他实施例中,流动屏障可以是不连续的,在这一结构中可以存在一个或多个中断或空隙。例如,在一个实施例中,如图2E所示,流动屏障(例如,205a或205b或205c)可以包括多个单独的分立元件,它们一起阻止密封剂150的流动。在又一实施例中,流动屏障可以包括多个设置在衬底110(或插入体130)上的分立元件,这些分立元件可以包括无源电气器件(例如,电容器、电阻器、电感器或者这些和/或其他器件的任何组合)。
现在参考图3,其示出了封装体叠层(PoP)组件302的实施例。PoP组件302包括下IC封装100和上IC封装300。下IC封装100可以包括文中描述的下IC封装的实施例中的任何一个。根据一个实施例,下IC封装100包括一个或多个处理系统,上IC封装300包括一个或多个存储器件。在另一实施例中,下IC封装100包括一个或多个处理系统,上IC封装300包括无线通信系统(或者替代地包括通信系统的一个或多个部件)。在又一实施例中,下IC封装100包括一个或多个处理系统,上IC封装300包括图形处理系统。PoP组件302可以包括任何类型的计算系统的部分,例如,手持计算系统(例如,蜂窝电话、智能电话、音乐播放器等)、移动计算系统(例如,膝上型电脑、上网本、平板电脑等)、台式计算系统或服务器。在一个实施例中,PoP组件包括固态驱动器(SSD)。
上IC封装300可以包括任何适当的封装结构。在一个实施例中,如图3所示,上IC封装300包括设置在封装衬底310上的若干IC管芯320a、320b、320c。若干引线键合327使管芯320a、320b、320c中的每一个与一个或多个其他管芯和/或与衬底310电连接。可以将模制材料355设置到管芯320a-c以及衬底310之上。根据一个实施例,多个互连340将上IC封装300耦合至下IC封装100。在一个实施例中,使一组互连340与插入体130上的一组端子180耦合。
互连340中的每一个可以包括任何类型的能够在上下IC封装100、300之间提供电连通的结构和材料。根据一个实施例,互连340组包括在下IC封装100的插入体130上的接合焊盘180和上IC封装300的衬底310之间延伸的焊料凸起阵列(也可能与设置在衬底310上的柱和/或焊盘的阵列相结合)。可以利用焊料回流工艺形成多个互连340。当然,应当理解,很多其他类型的互连和材料都是可能的。在一个实施例中,互连340的阵列还有助于将上IC封装300机械固定到下IC封装100上。
在一个实施例中,如图3所示,在密封剂150的上表面和衬底310的下表面之间可以存在缝隙395。在另一实施例中,衬底310可以落在密封剂150上。在衬底310与密封剂150接触的情况下,可以利用密封剂来控制插入体130和衬底310之间的撑开距离,从而保持互连340的预期高度。
现在转至图4,其示出了计算系统400的实施例。系统400包括设置在主板410和其他电路板上的若干部件。主板410包括第一面412和相对的第二面414,各种部件可以设置在第一面412和第二面414中的任一者或两者上。在所示的实施例中,计算系统400包括设置在主板的第一面412上的PoP组件302,PoP组件302可以包括文中描述的任何实施例。系统400可以包括任何类型的计算系统,例如,手持计算器件(例如,蜂窝电话、智能电话、移动互联网器件、音乐播放器等)或者移动计算器件(例如,膝上电脑、上网本、平板电脑、计算机等)。然而,所公开的实施例不限于手持和其他移动计算器件,这些实施例可以应用于任何其他类型的计算系统,例如,台式计算机和服务器。
主板410可以包括任何适当类型的能够在设置在该板上的各种部件中的一个或多个部件之间提供电连通的电路板和其他衬底。例如,在一个实施例中,主板410包括印刷电路板(PCB),其包括通过一层电介质材料相互隔离并且通过导电通孔互连的多个金属层。可以按照预期的电路图形成所述金属层中的任何一个或多个,以便在与板410耦合的部件之间对电信号进行路由(可能结合其他金属层)。然而,应当理解,所公开的实施例不限于上述PCB,此外,主板410可以包括任何其他适当的衬底。
如上所述,将PoP组件302设置到主板410的第一面412上。如前所述,PoP组件302可以包括与下IC封装100耦合的上IC封装300。PoP组件302可以包括任何预期的集成电路器件的组合。在一个实施例中,PoP组件302包括处理系统、图形处理系统、信号处理系统、无线通信系统、网络处理系统、芯片组、存储器以及这些和/或其他系统的组合中的任何一个或多个。在一个实施例中,设置在PoP组件302中的IC管芯包括芯片上系统(SoC)。然而,应当理解,所公开的实施例不限于任何具体类型或种类的IC器件。而且,应当指出,在一些实施例中,可以将其他部件设置到PoP组件302上。可以设置到PoP组件302中的其他部件包括例如电压调节器以及诸如电容器、电阻器、滤波器、电感器之类的无源电气器件。
使PoP组件302通过从所述PoP组件延伸出来的多个端子170(例如,连接盘、焊料凸起、金属柱等)与主板410电连接,所述端子与衬底410上的对应端子(例如,接合焊盘、凸起、柱等)耦合。可以采用任何适当的过程在PoP组件302的端子170组和衬底410上的对应端子组之间形成电连接。例如,可以通过焊料回流工艺使这些配合端子电耦合(也可能机械接合)。
除了PoP组件302之外,可以将一个或多个额外部件设置到主板410的面412、414中的任一者或两者上。例如,如图所示,可以将部件401a设置到主板110的第一面412上,可以将部件401b设置到主板的相对的第二面414上。可以被设置到主板410上的额外部件包括其他IC器件(例如,处理器件、存储器件、信号处理器件、无线通信器件等)、功率传输部件(例如,电压调节器、诸如电池的电源和/或诸如电容器的无源器件)以及一个或多个用户接口器件(例如,音频输入器件、音频输出器件、小键盘或诸如触摸屏显示器的其他数据输入器件和/或图形显示器等)以及这些和/或其他器件的任何组合。在另一实施例中,计算系统400包括辐射屏蔽。在另一实施例中,计算系统400包括冷却解决方案。在又一实施例中,计算系统400包括天线。在又一实施例中,组件400可以设置在外壳内。
参考图5,其示出了制造下IC封装以及将下IC封装附着到上IC封装上以形成PoP组件的方法的实施例。如方框510中所述,将一个或多个IC管芯附着到衬底上,在一些实施例中,可以将底部填充材料设置到IC管芯和衬底之间(例如,图1A到1L示出的实施例中的任何一个中的管芯120(或120a-c)和底部填充160以及上面所附文字中)。如方框520中所述,使插入体与衬底耦合(例如,图1A到1L的实施例中的任何一个中的插入体130)。如方框530中所述,将密封剂设置到下IC封装中(例如,图1A到1L的实施例中的任何一个中的密封剂150)。可以采用任何适当的技术将密封剂150设置到IC封装中,例如,通过注射器或者针型分配器、模制、模版印刷等。在一个实施例中,如方框515所述,将一个或多个流动屏障设置到下IC封装中,以控制密封剂150的流动(例如,图2A到2E中所示的实施例中的任何一个中的流动屏障205a-c以及上面所附的文字)。根据一个实施例,将衬底和插入体构造成面板或条的部分,可以在面板级上执行一个或多个上述组装过程,在这种情况下,通过个体分离过程使分立的封装组件分离,如方框535中所述。在又一实施例中,如方框540中所述,将上IC封装附着到下IC封装上,以形成PoP组件(例如,图3和上附文字)。
已经参考图1A到1L、图2A到2E、图3、图4和图5描述了很多实施例,应当理解可以将这些实施例或者实施例的某些特征结合使用。例如,可以将图2A到2E所示的流动屏障中的任何一个与文中描述的任何其他实施例结合使用。作为另一示例,图1A到1L所示的下IC封装的实施例中的任何实施例都可以形成PoP组件(例如,参考图3)或者计算系统(例如,参考图4)的部分。而且,文中采用诸如“第一面”、“第二面”、“第一表面”、“第二表面”等术语来描述所公开的实施例的各种特征。但是,应当理解,可以对文中公开的各种特征和实施例采用任何适当的命名法或术语(例如,“上面”、“下面”、“上表面”、“下表面”等)。
上述实施例可以表现出几个值得注意的特征。插入体与密封剂的结合能够减少温度循环变化过程中的封装翘曲(例如,在回流温度下),还能够减少最终组件的封装翘曲(例如,在室温下)。模拟研究表明,插入体和密封剂的结合在一些实施例中有可能将温度循环变化过程中发生的翘曲减少一半以上,此外还有可能将最后组件的翘曲减少一半以上。此外,所述插入体可以提供与从上IC封装延伸的凸起(或其他端子)配合的焊盘,其消除了在上下封装之间的互连包括凸起对接结构的情况下可能出现的凸起顶端与凸起顶端的对接。在组装过程中消除这样的凸起顶端与凸起顶端的啮合能够使上下IC封装之间的错位降至最低,还可以减少非润湿焊接接头损坏。而且,在附着至上IC封装之前不需要在插入体上实施形成焊料凸起的步骤(但是,向插入体上的焊盘涂覆焊膏层是处于所公开的实施例的范围内的)。此外,除了提供提高的封装刚度之外,密封剂还能够保护设置于下IC封装内的任何IC管芯,并减少管芯裂缝。在一些实施例中,可以将薄管芯(例如,具有250微米或更小的厚度的管芯)设置在下IC封装中,所述密封剂可以保护这样的薄管芯。
上述详细说明和附图只用于举例说明,而非构成限制。附图可以不显示实际尺寸和/或所表现的特征的比例。提供附图的目的主要是为了使所公开的实施例得到清晰全面的理解,不应从中解读出任何不必要的限制。在不背离所公开的实施例的精神以及所附权利要求的范围的情况下,本领域技术人员可以设计出各种对文中描述的实施例的添加、删减和修改以及替代性的方案。

Claims (20)

1.一种下集成电路(IC)封装,所述下IC封装用于与上IC封装耦合以形成封装体叠层组件,所述下IC封装包括:
衬底,具有第一面和相对的第二面;
IC管芯,与所述衬底的所述第一面耦合;
密封剂,所述密封剂设置在所述管芯的表面的至少一部分之上以及所述衬底的所述第一面的至少一部分之上;
插入体,具有第一面和相对的第二面,所述插入体的所述第二面面对所述衬底的所述第一面;
若干互连,使所述插入体与所述衬底电耦合;以及
多个端子,设置在所述插入体的所述第一面上,所述多个端子用于形成与所述上IC封装的电连接。
2.根据权利要求1所述的下IC封装,还包括用于控制所述密封剂的流动的屏障。
3.根据权利要求2所述的下IC封装,其中,所述屏障阻止所述密封剂朝向所述若干互连流动。
4.根据权利要求2所述的下IC封装,其中,所述屏障包括选自由拦截堤、相对于所述密封剂非浸润的涂层、和沟槽构成的组的结构。
5.根据权利要求1所述的下IC封装,其中,所述IC管芯的表面的一部分基本上无密封剂。
6.根据权利要求1所述的下IC封装,其中,所述密封剂在所述若干互连中的一个或多个互连的表面的至少一部分之上延伸。
7.根据权利要求1所述的下IC封装,其中,所述插入体包括具有开口的框架。
8.根据权利要求1所述的下IC封装,还包括设置在所述IC管芯和所述衬底的所述第一面之间的底部填充材料,其中,所述密封剂与所述底部填充材料的至少一部分接触。
9.根据权利要求1所述的下IC封装,还包括用于使所述IC管芯与所述衬底电耦合的若干引线键合,其中,所述密封剂被设置到所述引线键合中的至少一个引线键合之上。
10.根据权利要求1所述的下IC封装,其中,所述衬底被直接构建到所述IC管芯之上。
11.根据权利要求1所述的下IC封装,其中,所述多个端子中的至少一个端子包括导电焊盘,所述焊盘能够形成与从所述上IC封装延伸出来的导电凸起的电连接。
12.根据权利要求1所述的下IC封装,还包括设置在所述衬底的所述第二面上的第二多个端子,所述第二多个端子用于使所述下IC封装与电路板电耦合。
13.一种封装体叠层(PoP)组件,包括:
下集成电路(IC)封装,所述下IC封装包括:衬底,具有第一面和相对的第二面;IC管芯,与所述衬底的所述第一面耦合;插入体,具有第一面和面对所述衬底的所述第一面的相对的第二面;若干互连,使所述插入体与所述衬底电耦合;以及密封剂,所述密封剂设置在所述管芯的表面的至少一部分之上以及所述衬底的所述第一面的至少一部分之上;
上IC封装;以及
多个互连,用于使所述上IC封装与所述插入体的所述第一面电耦合。
14.根据权利要求13所述的PoP组件,其中,所述上IC封装包括设置在第二衬底上的至少一个IC管芯。
15.根据权利要求14所述的PoP组件,还包括:
导电焊盘,设置在所述插入体的所述第一面上;
其中,所述多个互连中的至少一个互连包括从所述第二衬底延伸出来并与所述导电焊盘耦合的焊料凸起。
16.根据权利要求13所述的PoP组件,还包括设置在所述下IC封装中以控制所述密封剂的流动的屏障。
17.根据权利要求13所述的PoP组件,其中,所述密封剂在所述若干互连中的一个或多个互连的表面的至少一部分之上延伸。
18.根据权利要求13所述的PoP组件,其中,所述插入体包括具有开口的框架。
19.根据权利要求13所述的PoP组件,其中,所述下IC封装的所述衬底被直接构建在所述IC管芯之上。
20.根据权利要求13所述的PoP组件,还包括所述下IC封装的所述衬底的所述第二面上的多个端子,所述多个端子用于使所述PoP组件与电路板电耦合。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109148310A (zh) * 2014-11-21 2019-01-04 意法半导体(格勒诺布尔2)公司 包括堆叠的芯片的电子器件
US10879219B2 (en) 2010-12-16 2020-12-29 Intel Corporation Lower IC package structure for coupling with an upper IC package to form a package-on-package (PoP) assembly and PoP assembly including such a lower IC package structure

Families Citing this family (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3751604A1 (en) * 2011-08-16 2020-12-16 INTEL Corporation Offset interposers for large-bottom packages and large-die package-on-package structures
US8718550B2 (en) * 2011-09-28 2014-05-06 Broadcom Corporation Interposer package structure for wireless communication element, thermal enhancement, and EMI shielding
US20140001623A1 (en) * 2012-06-28 2014-01-02 Pramod Malatkar Microelectronic structure having a microelectronic device disposed between an interposer and a substrate
US9497861B2 (en) 2012-12-06 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for package with interposers
US8994176B2 (en) 2012-12-13 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for package with interposers
TWI556033B (zh) * 2012-12-14 2016-11-01 義隆電子股份有限公司 行動電子裝置、其螢幕控制模組、及其觸控面板控制器
TWI584025B (zh) * 2012-12-14 2017-05-21 義隆電子股份有限公司 行動電子裝置的螢幕控制模組及其觸控面板控制器
TWI489176B (zh) 2012-12-14 2015-06-21 Elan Microelectronics Corp 行動電子裝置的螢幕控制模組及其控制器
US9768048B2 (en) * 2013-03-15 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package on-package structure
CN104051411B (zh) 2013-03-15 2018-08-28 台湾积体电路制造股份有限公司 叠层封装结构
US9596756B2 (en) 2013-09-06 2017-03-14 Apple Inc. Electronic device with printed circuit board noise reduction using elastomeric damming and damping structures
KR102134133B1 (ko) * 2013-09-23 2020-07-16 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
KR102245770B1 (ko) * 2013-10-29 2021-04-28 삼성전자주식회사 반도체 패키지 장치
US9627329B1 (en) * 2014-02-07 2017-04-18 Xilinx, Inc. Interposer with edge reinforcement and method for manufacturing same
US9379097B2 (en) 2014-07-28 2016-06-28 Apple Inc. Fan-out PoP stacking process
WO2016043761A1 (en) 2014-09-18 2016-03-24 Intel Corporation Method of embedding wlcsp components in e-wlb and e-plb
US9773740B2 (en) 2014-11-26 2017-09-26 Stmicroelectronics (Grenoble 2) Sas Stacked electronic device including a protective wafer bonded to a chip by an infused adhesive
US10319619B2 (en) 2014-12-05 2019-06-11 Samsung Electronics Co., Ltd. Equipment for manufacturing semiconductor devices and method for use of same for manufacturing semiconductor package components
US20160172292A1 (en) * 2014-12-16 2016-06-16 Mediatek Inc. Semiconductor package assembly
US10475715B2 (en) * 2015-06-17 2019-11-12 Intel Corporation Two material high K thermal encapsulant system
US9691675B1 (en) 2015-12-22 2017-06-27 Intel Corporation Method for forming an electrical device and electrical devices
KR20170086921A (ko) 2016-01-19 2017-07-27 삼성전기주식회사 패키지기판 및 그 제조 방법
CN109075151B (zh) 2016-04-26 2023-06-27 亚德诺半导体国际无限责任公司 用于组件封装电路的机械配合、和电及热传导的引线框架
US10177107B2 (en) * 2016-08-01 2019-01-08 Xilinx, Inc. Heterogeneous ball pattern package
US20180053753A1 (en) * 2016-08-16 2018-02-22 Freescale Semiconductor, Inc. Stackable molded packages and methods of manufacture thereof
US10079222B2 (en) 2016-11-16 2018-09-18 Powertech Technology Inc. Package-on-package structure and manufacturing method thereof
KR102494595B1 (ko) * 2016-11-21 2023-02-06 삼성전자주식회사 반도체 패키지
CN107980243A (zh) * 2017-03-15 2018-05-01 深圳大趋智能科技有限公司 安全ic保护结构及电路板
WO2018182756A1 (en) * 2017-04-01 2018-10-04 Intel Corporation 5G mmWAVE COOLING THROUGH PCB
KR102255758B1 (ko) * 2017-04-26 2021-05-26 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
US10217649B2 (en) * 2017-06-09 2019-02-26 Advanced Semiconductor Engineering, Inc. Semiconductor device package having an underfill barrier
KR102419154B1 (ko) * 2017-08-28 2022-07-11 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
US10497635B2 (en) 2018-03-27 2019-12-03 Linear Technology Holding Llc Stacked circuit package with molded base having laser drilled openings for upper package
US11410977B2 (en) 2018-11-13 2022-08-09 Analog Devices International Unlimited Company Electronic module for high power applications
US11328936B2 (en) * 2018-12-21 2022-05-10 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of package structure with underfill
US11164804B2 (en) 2019-07-23 2021-11-02 International Business Machines Corporation Integrated circuit (IC) device package lid attach utilizing nano particle metallic paste
KR20210109258A (ko) 2020-02-27 2021-09-06 삼성전자주식회사 반도체 패키지 장치
KR20210126988A (ko) 2020-04-13 2021-10-21 삼성전자주식회사 인터포저 및 이를 포함하는 반도체 패키지
US11270986B2 (en) 2020-05-18 2022-03-08 Analog Devices, Inc. Package with overhang inductor
KR20210144050A (ko) 2020-05-21 2021-11-30 삼성전자주식회사 반도체 패키지
US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component
US11296034B2 (en) * 2020-06-18 2022-04-05 Advanced Semiconductor Engineering, Inc. Substrate and semiconductor package comprising an interposer element with a slot and method of manufacturing the same
KR20220001311A (ko) 2020-06-29 2022-01-05 삼성전자주식회사 반도체 패키지, 및 이를 가지는 패키지 온 패키지
US11652014B2 (en) * 2020-09-30 2023-05-16 Advanced Semiconductor Engineering, Inc. Electronic package and method of manufacturing the same
KR20220072458A (ko) 2020-11-25 2022-06-02 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
US11705406B2 (en) * 2021-06-17 2023-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method for forming the same
US11765836B2 (en) 2022-01-27 2023-09-19 Xilinx, Inc. Integrated circuit device with edge bond dam

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6759307B1 (en) * 2000-09-21 2004-07-06 Micron Technology, Inc. Method to prevent die attach adhesive contamination in stacked chips
US20090166834A1 (en) * 2007-12-27 2009-07-02 Stats Chippac Ltd. Mountable integrated circuit package system with stacking interposer
US20100148344A1 (en) * 2008-12-11 2010-06-17 Harry Chandra Integrated circuit package system with input/output expansion

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4963148B2 (ja) * 2001-09-18 2012-06-27 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
TW200601516A (en) * 2004-06-25 2006-01-01 Advanced Semiconductor Eng Stacked multi-package module
TWI278122B (en) * 2005-06-17 2007-04-01 Advanced Semiconductor Eng Dispensing package of image sensor and its method
US7985623B2 (en) * 2006-04-14 2011-07-26 Stats Chippac Ltd. Integrated circuit package system with contoured encapsulation
KR100792352B1 (ko) 2006-07-06 2008-01-08 삼성전기주식회사 패키지 온 패키지의 바텀기판 및 그 제조방법
US20080142996A1 (en) * 2006-12-19 2008-06-19 Gopalakrishnan Subramanian Controlling flow of underfill using polymer coating and resulting devices
JP4901458B2 (ja) 2006-12-26 2012-03-21 新光電気工業株式会社 電子部品内蔵基板
JP2008166527A (ja) 2006-12-28 2008-07-17 Spansion Llc 半導体装置およびその製造方法
US7400033B1 (en) * 2006-12-29 2008-07-15 Intel Corporation Package on package design to improve functionality and efficiency
JP2009135398A (ja) 2007-11-29 2009-06-18 Ibiden Co Ltd 組合せ基板
TW200939451A (en) * 2008-03-06 2009-09-16 Advanced Semiconductor Eng Stacked semiconductor package
US7901987B2 (en) * 2008-03-19 2011-03-08 Stats Chippac Ltd. Package-on-package system with internal stacking module interposer
US7968373B2 (en) * 2008-05-02 2011-06-28 Stats Chippac Ltd. Integrated circuit package on package system
JP5645047B2 (ja) 2008-09-29 2014-12-24 日立化成株式会社 半導体素子搭載用パッケージ基板とその製法及び半導体パッケージ
US7863100B2 (en) * 2009-03-20 2011-01-04 Stats Chippac Ltd. Integrated circuit packaging system with layered packaging and method of manufacture thereof
US8080446B2 (en) * 2009-05-27 2011-12-20 Stats Chippac Ltd. Integrated circuit packaging system with interposer interconnections and method of manufacture thereof
US8624364B2 (en) * 2010-02-26 2014-01-07 Stats Chippac Ltd. Integrated circuit packaging system with encapsulation connector and method of manufacture thereof
US20120159118A1 (en) 2010-12-16 2012-06-21 Wong Shaw Fong Lower IC Package Structure for Coupling with an Upper IC Package to Form a Package-On-Package (PoP) Assembly and PoP Assembly Including Such a Lower IC Package Structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6759307B1 (en) * 2000-09-21 2004-07-06 Micron Technology, Inc. Method to prevent die attach adhesive contamination in stacked chips
US20090166834A1 (en) * 2007-12-27 2009-07-02 Stats Chippac Ltd. Mountable integrated circuit package system with stacking interposer
US20100148344A1 (en) * 2008-12-11 2010-06-17 Harry Chandra Integrated circuit package system with input/output expansion

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10879219B2 (en) 2010-12-16 2020-12-29 Intel Corporation Lower IC package structure for coupling with an upper IC package to form a package-on-package (PoP) assembly and PoP assembly including such a lower IC package structure
CN109148310A (zh) * 2014-11-21 2019-01-04 意法半导体(格勒诺布尔2)公司 包括堆叠的芯片的电子器件
CN109148310B (zh) * 2014-11-21 2022-12-06 意法半导体(格勒诺布尔2)公司 包括堆叠的芯片的电子器件

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