JP2010521818A - 半導体デバイスパッケージ化装置、パッケージ化された半導体部品、半導体デバイスパッケージ化装置の製造方法、及び半導体部品の製造方法 - Google Patents
半導体デバイスパッケージ化装置、パッケージ化された半導体部品、半導体デバイスパッケージ化装置の製造方法、及び半導体部品の製造方法 Download PDFInfo
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- JP2010521818A JP2010521818A JP2009553715A JP2009553715A JP2010521818A JP 2010521818 A JP2010521818 A JP 2010521818A JP 2009553715 A JP2009553715 A JP 2009553715A JP 2009553715 A JP2009553715 A JP 2009553715A JP 2010521818 A JP2010521818 A JP 2010521818A
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Abstract
【選択図】図4
Description
Claims (38)
- 第1のボードと第2のボードを含み、
前記第1のボードは、前側と、裏側と、ダイ接点のアレイと、前記ダイ接点と電気的につながれた第1の裏側端子のアレイと、第2の裏側端子のアレイと、各々が前記ダイ接点のアレイ及び前記第1の裏側端子のアレイ及び前記第2の裏側端子のアレイを有する、複数の個々のパッケージ領域と、を有し、
前記第2のボードは、前記第1のボードの前記前側にラミネートされた第1の面と、第2の面と、前記第2のボードを貫き、個々のパッケージ領域と整列され、ダイキャビティを画定する開口と、前記第1のボード及び前記第2のボードを貫いて伸びるインターコネクトによって前記第2の裏側端子と電気的につながれた前記第2の面にある前側接点のアレイと、を有する
ことを特徴とする半導体デバイスパッケージ化装置。 - 請求項1に記載の装置において、
前記第1及び前記第2のボードは、ポリマーのコアを有する
ことを特徴とする装置。 - 請求項1に記載の装置において、
前記第1のボード及び前記第2のボードを貫いて伸びる前記インターコネクトは、途切れのないスルーパッケージインターコネクトである
ことを特徴とする装置。 - 請求項1に記載の装置において、
前記第1のボードは、さらに、
前記ダイ接点を、対応する第1の裏側端子に電気的につなぐ、第1のインターコネクトを含み、
前記第1のボード及び前記第2のボードを貫いて伸びる前記インターコネクトは、第2のインターコネクトである
ことを特徴とする装置。 - 請求項1に記載の装置において、
前記第1のボードは、第1のプリント基板を含み、
前記第2のボードは、第2のプリント基板を含む
ことを特徴とする装置。 - 請求項1に記載の装置において、
前記個々のパッケージ領域と前記ダイキャビティは、ストリップに並べられ、
個々のダイキャビティは、前記ストリップ上の切断レーンによって、分離される
ことを特徴とする装置。 - 請求項1に記載の装置において、
前記ダイ接点は、前記第1のボードの前記前側にある
ことを特徴とする装置。 - 請求項1に記載の装置において、
前記第1のボードは、さらに、各スロットが個々のパッケージ領域に置かれるように、複数のスロットを含み、
前記ダイ接点は、前記スロットに隣接する前記第1のボードの前記第2の面に、アレイ状に並べられる
ことを特徴とする装置。 - 請求項1に記載の半導体デバイスパッケージ化装置において、
前記第1のボードは、
前記前側及び前記裏側を有するベースパネルを含み、
前記ベースパネルは、ポリマー材料からなり、
前記第2のボードは、
前記ベースパネルの前記前側に取り付けられた前記第1の面と、前記第2の面と、ダイキャビティを画定する前記複数の開口と、を有するライザーパネルを含み、
前記ライザーパネルは、ポリマー材料からなり、
前記ダイ接点の前記アレイは、前記ベースパネルにあり、
前記第1の裏側端子の前記アレイは、前記ベースパネルの前記裏側にあり、
前記デバイスは、前記ダイ接点を、前記第1の裏側端子と電気的につなぐ第1のインターコネクトを有し、
前記前側接点の前記アレイは、前記ライザーパネルの前記第2の面にあり、
前記第2の裏側端子の前記アレイは、前記ベースパネルの前記裏側にあり、
前記デバイスは、前記ベースパネルと前記ライザーパネルを貫いて伸びる第2のインターコネクトを有し、
前記第2のインターコネクトは、前記前側接点を、前記第2の裏側端子と電気的につなぐ
ことを特徴とする半導体デバイスパッケージ化装置。 - 請求項9に記載の装置において、
前記ベースパネルは、第1のプリント基板を含み、
前記ライザーパネルは、第2のプリント基板を含み、
前記開口は、前記第2のプリント基板の中にあるパンチ穴を含む
ことを特徴とする装置。 - 請求項10に記載の装置において、
前記ベースパネルは、第1のプリント基板を含み、
前記ライザーパネルは、さらに、前記第1の面に付着した接着剤を有する第2のプリント基板を含み、
前記開口は、前記第2のプリント基板及び前記接着剤の中にあるパンチ穴を含む
ことを特徴とする装置。 - 請求項10に記載の装置において、
前記第2の端子は、前記ライザーパネルの前記第2の面から前記ベースパネルの前記裏側まで伸びる途切れのないスルーパッケージ端子を含む
ことを特徴とする装置。 - 請求項9に記載の装置において、
前記ベースパネル及び前記ライザーパネルは、切断レーンによって分離された、複数のダイキャビティを有する、ストリップを画定する
ことを特徴とする装置。 - 請求項1に記載のパッケージ化された半導体部品において、
前記第1のボードは、前側と、裏側と、ダイ接点と、前記裏側にある第1の裏側端子の第1のアレイと、前記裏側にある第2の裏側端子の第2のアレイと、前記ダイ接点を前記第1の裏側端子に電気的につなぐ第1のインターコネクトと、を持つ第1のポリマー基板を有するベースを含み、
前記第2のボードは、第1の面と、第2の面と、開口と、前記第2の面にある前側接点と、を持つ第2のポリマー基板を有するライザーを含み、
前記第1の面は、前記第1のポリマー基板の前記前側に取り付けられ、
前記開口は、ダイキャビティを画定し、
前記パッケージ化された半導体部品は、さらに、
前記第1のポリマー基板及び前記第2のポリマー基板を貫き、前記前側接点を対応する第2の裏側端子と電気的につなぐ、第2のインターコネクトと、
前記ダイキャビティの中にあり、前記ダイ接点と電気的につながれた集積回路を有する、ダイと、を含む
ことを特徴とするパッケージ化された半導体部品。 - 請求項14に記載のパッケージ化された部品において、
さらに、前記ライザーの前記第2の面に積層された第2のパッケージ化された半導体部品を含み、
前記第2のパッケージ化された半導体部品は、前記前側接点に取り付けられた電気的コネクターを有する
ことを特徴とするパッケージ化された部品。 - 請求項14に記載のパッケージ化された部品において、
ダイ接点は、前記ベースの前記前側にあり、
前記ダイは、ダイ接点とワイヤーボンドされたボンドパッドを有する
ことを特徴とするパッケージ化された部品。 - 請求項14に記載のパッケージ化された部品において、
前記ダイ接点は、前記ベースの前記前側にあり、
前記ダイは、前記ダイ接点に取り付けられたボンドパッドフリップチップを有する
ことを特徴とするパッケージ化された部品。 - 請求項14に記載のパッケージ化された部品において、
前記ベースは、さらに、スロットを含み、
前記ダイ接点は、前記ベースの前記裏側にあり、
前記ダイは、前記スロットに向かい合い、前記スロットを通って伸びるワイヤーボンドにより前記ダイ接点とワイヤーボンドされた、ボンドパッドを有する
ことを特徴とするパッケージ化された部品。 - 請求項14に記載のパッケージ化された部品において、
さらに、前記ダイキャビティ内に、保護材を含む
ことを特徴とするパッケージ化された部品。 - ライザーボードの第1の面をベースボードの前側に取り付けるステップであって、
ダイキャビティが、前記ベースボードの対応する個々のパッケージ領域に整列された前記ライザーボード内の個々の開口によって形成され、
前記ベースボードは、ダイ接点と、前記ベースボードの裏側にあり、前記ダイ接点と電気的につながれた第1の裏側端子と、を有する、というステップと、
前記ライザーボード及び前記ベースボードを貫いて伸びる、複数のスルーパッケージビアを形成するステップと、
前記スルーパッケージビアの中に導電材料を堆積させるステップであって、
前記導電材料は、前記ライザーボードの第2の面にある前側接点を、前記ベースボードの裏側にある対応する第2の裏側端子と、電気的につなぐスルーパッケージインターコネクトを形成する、というステップと、を含む
ことを特徴とする半導体デバイスパッケージ化装置を製造する方法。 - 請求項20に記載の方法であって、
前記ライザーボードを前記ベースボードに取り付けるステップより前に、さらに、
接着剤を前記ライザーボードの前記第1の面に付着するステップと、
前記ライザーボード及び前記接着剤を貫く前記開口を開けるステップと、を含む
ことを特徴とする方法。 - 請求項20に記載の方法であって、
前記ベースボードは、第1のプリント基板を含み、
前記ライザーボードは、第2のプリント基板を含み、
さらに、
前記ライザーボードの前記前側接点を、前記ベースボードの前記第2の裏側端子と整列させるステップと、
前記ライザーボードの前記第1の面及び前記ベースボードの前記前側を、接着剤に押し付けるステップと、を含む
ことを特徴とする方法。 - 請求項22に記載の方法であって、
前記スルーパッケージビアを形成するステップは、前記ライザーボード及び前記ベースボードを貫く穴を開けるステップを含む
ことを特徴とする方法。 - 請求項20に記載の方法であって、さらに、
前記ライザーボードの前記前側接点を、前記ベースボードの前記第2の裏側端子と整列させるステップと、
前記ライザーボードの前記第1の面及び前記ベースボードの前記前側を接着剤に押し付けるステップと、を含み、
前記スルーパッケージビアを形成するステップは、対応し対をなす前側接点と第2の裏側端子をつなげる穴を開けるステップを含む
ことを特徴とする方法。 - 請求項20に記載の方法であって、さらに、
前記ライザーボードの前記前側接点を、前記ベースボードの前記第2の裏側端子と整列させるステップと、
前記ライザーボードの前記第1の面及び前記ベースボードの前記前側を接着剤に押し付けるステップと、を含み、
前記スルーパッケージビアを形成するステップは、対応し対をなす前側接点と第2の裏側端子をつなげる穴を開けるステップを含み、
前記スルーパッケージビアの中に導電材料を堆積させるステップは、前記穴の中に金属をめっきするステップを含む
ことを特徴とする方法。 - 請求項20に記載の方法であって、
前記ライザーボードを前記ベースボードに取り付けるステップの前に、さらに、
前記ライザーボードの前記第2の面に回路を形成するステップと、
前記ライザーボードの前記第1の面に接着剤を付着するステップと、
前記ライザーボード及び前記接着剤を貫く前記開口を開けるステップと、を含み、
前記ライザーボードを前記ベースボードに取り付けるステップは、
前記開口を対応する個々のパッケージ領域と整列させながら、前記ライザーボードの前記第1の面にある前記接着剤を前記ベースボードの前記前側に押し付けるステップを含む
ことを特徴とする方法。 - 請求項26に記載の方法であって、
前記第2の面にある前記前側接点は、前記ベースボードの対応する第2の裏側端子に対して重ねられ、
前記ビアを形成するステップは、前記前側接点に、対応する裏側接点まで伸びる穴を開けるステップを含む
ことを特徴とする方法。 - 請求項27に記載の方法であって、
前記ビアの中に前記導電材料を堆積させるステップは、前記穴に金属をめっきするステップを含む
ことを特徴とする方法。 - 半導体部品の製造方法であって、
パッケージ化されるべき複数のダイが中にある装置を提供するステップであって、
前記装置は、第1のボードと第2のボードを含み、
前記第1のボードは、前側と、裏側と、ダイ接点のアレイと、前記ダイ接点と電気的につながれた第1の裏側端子のアレイと、第2の裏側端子のアレイと、各々が前記ダイ接点のアレイ及び前記第1の裏側端子のアレイ及び前記第2の裏側端子のアレイを有する、複数の個々のパッケージ領域と、を有し、
前記第2のボードは、前記第1のボードの前記前側にラミネートされた第1の面と、第2の面と、前記第2のボードを貫き、個々のパッケージ領域と整列され、ダイキャビティを画定する開口と、前記第1のボード及び前記第2のボードを貫いて伸びるスルーパッケージインターコネクトによって前記第2の裏側端子と電気的につながれた、前記第2の面にある前側接点のアレイと、を有する、というステップと、
前記ダイキャビティ内に半導体ダイを置くステップと、
前記ダイ上のボンドパッドを、前記第1のボードの対応するダイ接点と電気的につなぐステップと、
前記ダイキャビティの中に保護材を堆積させるステップと、を含む
ことを特徴とする半導体部品の製造方法。 - 請求項29に記載の方法であって、
前記ダイ上の前記ボンドパッドを、前記ダイ接点と電気的につなぐステップは、前記ボンドパッドを、前記ダイ接点とワイヤーボンドするステップを含む
ことを特徴とする方法。 - 請求項29に記載の方法であって、
前記ダイ上の前記ボンドパッドを、前記ダイ接点と電気的につなぐステップは、前記ボンドパッドを、前記ダイ接点上にフリップチップ実装するステップを含む
ことを特徴とする方法。 - 請求項29に記載の方法であって、
前記第1のボードは、スロットを有し、
前記ダイ接点は、前記スロットの近くの前記第1のボードの前記裏側に、アレイ状に並べられ、
前記ダイは、前記ダイ上のボンドパッドが対応するスロットと整列されるように、前記第1のボードの前記前表面に取り付けられたアクティブ側を有し、
前記ダイ上の前記ボンドパッドを、前記ダイ接点と電気的につなぐステップは、前記ボンドパッドから前記ダイ接点まで前記スロットを通って伸びるワイヤーボンドを形成するステップを含む
ことを特徴とする方法。 - 請求項29に記載の方法であって、さらに、
前記個々のパッケージ領域間で、前記第1のボード及び前記第2のボードを切断するステップであって、個々のパッケージ化された半導体部品は、互いに分離される、というステップを含む
ことを特徴とする方法。 - 請求項33に記載の方法であって、さらに、
前記個々のパッケージ化された半導体部品をテストするステップと、
良品とわかるパッケージ化された半導体部品のみを、互いに積層するステップと、を含む
ことを特徴とする方法。 - 請求項34に記載の方法であって、
積層するステップは、第1のパッケージ化された半導体部品の前側接点を、前記第1のパッケージ化された半導体部品上に積層された第2のパッケージ化された半導体部品の、対応する第2の裏側端子と電気的につなぐステップを含む
ことを特徴とする方法。 - 請求項29に記載の方法であって、さらに、
良品とわかるパッケージを決定するために、前記第1のボード及び前記第2のボードを切断する前に、前記個々のパッケージ化された半導体部品をテストするステップを含む
ことを特徴とする方法。 - 請求項36に記載の方法であって、さらに、
前記個々のパッケージ領域の間で、前記第1のボード及び前記第2のボードを切断するステップと、
良品とわかるパッケージ化された半導体部品のみを、互いに積層するステップと、を含む
ことを特徴とする方法。 - 請求項37に記載の方法であって、
積層するステップは、第1のパッケージ化された半導体部品の前側接点を、前記第1のパッケージ化された半導体部品上に積層された、第2のパッケージ化された半導体部品の、対応する第2の裏側端子に電気的につなぐステップを含む
ことを特徴とする方法。
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