JP6061937B2 - 積層された超小型電子装置を有する超小型電子パッケージ及びその製造方法 - Google Patents

積層された超小型電子装置を有する超小型電子パッケージ及びその製造方法 Download PDF

Info

Publication number
JP6061937B2
JP6061937B2 JP2014537171A JP2014537171A JP6061937B2 JP 6061937 B2 JP6061937 B2 JP 6061937B2 JP 2014537171 A JP2014537171 A JP 2014537171A JP 2014537171 A JP2014537171 A JP 2014537171A JP 6061937 B2 JP6061937 B2 JP 6061937B2
Authority
JP
Japan
Prior art keywords
microelectronic
chip
microelectronic device
contact
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2014537171A
Other languages
English (en)
Other versions
JP2014531134A (ja
JP2014531134A5 (ja
Inventor
キャスキー，テレンス
モハメッド，イリヤス
Original Assignee
インヴェンサス・コーポレイション
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by インヴェンサス・コーポレイション filed Critical インヴェンサス・コーポレイション
Publication of JP2014531134A publication Critical patent/JP2014531134A/ja
Publication of JP2014531134A5 publication Critical patent/JP2014531134A5/ja
Application granted granted Critical
Publication of JP6061937B2 publication Critical patent/JP6061937B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/117—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/06155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H01L2224/1329—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
    • H01L2224/2733—Manufacturing methods by local deposition of the material of the layer connector in solid form
    • H01L2224/27334—Manufacturing methods by local deposition of the material of the layer connector in solid form using preformed layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H01L2224/48108—Connecting bonding areas at different heights the connector not being orthogonal to a side surface of the semiconductor or solid-state body, e.g. fanned-out connectors, radial layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73217—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82031—Reshaping, e.g. forming vias by chemical means, e.g. etching, anodisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82035—Reshaping, e.g. forming vias by heating means
    • H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82047—Reshaping, e.g. forming vias by mechanical means, e.g. severing, pressing, stamping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06596—Structural arrangements for testing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1052—Wire or wire-like electrical connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1076—Shape of the containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1076—Shape of the containers
    • H01L2225/1082—Shape of the containers for improving alignment between containers, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/186—Material

Description

本発明は、積層された超小型電子装置を含む超小型電子パッケージ及びそのパッケージの製造方法に関する。
［関連出願の相互参照］
本出願は、２０１１年１０月２０日に出願された米国特許出願第１３／２７７，３３０号の継続出願である。この出願の開示内容を引用することにより本明細書の一部をなすものとする。
半導体チップは表の面上に配置されチップ自体の内部電気回路に接続されたコンタクトを有する平板体である。半導体チップは通常、パッケージに入れられてパッケージのコンタクトに電気的に接続された複数の端子を有する超小型電子パッケージを構成する。次に、パッケージの端子は外部の超小型電子部品、例えば回路パネルに接続されてもよい。
複数の超小型電子パッケージを、「積層」配置してパッケージに入れることがしばしば望ましい。この積層配置では超小型電子パッケージはそれぞれ１つ以上の半導体チップを含み、積み重ねられてスペースを節約する。積層チップパッケージ構造体又はパッケージ・オン・パッケージ（ＰｏＰ）においては、複数のパッケージのそれぞれのチップは積み重ねられてその表面積は全チップの総表面積より小さい。このＰｏＰのチップの低減された面積によって、ＰｏＰのチップが取り付けられうる印刷回路基板（ＰＣＢ）上の領域を非常に効率的に利用することが出来る。
通常、ＰｏＰに含まれる複数の超小型電子パッケージは、積層状態で結合されＰｏＰを構成する前に、個々のパッケージのチップのチップコンタクトにおけるテストを可能にするのに十分大きなサイズを有する。また、幾つかのＰｏＰでは、導電性構造体が複数のパッケージのそれぞれのチップのチップコンタクト同士を電気的に相互接続する。このような導電性構造体はパッケージ間に高い寄生成分を発生させる長さを有し、望ましくない。
従って、超小型電子パッケージの外部の超小型電子部品に接続可能な半導体チップ等の超小型電子素子をそれぞれ備え積層された超小型電子装置を含む超小型電子パッケージを製造する技術の更なる改善が望ましい。
本開示の１つの実施形態によれば、超小型電子パッケージは、複数の第１のチップコンタクトを有する半導体チップと、前記半導体チップの端に接する封止層と、前記封止層の表面に露出し前記第１のチップコンタクトと電気的に接続された複数の第１の装置コンタクトとを含む第１の超小型電子装置を備えてよい。本パッケージは、複数の第２のチップコンタクトを表面に有する半導体チップと、前記半導体チップの端に接し前記端から延びる表面を有する封止層とを含む第２の超小型電子装置であって、該第２の超小型電子装置の前記半導体チップの前記表面と前記封止層の前記表面は該第２の超小型電子装置の外面を形成する第２の超小型電子装置を備えてよい。本パッケージは前記第１の装置コンタクトと電気的に接続された複数の結合線も備えてよい。本パッケージは、前記第２の超小型電子装置の前記外面に位置する複数のパッケージ端子であって、（ｉ）前記第１の装置コンタクトに前記結合線を介して電気的に接続されたパッケージ端子と（ｉｉ）前記第２のチップコンタクトに接して形成された金属被覆されたビアと配線とを介して前記第２のチップコンタクトに電気的に接続されたパッケージ端子とを更に備えてよい。
本開示の別の実施形態では、超小型電子パッケージの製造方法は、第１の超小型電子装置を第２の超小型電子装置の上に積層することを備えてよい。前記第１の超小型電子装置は、複数の第１のチップコンタクトを有する半導体チップと、前記半導体チップの端に接する封止層と、前記封止層の表面に露出し前記第１のチップコンタクトと電気的に接続された複数の第１の装置コンタクトとを含んでよい。前記第２の超小型電子装置は、複数の第２のチップコンタクトを表面に有する半導体チップと、前記第２の超小型電子装置の前記半導体チップの端に接し前記端から延びる表面を有する封止層とを含み、前記第２の超小型電子装置の前記半導体チップの前記表面と前記封止層の前記表面は前記第２の超小型電子装置の外面を形成する。本方法は、前記第１の装置コンタクトを前記第２の超小型電子装置の外面に位置する複数のパッケージ端子に電気的に接続する複数の結合線を形成することを更に備えてよい。前記パッケージ端子は前記第２のチップコンタクトに接して形成された金属被覆されたビアと配線とを介して前記第２のチップコンタクトに電気的に接続されている。
本開示の１つの実施形態に係る垂直方向に積層された超小型電子素子を含む超小型電子装置の製造方法の１段階を例示する概略断面図である。 本開示の１つの実施形態に係る垂直方向に積層された超小型電子素子を含む超小型電子装置の製造方法の１段階を例示する概略断面図である。 図３Ａは、本開示の１つの実施形態に係る垂直方向に積層された超小型電子素子を含む超小型電子装置の一部の概略断面図である。図３Ｂは、本開示の別の実施形態に係る垂直方向に積層された超小型電子素子を含む超小型電子装置の一部の概略断面図である。 本開示の１つの実施形態に係るパッケージ端子を有する超小型電子装置の製造方法の１段階を例示する概略断面図である。 本開示の１つの実施形態に係るパッケージ端子を有する超小型電子装置の製造方法の１段階を例示する概略断面図である。 本開示の１つの実施形態に係るパッケージ端子を有する超小型電子装置の製造方法の１段階を例示する概略断面図である。 本開示の１つの実施形態に係るパッケージ端子を有する超小型電子装置の製造方法の１段階を例示する概略断面図である。 本開示の１つの実施形態に係るパッケージ端子を有する超小型電子装置の製造方法の１段階を例示する概略断面図である。 本開示の１つの実施形態に係る図１〜図３及び図４〜図８の方法を使用して形成された超小型電子装置が積層された超小型電子パッケージの製造方法の１段階を例示する概略断面図である。 本開示の１つの実施形態に係る図１〜図３及び図４〜図８の方法を使用して形成された超小型電子装置が積層された超小型電子パッケージの製造方法の１段階を例示する概略断面図である。 本開示の１つの実施形態に係る図１〜図３及び図４〜図８の方法を使用して形成された超小型電子装置が積層された超小型電子パッケージの製造方法の１段階を例示する概略断面図である。 図１１のパッケージの底面図である。 本開示の別の実施形態に係る超小型電子パッケージの概略断面図である。 本開示の別の実施形態に係る超小型電子パッケージの概略断面図である。 本開示の１つの実施形態に係るシステムの概略図である。
超小型電子素子をそれぞれ備え積層された超小型電子装置１２及び１４を含む超小型電子パッケージ１０は、図１〜図１１に示す本開示の実施形態に従って製造されてもよい。前記各超小型電子素子は半導体チップ又はウェハなどであってよい。チップは複数の能動素子（例えば、トランジスタ、ダイオードなど）、複数の受動素子（例えば、抵抗、コンデンサ、インダクタなど）、又は能動素子と受動素子の両方を含む。通常、少なくとも１つのチップが能動素子、又は能動素子と受動素子の両方を含む。各チップは超小型電子装置内の他のチップと同じ種類であってもよいし、異なる種類であってもよい。
特定の実施形態では、パッケージ１０内の超小型電子装置のうち１つ以上、例えば超小型電子装置１４は、論理チップとして主要な機能を有するよう構成されたチップ、例えばプログラマブル汎用又は専用プロセッサ、マイクロコントローラ、書替え可能ゲートアレイ（ＦＰＧＡ）デバイス、特定用途集積回路（ＡＳＩＣ）、ディジタル信号プロセッサなどを含んでよい。このような実施形態では、パッケージ１０内の超小型電子装置のうち１つ以上、例えば超小型電子装置１２は、論理チップ以外の主要な機能を有するチップを含んでよい。例えば、１つ以上の論理チップを有する装置１４は、主要なメモリ機能を有する１つ以上の記憶アレイチップをそれぞれ含む１つ以上の装置１２と結合されてもよい。このようなメモリ記憶アレイチップは、揮発性メモリ記憶領域、例えば動的ランダムアクセスメモリ（ＤＲＡＭ）、静的ランダムアクセスメモリ（ＳＲＡＭ）、又は不揮発性メモリ記憶アレイ、例えばフラッシュメモリ又は磁気ランダムアクセスメモリ（ＭＲＡＭ）、又は揮発性記憶アレイと不揮発性記憶アレイとの組み合わせを含んでもよい。特定の実施形態では、パッケージ１０の超小型電子装置のうち１つ以上は、論理機能と他の重要な機能、例えば重要なメモリ機能とを同じチップ上で結合したチップを含んでもよい。
図１、図２を参照すると、超小型電子装置１２は垂直方向に積層されたチップ１６Ａ及び１６Ｂを含んでもよい。各チップ１６は表の面１８と表の面１８と反対側の裏面２０とを有してよい。超小型電子装置１２は１つのチップの表の面が他のチップの裏面と対面するよう構成されていてもよいし、超小型電子装置１２は垂直方向に積層された２つを超える数のチップ１６を含んでもよい。これらのチップ１６は対面する面において接着剤の層（不図示）により接合され、積層されたチップの底のチップ、例えば積層されたチップ１６Ａと１６Ｂのうちのチップ１６Ｂも、台板３１の表面２９に接着剤の層（不図示）により接合されてよい。台板３１は誘電材料又はガラスでできていてもよい。接着層はダイ取付け接着剤を含んでもよく、コンプライアンス、熱伝導性、水分又は他の汚染物質に対する不透過性などの特性、又はこれら特性の組み合わせを有するものを選択してもよい。接着層は、チップ１６の表の面又は裏面を覆うよう塗布された、例えば流動性の接着剤又は粘着性の（部分的に硬化した）接着剤であってよい。塗布後、例えばピックアンドプレースツールを使用して他のチップが該接着層に接合される。或いは、接着層は液体として剥離可能な裏材上に堆積されるか、部分的に硬化した接着層として剥離可能な裏材に接合されてもよい。その後、チップ１６が該接着層に接合される。剥離可能な裏材を除去した後、該接着層は他のチップ又は台板３１と整列され接合されうる。
本開示で使用されているように、「上方へ」、「下方へ」、「垂直に」、及び「水平に」等の用語は指定された構成要素の基準系を指すと理解されるべきであり、通常の重力基準系に合致する必要はない。また、参照の容易さのために、本開示において、方向は超小型電子パッケージ１０内で超小型電子装置１４上に積層された超小型電子装置１２の表の面（例えば図１に示すチップ１６Ｂの表面１８Ｂ）を基準として指定される。通常、「上向きの」又は「から上方への」と称される方向は超小型電子装置１２の表の面に直交し離れる方向を指す。「下向きの」と称される方向は超小型電子装置１２の表の面に直交し上向き方向と反対の方向を指す。「垂直な」方向は超小型電子装置１２の表の面に直交する方向を指す。基準点の「上方」という用語はその基準点の上方の点を指し、基準点の「下方」という用語はその基準点の下方の点を指す。任意の個々の構成要素の「最上部」はその構成要素の上向き方向に最も遠い点又は点群を指し、任意の構成要素の「底部」という用語はその構成要素の下向き方向に最も遠い点又は点群を指す。
超小型電子装置１２において、チップ１６Ｂは、チップ１６Ｂの端２４Ｂからチップ１６Ａの端２４Ａまで延びる表面部２２を除くチップ１６Ａの表の面１８Ａを覆う。両方のチップ１６の端２４の反対側の端２６同士は垂直に整列されている場合も、そうでない場合もある。１つの実施形態では、チップ１６Ａ及び１６Ｂは、チップ１６Ａの表の面１８Ａの両部分２２がそれぞれチップ１６Ｂの端２４Ｂと２６Ｂを超えて延びるよう構成され積層されていてもよい。
チップ１６内の回路又は他の導電性要素（不図示）に電気的に接続された複数の素子／チップコンタクト２８が、積層されたチップのうちチップ１６Ａの表の面１８Ａの部分２２及びチップ１６Ｂの表の面１８Ｂにおいて露出していてよい。
本開示で使用されているように、電気的に伝導性の部分は、表面、例えば半導体チップの上面を形成する誘電体層の表面において、該金属製部分が該表面に塗布されたコンタクト又はボンディング材料に接触可能な場合、「露出している」と考えることが出来る。従って、誘電体の表面から突出するか又は誘電体の表面と同じ高さの金属製部分は、該表面に露出している。一方、誘電体内の誘電体の表面まで延在する穴の中に配置又は整列された引っ込んだ導電性部分も該表面に露出している。
例えば半導体チップ上のコンタクト２８は、アルミニウム又は銅を含み、サブミクロン寸法の露出した表の面を有する。コンタクト２８の表の面は、コンタクト２８を後の処理の間、例えば後述するようにチップの表の面を覆う誘電材料にレーザ光をあてる際に発生しうる損傷から保護する金属又は他の導電材料で覆われ、一方、該コンタクトはパッケージの他の電気的に伝導性の材料又は要素に該コンタクトを覆う該導電材料を介して電気的に接続される。２０１１年８月１日に出願された米国特許出願第１３／１９５，１８７号を参照されたい。この出願を引用することにより本明細書の一部となすものとする。
図２を参照すると、超小型電子装置１２の製造の一段階において、封止剤の層３０が、表面１８Ａのチップ１６Ｂの端２６Ａから延びる非被覆部分２２と、チップ１６Ａ及び１６Ｂの端２４及び２６と、チップ１６Ｂの裏面２０Ｂの非被覆部分とを覆って形成されてよい。外部環境から被封止要素を保護する封止層は誘電材料又は樹脂を含んでもよい。１つの実施形態では、封止層は成形プロセスにより形成されてよい。この成形プロセスはチップ１６Ａの裏面２０Ａから同一平面上を延びる封止層３０の平らな上面３２を形成する。また、該封止層はチップ１６Ｂの表の面１８Ｂから同一平面上を延びる平らな裏面３４を形成してもよい。台板３１は、封止層の形成の次に、例えば研磨、エッチング、又は類似の手法で除去されてもよい。これにより封止層で覆われ露出した面を有する積層されたチップ１６を備えた超小型電子装置１２が得られる。
封止層３０がチップ１６Ａのコンタクト２８Ａを覆って形成された１つの実施形態では、製造の次の段階は、裏面３４から封止層３０を貫通してチップ１６Ａの表の面の部分２２に向かう穴３６の形成を含む。チップ１２Ａの表の面１８Ａの部分２２においてコンタクト２８Ａを覆う導電材料は穴３６内で露出している。
穴３６はチップから離れる垂直又は概ね垂直な軸に沿って延在する。図３Ａを参照すると、穴３６は裏面３４において略円形の上端３８とチップ１６Ａのコンタクト２８Ａに隣接した略円形の下端４０とを有する略円錐形又は円筒形をしていてもよい。別の実施形態では、穴３６は約２５ミクロンの平均直径又は幅を有してもよい。この穴の上端の直径又は幅と下端の直径又は幅との差は約５〜１０ミクロンであってよい。幾つかの例では、穴の下端の幅は上端の幅より小さくてもよい。別の例では、穴の下端の幅は上端の幅と同じであってよい。
別の実施形態では、穴３６は超小型電子装置１２のチップの表の面に概ね平行に延びるスロットの形態であってもよい。
１つの実施形態では、穴３６は、例えばレーザ、打ち抜き、又はエッチングを使用する除去により封止層に形成されてもよい。
別の実施形態では、封止層３０はチップ１６Ａ、１６Ｂの端の形状と、チップ１６Ａの表の面の非被覆部及びチップ１６Ｂの裏面の非被覆部とを有するよう予め形成され、チップ１６Ａの露出した素子コンタクト２８Ａに適合するよう予形成された穴を備えてもよい。封止層３０は軟化した状態で、積層されたチップを覆う適正な位置に取り付け、又は押し付けられて、該穴は垂直方向にコンタクト２８Ａと整列される。１つの実施形態では、このような場合の封止層は、積層されたチップに取り付ける時、部分的に硬化した、例えば「Ｂステージ」材料であってもよい。
製造の次の段階では、図３Ａを参照すると、超小型電子装置コンタクトは、裏面３４から穴３６を通ってコンタクト２８Ａへ延びる金属被覆されたビア４２として形成されてもよい。例えば、ビア４２は裏面３４からコンタクト２８Ａを覆う隆起又は柱（不図示）まで延びてもよい。ビア４２はエッチング可能な導電材料、望ましくは銅、銅系合金、アルミニウム、ニッケル、金等の金属を含んでよい。
１つの実施形態では、ビア４２は堆積、例えば電解金属めっき又は無電解金属めっき、導電材料又は導電性基質材料の蒸着、又はステンシルを使用して導電性ペーストを選択的に穴内に印刷して導電性ビアを形成することで、形成されてよい。別の実施形態では、導電性シード層（不図示）を、導電性ビア４２を形成する前に穴３６内に形成してもよい。
別の実施形態では、封止層３０はチップ１６Ａ及び１６Ｂの表の面と裏面との非被覆部とチップ１６の端とを覆うよう成形プロセスにより成形されてよい。この成形プロセスでは、金型の構造要素又は別の要素、例えばピンが垂直方向にコンタクト２８Ａと整列され穴３６を形成する。図３Ｂを参照すると、封止層の形成の次に、導電材料が穴３６内に堆積され導電性パッド４４を表面部２２に形成してもよい。パッド４４はチップコンタクト２８Ａに電気的に接続された超小型電子装置１２の装置コンタクトとして働きうる。
上記の様々な製造工程を、例えば台板上に配列された複数のチップ積層体に対して実行し、複数の超小型電子装置１２を形成するのが望ましい。複数の装置１２の個々は、該台板の除去前又は後に装置１２間の封止層をダイシングラインに沿って切断することで得られる。超小型電子装置１２は、完成時に該１つ以上のチップを支持するためのパッケージ基板を必要とせずに構築されるのが望ましい。
図４〜図８を参照すると、超小型電子装置１４を形成するために、複数の半導体チップ１６Ｃはそれらの表の面１８Ｃにおいて接着剤の層（不図示）により台板５２の表面５０に接合されてよい。台板５２と接着剤とは超小型電子装置１２の形成について上述したのと類似の材料から形成されてよい。
図５を参照すると、封止剤の層５４が、複数のチップ１６Ｃの裏面２０Ｃと端２４Ｃ及び２６Ｃとを覆って形成されてよい。封止層５４は超小型電子装置１２について上述したのと同様にして類似の材料で成形により形成され、その後、台板５２は除去されてもよい。個々の超小型電子装置１４はそれぞれチップ１６Ｃを備え、両端６４及び６６を有し、封止層をダイシングライン５６に沿って、例えばソーイング又はスクライビングで切断することで得られる。別の実施形態では、個々のパッケージを得るために、台板５２を除去する前に切断されてよい。
１つの実施形態では、封止層５４は成形プロセスにより形成され、端６４と端６６との間を延びる平らな上面５８と、チップ１６Ｃの表の面１８Ｃと同一の面でチップ１６Ｃの端２６Ｃと端６６との間及びチップ１６Ｃの端２４Ｃと端６４との間を延びる平らな裏面６０とが形成される。
図６を参照すると、穴６２が封止層５４を貫通して形成され、全厚みを通って裏面６０から上面５８まで延びている。穴６２は表面５８及び６０に沿って所定の位置にあり、導電性要素がその中を通り、超小型電子装置１４のコンタクトを別の超小型電子装置、例えば下記に詳述するように超小型電子装置１４上に積層されてパッケージ１０を構成する超小型電子装置１２の装置コンタクトに電気的に接続することができる。穴６２は直径約４００ミクロン〜１ｍｍの円筒形スロットの形態であってよい。１つの実施形態では、複数の穴６２は、端２６Ｃと端６６との間の穴と端２４Ｃと端６４との間の穴とを含む。別の実施形態では、穴６２は概ね水平に超小型電子装置１４内を延びるスロットとして構成されてもよい。穴６２は穴３６の形成について上述したのと同様なプロセスを使用して形成されてよい。
図７と、表の面１８Ｃにおいて露出したチップ１６Ｃのコンタクト２８Ｃを含む装置１４の部分の拡大図を例示する図８とを参照すると、誘電材料の層６８がチップ１６Ｃの表の面１８Ｃと、表の面１８Ｃから穴６２まで延びる封止層５４の裏面６０と、２つの穴６２から端６４、６６まで延びる裏面６０とを覆って形成されてもよい。次に、誘電層６８を貫通してコンタクト２８Ｃに向かって延びる穴７０が形成されてコンタクト２８Ｃを覆う導電材料（不図示）を露出させてよい。次に、電気的に伝導性の部分が表の面１８Ｃに形成されてよい。該導電性の部分は、誘電層６８の裏面６９から穴７０を通ってコンタクト２８Ｃを覆う導電材料まで延びる導電性のビア７２と、ビア７２から表面６９に沿って延びる導電性配線７４と、表面６９にあり望ましくは配線７４から延び電気的に接続された端子７６とを含む。端子７６は超小型電子装置１４の裏面７８に露出し、コンタクト２８Ｃに配線７４及びビア７０を介して電気的に接続される。
他の実施形態では、一連の蒸着処理が封止された組立体に対して実行されて、金属被覆されたビアと導電性配線の１つ以上の層と誘電材料の複数の層とを備える導電性構造体が作製される。
また、誘電層６８を貫通して装置１４の封止層５４の裏面６０まで延びる穴８０が形成されてもよい。図示していないが、穴８０は表面６０の長さに沿ってこれと平行に装置１４の別の電気要素、例えば電源（不図示）の正又は負の接地端子まで延びていてもよい。次に、導電性の部分が装置１４の表面７８に形成されてよい。該導電性の部分は、誘電層６８の裏面６９から穴８０を通って封止層５４の裏面６０まで延びる導電性のビア８２と、ビア８２から表面６９に沿って延びる導電性配線８４と、表面６９にあり望ましくは配線８４から延び電気的に接続された端子８６とを含む。１つの実施形態では、ビア８２の導電材料は裏面６０に沿って延びて、電源（不図示）の正及び負の端子を構成する外部コネクタに接続されてもよい。
装置１４の封止層の裏面６０にある配線、ビア、及び端子を構成する導電性部分は、超小型電子装置１２の装置コンタクトを形成するのに使用されるのと同じ上述した材料を含み、フォトリソグラフィ又は類似のプロセスで形成されてもよい。配線は任意の適切な金属堆積手法で形成されてよい。この堆積手法は例えばスパッタリング、無電解又は電解めっき、又は導電性ペースト又は導電性基質材料の印刷又はステンシル印刷を含む。
半田レジスト層（不図示）で誘電層６８の裏面６９の非被覆部を覆い、パターン形成して配線７４、８４を覆ってもよい。これにより端子７６、８６が表面６９に露出される。
また、半田レジスト層の形成の次に、ボンドメタル、半田、導電性ペースト、導電性基質材料などの導電材料の塊８８からなる結合部が、導電性部分の外面の露出部（端子７４、８４として働く）上に形成されてよい。塊８８の幾つかは端子７６、導電性配線７４、及びビア７２を介してチップ１６Ｃのコンタクト２８Ｃに電気的に接続されてよい。また、塊８８の幾つかは端子８６、配線８４、及びビア８２を介して、例えば装置１４に含まれるか関連する他の電子回路に電気的に接続されてもよい。塊８８はボンドメタル、例えば半田、金、スズ、又はインジウムを含んでよい。塊８８の形成の次に、半田レジスト層は除去されてもよい。
超小型電子装置１４は超小型電子装置１２と同様に、完成時に該１つ以上のチップを支持するためのパッケージ基板を必要とせずに構築されるのが望ましい。
従って、上記のように形成された装置１２、１４はテスト可能な装置を構成し、それぞれ含まれるチップの所望の電気的機能性及び動作性を確認するためにテストを実行することが出来る。例えば装置１２のチップ１６Ａは、装置コンタクトとの接続を介して機能テストを実行でき、チップ１６Ｂは、露出したコンタクト２８Ｂとの接続を介して機能テストを実行できる。また、超小型電子装置１４の端子はチップ１６Ｃの機能テストに適切である。従って、各超小型電子装置１２、１４内のチップは、装置を積層し組み立てる前に、必要に応じて他の超小型電子装置と共に機能をテストできるので、下記に説明するパッケージ１０などの共通パッケージを形成できる。
図９〜図１１を参照すると、超小型電子装置１２は望ましくはテスト後、超小型電子装置１４（望ましくはテスト後の）に垂直積層配置で取り付けられてパッケージ１０を形成する。装置１２は裏面３４、１８Ｂからなる裏面９０において装置１４の封止層５４の上面５８に、接着剤の層９２により取り付けられる。接着剤９２は上述した装置１２のチップを互いに接合するのに使用した接着剤に類似していてよい。装置１２、１４は、装置１４の穴６２が装置１２の装置コンタクト、例えばビア４２と露出したチップコンタクト２８Ｂとに垂直に整列された状態で互いに接合される。
図１０を参照すると、積層された装置１２及び１４からなるパッケージ１０は、配線８４の露出部に一端が接続し、他端が超小型電子装置１２のチップの装置コンタクト又はチップコンタクトに接続された結合線１００を有してもよい。例えば、導電性要素間の電気的接続が概略的に例示されたパッケージ１０の底面図である図１２を参照すると、結合線１００Ａは、端子８６Ｃ及び塊８８Ｃに電気的に接続された配線８４Ｃを、装置１２のチップ１６Ａのコンタクト２８Ａに電気的に接続されたビア４２Ａに接続する。また、結合線１００Ｂは、端子８６Ｂ及び塊８８Ｂに電気的に接続された配線８４Ｃを、超小型電子装置コンタクト、例えば装置１２のチップ１６Ａの別のコンタクト２８Ａに電気的に接続されたパッド（不図示）に接続する。また、装置１４の形成に関して上記説明したように、チップ１６Ｃのコンタクト２８Ｃは塊８８Ａに導電性ビア７２Ａ（図１２において不図示）、配線７４Ａ、及び端子７６Ａ（図１２において不図示）を介して電気的に接続される。１つの実施形態では、穴６２と超小型電子装置１４の近接する端６４又は６６との間に位置する端子８６と電気的に互いに接続された関連する配線、ビア、及び塊８８とは、結合線１００が接続される電源及び接地端子を構成してもよい。一方、穴６２と超小型電子装置１４のチップの近接する端２４又は２６との間に位置する端子８６と電気的に互いに接続された関連する配線、ビア、及び塊８８とは、接続された結合線１００を介して超小型電子装置１２のチップとのデータ交換を可能にする。
１つの実施形態では、結合線１００は、細線の端に露出したワイヤー（通常、金、銅、又は銅合金製）の端を加熱してボールボンドを形成するよう軟化させることで、装置コンタクト、例えばビア４２及び配線８４に圧着により接合され、ベース（不図示）を形成することができる。
或いは、結合線をウエッジ接合により形成できる。ウエッジ接合はワイヤーの端に近い部分を加熱し装置１４の裏面の装置コンタクト及び配線に沿って加圧しながら引っ張ることで形成される。アルミニウム結合線をこの方法で形成できる。このようなプロセスは米国特許第７，３９１，１２１号により詳しく記載されている。この特許の開示内容全体を引用することにより本明細書の一部となすものとする。
図１１を参照すると、封止層１０２が、穴６２内と穴６２に隣接した封止層５４の裏面６０の非被覆部を覆って形成され、結合線１００を封止してもよい。封止層１０２はエポキシ材料を含んでもよい。
別の実施形態では、図１３を参照すると、超小型電子パッケージ２００は装置１４と類似の構成を有する超小型電子装置２１４と装置１２と類似の構成を有する超小型電子装置２１２とを含み、装置２１４の上に垂直方向に装置２１２が積層されていてよい。パッケージ２００において、装置２１２は、裏面２２０の装置２１４の両端２２４、２２６から延びる両部分２１８上に露出したチップコンタクト２１６を有する。装置２１４は中を結合線が通る貫通する穴を有していない。上述したパッケージ１０と同様に、結合線２３０は装置２１２のコンタクト２１６を覆う導電材料（不図示）から端２２６、２２４を回って配線８４まで延び、配線８４は端子８６を装置２１４内の半導体チップ１６Ｃのチップコンタクト２８Ｃに電気的に接続する。
別の実施形態では、図１４を参照すると、超小型電子パッケージ３００は超小型電子装置３１４の上に垂直方向に積層された上述した超小型電子装置１２を含んでもよい。封止層５４の裏面が装置３１４の裏面３６５を形成し、封止剤がチップコンタクト２８Ｃが配置されたチップ１６の表の面１８Ｃから装置３１４の裏面３６５に延びている点を除いて、装置３１４は上述した超小型電子装置１４と類似の構成を有する。この実施形態では、穴３６２が裏面３６５から装置３１４の厚みを貫通して装置１２の表面３４まで延び、上側の装置１２のチップ１６Ｂのコンタクト２８Ｂに垂直に整列されている。結合線３７０は装置１２の装置コンタクト４４から穴３６２を通って装置３１４の裏面３６５にある配線８４まで延びている。また、結合線３７２はコンタクト２８Ｂから装置３１４の端３２４を回って装置３１４の裏面上の配線８４まで延び、端子８６をチップコンタクト２８Ｂに電気的に接続する。また、結合線３７４はコンタクト２８Ａに電気的に接続された装置コンタクト４４から装置３１４の端３２６を回って延び、装置３１４の裏面上の配線８４に接続することで、端子８６をコンタクト２８Ａに電気的に接続する。
上記した超小型電子パッケージは、図１５に示すように様々な電子システムの構成において使用できる。例えば、本開示の別の実施形態に係るシステム４００は、上記の超小型電子パッケージ４０６と他の電子部品４０８及び４１０とを含む。この図の例では、部品４０８は半導体チップであり、一方、部品４１０は表示画面であるが、任意の他の部品を使用できる。図１５では図の明確さのために追加の部品が２つだけ描かれているが、勿論、システムは任意の数の部品を含んでよい。電子パッケージ又は組立体４０６は上記のパッケージ又は組立体のいずれでもよい。別の変形例では、任意の数の超小型電子パッケージ又は組立体が使用される。超小型電子パッケージ又は組立体４０６と部品４０８及び４１０は破線で概略描いた共通のハウジング４１１に実装され、適宜互いに電気的に接続されて所望の回路を形成する。図に示した代表的なシステムでは、該システムはフレキシブル印刷回路基板等の回路パネル４１２を含み、該回路パネルは部品を互いに接続する多数の導体４１４（図１５では１つだけ描かれている）を含む。しかし、これは単に代表例であり、電気的接続のための任意の適切な構造体を使用できる。ハウジング４１１は、例えば携帯電話又は携帯情報端末で使用可能な種類の携帯ハウジングとして描かれており、表示画面４１０はハウジングの表面に露出している。構造体４０６が撮像チップ等の光感応素子を含む場合、レンズ４１６又は他の光学素子も該構造体に光を導くために設けてもよい。図１５に示す簡略化したシステムは単に代表例であり、通常、固定構造体と見なされるシステム、例えば卓上型コンピュータ、ルーター等を含む他のシステムを上記の構造体を使用して作製することが出来る。
従って、本開示の実施形態は、テスト可能な複数の超小型電子装置を共通のパッケージ内に組み立てる方法を提供する。この共通のパッケージは、回路パネル、回路基板、フレキシブル回路パネル等の外部部品に接続するための共通のパッケージ端子群を有する。各超小型電子装置は１つ以上の半導体チップを含み、超小型電子装置群のうち第１の超小型電子装置の表面に露出する装置コンタクトは、第１の超小型電子装置の１つ以上のチップのチップコンタクト及び第２の超小型電子装置の外面にあるパッケージ端子に電気的に接続される。各超小型電子装置は、完成時に該１つ以上のチップを支持するためのパッケージ基板を必要とせずに構築されうる。装置コンタクトは第１の装置の半導体チップのチップコンタクトから第１の装置の露出した面に沿って少なくとも一方向に離すことができる。該パッケージの超小型電子装置は、ウェハレベル・チップスケールパッケージ（ＷＬＣＳＰ）又はファンアウト・ウェハレベルパッケージ（ＦＯ−ＷＬＰ）の特徴、ワイヤーボンド可能なパッド等の装置コンタクトは、導電材料を１つ以上の半導体チップを含む封止された組立体上に堆積させることで形成される、に類似の特徴を有する可能性がある。例えば、超小型電子装置は再構成されたウェハ又は回路パネルの一部であってもよい。
装置コンタクトは各第１の超小型電子装置における１つ以上の半導体チップの機能テストに適しており、端子は各第２の超小型電子装置における１つ以上の半導体チップの機能テストに適しているので、共通のパッケージ内に１つ以上の第１の超小型電子装置と１つ以上の第２の超小型電子装置とを更に組み立てる前に、第１と第２の超小型電子装置のそれぞれのチップを機能テストすることが出来る。
本発明を特定の実施形態について説明したが、これらの実施形態は本発明の原理と用途を単に例示していることは理解されるべきである。従って、これらの実施形態に多数の変更が加えられる可能性があり、添付の請求項により定義される本発明の思想及び範囲から逸脱することなく他の構成が想到される可能性があることは理解されるべきである。

Claims (30)

  1. 複数の第１のチップコンタクトを有する半導体チップと、前記半導体チップの端に接する封止層と、前記封止層の表面に露出し前記第１のチップコンタクトと電気的に接続された複数の第１の装置コンタクトとを含む第１の超小型電子装置と、
    複数の第２のチップコンタクトを表面に有する半導体チップと、前記半導体チップの端に接し前記端から延びる表面を有する封止層とを含む第２の超小型電子装置であって、該第２の超小型電子装置の前記半導体チップの前記表面と前記封止層の前記表面は該第２の超小型電子装置の外面を形成する第２の超小型電子装置と、
    前記第１の装置コンタクトと電気的に接続された複数の結合線と、
    前記第２の超小型電子装置の前記外面に位置する複数のパッケージ端子であって、（ｉ）前記第１の装置コンタクトに前記結合線を介して電気的に接続されたパッケージ端子と（ｉｉ）前記第２のチップコンタクトに接して形成された金属被覆されたビアと配線とを介して前記第２のチップコンタクトに電気的に接続されたパッケージ端子と
    を備えてなり、
    前記第１の超小型電子装置は、前記第１の超小型電子装置の外面に露出した複数の第１のチップコンタクトを有する第１の半導体チップと、前記第１の超小型電子装置の前記封止層を貫通する導電性ビアを介して第１のチップコンタクトが前記第１の装置コンタクトに接続された第２の半導体チップとを含むことを特徴とする超小型電子パッケージ。
  2. 前記第１の超小型電子装置はメモリ記憶アレイ機能を主に提供するよう構成されていることを特徴とする請求項１に記載の超小型電子パッケージ。
  3. 前記第２の超小型電子装置は論理機能を主に提供するよう構成されていることを特徴とする請求項２に記載の超小型電子パッケージ。
  4. 前記第２の半導体チップの前記第１のチップコンタクトのうち少なくとも１つは、前記第１の超小型電子装置の前記封止層の貫通孔において露出していることを特徴とする請求項１に記載の超小型電子パッケージ。
  5. 前記第１及び第２の半導体チップはメモリ記憶アレイ機能を主に提供するよう構成されていることを特徴とする請求項１に記載の超小型電子パッケージ。
  6. 前記第２の半導体チップが前記第１の半導体チップを部分的に覆うことで、前記第２の半導体チップの前記第１のチップコンタクトが前記第１の半導体チップの端を超えて配置されることを特徴とする請求項５に記載の超小型電子パッケージ。
  7. 前記第１及び第２の半導体チップの前記第１のチップコンタクトは、それぞれ前記第１及び第２の半導体チップの端に隣接して配置されていることを特徴とする請求項５に記載の超小型電子パッケージ。
  8. 前記パッケージ端子に結合された導電性の結合部を更に備えることを特徴とする請求項１に記載の超小型電子パッケージ。
  9. 前記複数の結合線の少なくとも幾つかは、前記第２の超小型電子装置の端を回って延びていることを特徴とする請求項１に記載の超小型電子パッケージ。
  10. 複数の第１のチップコンタクトを有する半導体チップと、前記半導体チップの端に接する封止層と、前記封止層の表面に露出し前記第１のチップコンタクトと電気的に接続された複数の第１の装置コンタクトとを含む第１の超小型電子装置と、
    複数の第２のチップコンタクトを表面に有する半導体チップと、前記半導体チップの端に接し前記端から延びる表面を有する封止層とを含む第２の超小型電子装置であって、該第２の超小型電子装置の前記半導体チップの前記表面と前記封止層の前記表面は該第２の超小型電子装置の外面を形成する第２の超小型電子装置と、
    前記第１の装置コンタクトと電気的に接続された複数の結合線と、
    前記第２の超小型電子装置の前記外面に位置する複数のパッケージ端子であって、（ｉ）前記第１の装置コンタクトに前記結合線を介して電気的に接続されたパッケージ端子と（ｉｉ）前記第２のチップコンタクトに接して形成された金属被覆されたビアと配線とを介して前記第２のチップコンタクトに電気的に接続されたパッケージ端子と
    を備えてなり、
    前記複数の結合線の少なくとも幾つかは、前記第２の超小型電子装置の前記封止層の貫通孔を通って延びていることを特徴とする超小型電子パッケージ。
  11. 前記複数のパッケージ端子の少なくとも幾つかは、前記貫通孔と前記第２の超小型電子装置の端との間に配置されていることを特徴とする請求項１０に記載の超小型電子パッケージ。
  12. 前記複数のパッケージ端子の前記少なくとも幾つかは、電源及び接地端子のうち少なくとも１つを含むことを特徴とする請求項１１に記載の超小型電子パッケージ。
  13. 前記複数のパッケージ端子の少なくとも幾つかは、前記貫通孔と前記第２の超小型電子装置の前記半導体チップの端との間に配置されていることを特徴とする請求項１０に記載の超小型電子パッケージ。
  14. 前記第１の超小型電子装置の前記封止層は、前記半導体チップの、前記第１のチップコンタクトが配置された表面と反対側の表面を覆っていることを特徴とする請求項１に記載の超小型電子パッケージ。
  15. 前記第２の超小型電子装置の前記封止層は、前記半導体チップの、前記第２のチップコンタクトが配置された表面と反対側の表面を覆っていることを特徴とする請求項１に記載の超小型電子パッケージ。
  16. 前記第１及び第２の超小型電子装置のうち少なくとも１つは、前記第１及び第２の超小型電子装置を備える該超小型電子パッケージの形成の前に機能テストが可能であることを特徴とする請求項１に記載の超小型電子パッケージ。
  17. 前記第１及び第２の超小型電子装置のそれぞれは、前記第１及び第２の超小型電子装置を備える該超小型電子パッケージの形成の前に機能テストが可能であることを特徴とする請求項１に記載の超小型電子パッケージ。
  18. 第１の超小型電子装置を第２の超小型電子装置の上に積層するステップであって、
    前記第１の超小型電子装置は、複数の第１のチップコンタクトを有する半導体チップと、前記半導体チップの端に接する封止層と、前記封止層の表面に露出し前記第１のチップコンタクトと電気的に接続された複数の第１の装置コンタクトとを含み、
    前記第２の超小型電子装置は、複数の第２のチップコンタクトを表面に有する半導体チップと、前記第２の超小型電子装置の前記半導体チップの端に接し、前記端から延びる表面を有する封止層とを含み、前記第２の超小型電子装置の前記半導体チップの前記表面と前記封止層の前記表面は前記第２の超小型電子装置の外面を形成している、ステップと、
    次いで前記第１の装置コンタクトを前記第２の超小型電子装置の前記外面に位置する複数のパッケージ端子に電気的に接続する複数の結合線を形成するステップであって、前記パッケージ端子は前記第２のチップコンタクトに接して形成された金属被覆されたビアと配線とを介して前記第２のチップコンタクトに電気的に接続されている、ステップと
    を含んでなり、
    前記第１の超小型電子装置は、前記第１の超小型電子装置の外面に露出した複数の第１のチップコンタクトを有する第１の半導体チップと、前記第１の超小型電子装置の前記封止層を貫通する導電性ビアを介して第１のチップコンタクトが前記第１の装置コンタクトに接続された第２の半導体チップとを含むことを特徴とする超小型電子パッケージの製造方法。
  19. 前記ビアと配線は堆積されることを特徴とする請求項１８に記載の方法。
  20. 前記第１の超小型電子装置はメモリ記憶アレイ機能を主に提供するよう構成されていることを特徴とする請求項１８に記載の方法。
  21. 前記第２の超小型電子装置は論理機能を主に提供するよう構成されていることを特徴とする請求項１８に記載の方法。
  22. 前記第１及び第２の半導体チップはメモリ記憶アレイ機能を主に提供するよう構成されていることを特徴とする請求項１８に記載の方法。
  23. 前記第２の半導体チップが前記第１の半導体チップを部分的に覆うことで、前記第２の半導体チップの前記第１のチップコンタクトが前記第１の半導体チップの端を越えて配置されることを特徴とする請求項１８に記載の方法。
  24. 前記複数の結合線を形成するステップは、前記複数の結合線の少なくとも幾つかが前記第２の超小型電子装置の端を回って延びるよう形成することを特徴とする請求項１８に記載の方法。
  25. 第１の超小型電子装置を第２の超小型電子装置の上に積層するステップであって、
    前記第１の超小型電子装置は、複数の第１のチップコンタクトを有する半導体チップと、前記半導体チップの端に接する封止層と、前記封止層の表面に露出し前記第１のチップコンタクトと電気的に接続された複数の第１の装置コンタクトとを含み、
    前記第２の超小型電子装置は、複数の第２のチップコンタクトを表面に有する半導体チップと、前記第２の超小型電子装置の前記半導体チップの端に接し、前記端から延びる表面を有する封止層とを含み、前記第２の超小型電子装置の前記半導体チップの前記表面と前記封止層の前記表面は前記第２の超小型電子装置の外面を形成している、ステップと、
    次いで前記第１の装置コンタクトを前記第２の超小型電子装置の前記外面に位置する複数のパッケージ端子に電気的に接続する複数の結合線を形成するステップであって、前記パッケージ端子は前記第２のチップコンタクトに接して形成された金属被覆されたビアと配線とを介して前記第２のチップコンタクトに電気的に接続されている、ステップと
    を含んでなり、
    前記複数の結合線を形成するステップは、前記複数の結合線の少なくとも幾つかが前記第２の超小型電子装置の前記封止層の貫通孔を通って延びるよう形成することを特徴とする方法。
  26. 前記第２の超小型電子装置の前記封止層の前記貫通孔は、前記第２の超小型電子装置の前記半導体チップの周りに前記封止層を成形する間に形成されることを特徴とする請求項２５に記載の方法。
  27. 前記貫通孔と同じ構成を有する要素が、前記成形時、前記貫通孔を形成することを特徴とする請求項２６に記載の方法。
  28. 前記第１及び第２の超小型電子装置のうち少なくとも１つを前記積層するステップの前に機能テストすることを更に含んでいることを特徴とする請求項１８に記載の方法。
  29. 前記第１及び第２の超小型電子装置のそれぞれを前記積層するステップの前に機能テストすることを更に含んでいることを特徴とする請求項１８に記載の方法。
  30. 前記第１及び第２の超小型電子装置のうち少なくとも１つは、再構成されたウェハ又は回路パネルであることを特徴とする請求項１８に記載の方法。
JP2014537171A 2011-10-20 2012-10-17 積層された超小型電子装置を有する超小型電子パッケージ及びその製造方法 Active JP6061937B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/277,330 US8723327B2 (en) 2011-10-20 2011-10-20 Microelectronic package with stacked microelectronic units and method for manufacture thereof
US13/277,330 2011-10-20
PCT/US2012/060585 WO2013059297A1 (en) 2011-10-20 2012-10-17 Microelectronic package with stacked microelectronic units and method for manufacture thereof

Publications (3)

Publication Number Publication Date
JP2014531134A JP2014531134A (ja) 2014-11-20
JP2014531134A5 JP2014531134A5 (ja) 2015-12-03
JP6061937B2 true JP6061937B2 (ja) 2017-01-18

Family

ID=47215738

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014537171A Active JP6061937B2 (ja) 2011-10-20 2012-10-17 積層された超小型電子装置を有する超小型電子パッケージ及びその製造方法

Country Status (6)

Country Link
US (4) US8723327B2 (ja)
EP (1) EP2769412B1 (ja)
JP (1) JP6061937B2 (ja)
KR (1) KR101904409B1 (ja)
TW (1) TWI463635B (ja)
WO (1) WO2013059297A1 (ja)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8553420B2 (en) 2010-10-19 2013-10-08 Tessera, Inc. Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
US8952516B2 (en) 2011-04-21 2015-02-10 Tessera, Inc. Multiple die stacking for two or more die
US8970028B2 (en) 2011-12-29 2015-03-03 Invensas Corporation Embedded heat spreader for package with multiple microelectronic elements and face-down connection
US9013033B2 (en) * 2011-04-21 2015-04-21 Tessera, Inc. Multiple die face-down stacking for two or more die
US8304881B1 (en) 2011-04-21 2012-11-06 Tessera, Inc. Flip-chip, face-up and face-down wirebond combination package
US8633576B2 (en) 2011-04-21 2014-01-21 Tessera, Inc. Stacked chip-on-board module with edge connector
US8928153B2 (en) 2011-04-21 2015-01-06 Tessera, Inc. Flip-chip, face-up and face-down centerbond memory wirebond assemblies
US8723327B2 (en) * 2011-10-20 2014-05-13 Invensas Corporation Microelectronic package with stacked microelectronic units and method for manufacture thereof
US8709868B2 (en) * 2012-08-23 2014-04-29 Freescale Semiconductor, Inc. Sensor packages and method of packaging dies of differing sizes
US9401338B2 (en) * 2012-11-29 2016-07-26 Freescale Semiconductor, Inc. Electronic devices with embedded die interconnect structures, and methods of manufacture thereof
US9472533B2 (en) * 2013-11-20 2016-10-18 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming wire bondable fan-out EWLB package
TWI649856B (zh) * 2016-05-13 2019-02-01 精材科技股份有限公司 晶片封裝體與其製造方法
CN112117242B (zh) * 2019-06-20 2023-01-31 江苏长电科技股份有限公司 芯片封装结构及其制造方法
KR20210000812A (ko) * 2019-06-25 2021-01-06 삼성전자주식회사 반도체 장치 및 그 제조 방법
US11134575B2 (en) * 2019-09-30 2021-09-28 Gentherm Gmbh Dual conductor laminated substrate

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5422435A (en) 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US5998864A (en) 1995-05-26 1999-12-07 Formfactor, Inc. Stacking semiconductor devices, particularly memory chips
JP3644662B2 (ja) * 1997-10-29 2005-05-11 株式会社ルネサステクノロジ 半導体モジュール
JP3481444B2 (ja) 1998-01-14 2003-12-22 シャープ株式会社 半導体装置及びその製造方法
DE10023823A1 (de) 2000-05-15 2001-12-06 Infineon Technologies Ag Multichip-Gehäuse
US6885106B1 (en) 2001-01-11 2005-04-26 Tessera, Inc. Stacked microelectronic assemblies and methods of making same
TWI322448B (en) * 2002-10-08 2010-03-21 Chippac Inc Semiconductor stacked multi-package module having inverted second package
JP2005353837A (ja) * 2004-06-10 2005-12-22 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
DE102005006333B4 (de) 2005-02-10 2007-10-18 Infineon Technologies Ag Halbleiterbauteil mit mehreren Bondanschlüssen und gebondeten Kontaktelementen unterschiedlicher Metallzusammensetzung und Verfahren zur Herstellung desselben
US20060202317A1 (en) 2005-03-14 2006-09-14 Farid Barakat Method for MCP packaging for balanced performance
US7402911B2 (en) 2005-06-28 2008-07-22 Infineon Technologies Ag Multi-chip device and method for producing a multi-chip device
TWI263313B (en) * 2005-08-15 2006-10-01 Phoenix Prec Technology Corp Stack structure of semiconductor component embedded in supporting board
KR100681263B1 (ko) 2006-01-17 2007-02-09 삼성전자주식회사 반도체 패키지
KR100885419B1 (ko) 2006-04-26 2009-02-24 삼성전자주식회사 적층형 패키지 구조체
US7619901B2 (en) * 2007-06-25 2009-11-17 Epic Technologies, Inc. Integrated structures and fabrication methods thereof implementing a cell phone or other electronic system
US20090001529A1 (en) * 2007-06-27 2009-01-01 Ming Hsun Lee Package stacking using unbalanced molded tsop
US8299626B2 (en) 2007-08-16 2012-10-30 Tessera, Inc. Microelectronic package
KR20090055316A (ko) * 2007-11-28 2009-06-02 삼성전자주식회사 반도체 패키지와, 이를 구비하는 전자 기기 및 반도체패키지의 제조방법
US8531043B2 (en) * 2008-09-23 2013-09-10 Stats Chippac Ltd. Planar encapsulation and mold cavity package in package system
US8026589B1 (en) * 2009-02-23 2011-09-27 Amkor Technology, Inc. Reduced profile stackable semiconductor package
US8169065B2 (en) * 2009-12-22 2012-05-01 Epic Technologies, Inc. Stackable circuit structures and methods of fabrication thereof
US8487421B2 (en) 2011-08-01 2013-07-16 Tessera, Inc. Microelectronic package with stacked microelectronic elements and method for manufacture thereof
US8723327B2 (en) * 2011-10-20 2014-05-13 Invensas Corporation Microelectronic package with stacked microelectronic units and method for manufacture thereof

Also Published As

Publication number Publication date
US8723327B2 (en) 2014-05-13
KR20140085520A (ko) 2014-07-07
TW201322419A (zh) 2013-06-01
US9876002B2 (en) 2018-01-23
US20130099387A1 (en) 2013-04-25
WO2013059297A1 (en) 2013-04-25
US20160035712A1 (en) 2016-02-04
JP2014531134A (ja) 2014-11-20
TWI463635B (zh) 2014-12-01
US20170141094A1 (en) 2017-05-18
EP2769412A1 (en) 2014-08-27
US9583475B2 (en) 2017-02-28
US9165911B2 (en) 2015-10-20
KR101904409B1 (ko) 2018-10-05
US20140212996A1 (en) 2014-07-31
EP2769412B1 (en) 2019-02-20

Similar Documents

Publication Publication Date Title
JP6061937B2 (ja) 積層された超小型電子装置を有する超小型電子パッケージ及びその製造方法
US10170412B2 (en) Substrate-less stackable package with wire-bond interconnect
US8786070B2 (en) Microelectronic package with stacked microelectronic elements and method for manufacture thereof
US7535109B2 (en) Die assembly having electrical interconnect
US8729690B2 (en) Assembly having stacked die mounted on substrate
US7683459B2 (en) Bonding method for through-silicon-via based 3D wafer stacking
JP2010521818A (ja) 半導体デバイスパッケージ化装置、パッケージ化された半導体部品、半導体デバイスパッケージ化装置の製造方法、及び半導体部品の製造方法
KR20130091624A (ko) 반도체 장치 및 그 제조방법
WO2009146587A1 (en) Bongding method for through-silicon-via based 3d wafer stacking
JP2015523740A (ja) 再構成されたウェハレベル超小型電子パッケージ
US8872318B2 (en) Through interposer wire bond using low CTE interposer with coarse slot apertures
US9659848B1 (en) Stiffened wires for offset BVA

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20151016

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20151016

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20160707

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20160715

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160929

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20161118

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20161213

R150 Certificate of patent or registration of utility model

Ref document number: 6061937

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250