TW201322419A - 具有堆疊的微電子單元之微電子封裝及其製造方法 - Google Patents

具有堆疊的微電子單元之微電子封裝及其製造方法 Download PDF

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TW201322419A
TW201322419A TW101138771A TW101138771A TW201322419A TW 201322419 A TW201322419 A TW 201322419A TW 101138771 A TW101138771 A TW 101138771A TW 101138771 A TW101138771 A TW 101138771A TW 201322419 A TW201322419 A TW 201322419A
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Taiwan
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microelectronic
unit
wafer
semiconductor wafer
microelectronic unit
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TW101138771A
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TWI463635B (zh
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Terrence Caskey
Ilyas Mohammed
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Invensas Corp
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Abstract

本發明揭示一種微電子封裝，其可包含一第一微電子單元，該第一微電子單元包含：一半導體晶片，其具有第一晶片接觸件；一囊封劑，其接觸該半導體晶片之一邊緣；及第一單元接觸件，其暴露於該囊封劑之一表面上且與該等第一晶片接觸件電連接。該封裝可包含：一第二微電子單元，其包含在其一表面上具有第二晶片接觸件之一半導體晶片；及一囊封劑，其接觸該第二單元之該晶片之一邊緣且具有遠離該邊緣延伸之一表面。該第二單元之該晶片與該囊封劑之該等表面界定該第二單元之一面。該面上之封裝端子可透過與該等第一單元接觸件電連接之接合線與該等第一單元接觸件電連接以及透過形成為與該等第二晶片接觸件接觸之金屬化通孔及跡線與該等第二晶片接觸件電連接。

Description

具有堆疊的微電子單元之微電子封裝及其製造方法
本申請案之標的係關於一種包含堆疊的微電子單元之微電子封裝及製作該封裝之方法。
半導體晶片係具有安置在正面上、連接至晶片本身之內部電路之接觸件之平坦本體。晶片通常經封裝以形成具有電連接至封裝之接觸件之端子之微電子封裝。封裝之端子隨後可連接至外部微電子組件，諸如電路面板。
通常需要將微電子封裝封裝成「堆疊」配置，即，其中各包含至少一半導體晶片之複數個微電子封裝彼此疊置以節省空間。在堆疊的晶片封裝結構或層疊封裝(「PoP」)中，各自封裝之晶片可經安裝以佔據小於所有晶片之總表面積之表面積。PoP之晶片之減小面積可導致PoP之晶片最終可附接之印刷電路板(「PCB」)上之面積之非常高效利用。
通常，包含在PoP中之微電子封裝具有大至足以允許在封裝接合為堆疊配置以形成PoP前在其晶片接觸件上測試個別封裝之晶片之大小。此外，在一些PoP中，導電結構將各自封裝之晶片之晶片接觸件彼此電互連且此導電結構可具有導致封裝之間之高寄生效應(其非所要)之長度，因此，在製作包含堆疊的微電子單元的微電子封裝之技術中需要進一步改良，該等單元之各者包含微電子元件，諸如半導體晶片，該微電子元件可連接至微電子封裝外部 之微電子組件。
根據本揭示內容之一實施例，微電子封裝可包含第一微電子單元，該第一微電子單元包含：半導體晶片，其具有第一晶片接觸件；囊封劑，其接觸半導體晶片之邊緣；及第一單元接觸件，其暴露於囊封劑之表面上且與第一晶片接觸件電連接。該封裝可包含：第二微電子單元，其包含在其表面上具有第二晶片接觸件之半導體晶片；及囊封劑，其接觸第二微電子單元之半導體晶片之邊緣且具有遠離邊緣延伸之表面，其中第二微電子單元之半導體晶片與囊封劑之表面界定第二微電子單元之面。該封裝亦可包含與第一單元接觸件電連接之接合線。該封裝可進一步包含第二微電子單元之面上之封裝端子，該等封裝端子i)透過接合線與第一單元接觸件電連接及(ii)透過形成為與第二晶片接觸件接觸之金屬化通孔及跡線與第二晶片接觸件電連接。
在本揭示內容之另一實施例中，一種製作微電子封裝之方法可包含將第一微電子單元堆疊至第二微電子單元上。第一微電子單元可包含：半導體晶片，其具有第一晶片接觸件；囊封劑，其接觸半導體晶片之邊緣；及第一單元接觸件，其等暴露於囊封劑之表面上且與第一晶片接觸件電連接。第二微電子單元可包含：半導體晶片，其在其表面上具有第二晶片接觸件；及囊封劑，其接觸第二微電子單元之半導體晶片之邊緣且具有遠離該邊緣延伸之表面，其 中第二微電子單元之半導體晶片與囊封劑之表面界定第二微電子單元之面。該方法可進一步包含形成在第二微電子單元之面上將第一單元接觸件與封裝端子電連接之接合線，其中封裝端子透過形成為與第二晶片接觸件接觸之金屬化通孔及跡線與第二晶片接觸件電連接。
如圖1至圖11所示，包含堆疊的微電子單元12及14(微電子單元之各者包含微電子元件)之微電子封裝10可根據本揭示內容之實施例製作。微電子元件之各者可為半導體晶片、晶圓或類似物。晶片可具體體現為複數個主動裝置(例如，電晶體、二極體等)、複數個被動裝置(例如，電阻器、電容器、電感器等)或主動裝置及被動裝置兩者。通常，至少一晶片具體體現為主動裝置或主動裝置及被動裝置兩者。各晶片可與微電子單元中之其他晶片類型相同或晶片可為不同類型。
在特定實施例中，封裝10中之微電子單元之一者或多者(諸如微電子單元14)可包含組態為具有作為邏輯晶片之主要功能之晶片，例如，尤其是可程式化通用或專用處理器、微控制器、場可程式化閘陣列(「FPGA」)裝置、應用特定積體電路(「ASIC」)、數位信號處理器。在此實施例中，封裝10中之微電子單元之一者或多者(諸如微電子單元12)可包含晶片以具有除邏輯晶片以外之主要功能。舉例而言，具有一或多個邏輯晶片之單元14可與一或多個單元12組合，各單元包含具有主要記憶體功能之一或多個儲 存陣列晶片。此記憶體儲存陣列晶片可包含揮發性記憶體儲存區域，例如動態隨機存取記憶體(「DRAM」)、靜態隨機存取記憶體(「SRAM」)、非揮發性記憶體儲存陣列，諸如快閃記憶體或磁性隨機存取記憶體(「MRAM」)或揮發性儲存陣列與非揮發性儲存陣列之組合。在特定實施例中，封裝10之微電子單元之一者或多者可包含將邏輯功能及實質其他功能例如實質記憶體功能組合在相同晶片上之晶片。
參考圖1至圖2，微電子單元12可包含垂直堆疊的晶片16A及16B。晶片16之各者可具有正面18及與正面18相對之背面20。微電子單元12可形成為一晶片之正面面對另一晶片之背面，且單元12可包含配置為垂直堆疊之多於兩個晶片16。晶片16可藉由黏著劑層(未展示)附著在其等之面對表面上且晶片堆疊中之底部晶片，諸如包含晶片16A及16B之堆疊中之晶片16B亦可藉由黏著劑層(未展示)附著至載板31之表面29。載板31可由介電材料或玻璃形成。黏著劑層可包含晶粒附著黏著劑且可針對柔度、導熱性、對水分或其他污染物之不可滲透性之性質或此等性質之組合而選擇。舉例而言，黏著劑層可為可流動黏著劑或黏性(部分固化)黏著劑，其經施加以疊加於晶片16之正面或背面，隨後諸如使用拾放工具將晶片附著至黏著劑層。或者，黏著劑層可作為液體沈積至可剝離背襯或作為部分固化黏著劑層附著至可剝離背襯，隨後將晶片16附著至黏著劑層。在移除可剝離背襯後，黏著劑層隨後可與另一晶片 或載板31對準及接合。
如本揭示內容中所使用，術語諸如「向上」、「向下」、「垂直」及「水平」應理解為參考所指定元件之參考架構且無需符合正常的重力參考架構。此外，為便於參考，參考堆疊在微電子封裝10中之微電子單元14上方之微電子單元12之「正」面，諸如如圖1所示之晶片16B之表面18B，註明本揭示內容中之方向。通常，稱作「向上」或「上升」之方向應指正交且遠離微電子單元12之正面之方向。稱作「向下」之方向應指正交於微電子單元12之正面且與向上方向相反之方向。「垂直」方向應指正交於單元12之正面之方向。術語參照點「上方」應指參照點向上的一點且術語參照點「下方」應指參照點向下的點。任意個別元件之「頂部」應指在向上方向上延伸最遠之該元件之點或諸點且術語任意元件之「底部」應指在向下方向上延伸最遠之元件之點或諸點。
在微電子單元12中，晶片16B可疊加於晶片16A之正面18A，延伸超過晶片16B之邊緣24B至晶片16A之邊緣24A之正面18A之表面部分22除外。各自晶片16相對於邊緣24之邊緣26可或可不垂直對準。在一實施例中，晶片16A及16B可經組態及堆疊使得晶片16A之正面18A之部分22分別延伸超過晶片16B之邊緣24B及26B。
電連接至晶片16內之電路或其他導電元件(未展示)之元件或晶片接觸件28可暴露於晶片16A之正面18A之部分22上及堆疊的晶片之晶片16B之正面18B上。
如本揭示內容中所使用，若金屬特徵可接達施加至一表面之接觸件或接合材料，則導電特徵可被視作「暴露於」此表面，諸如形成半導體晶片之頂部表面之介電層之表面。因此，從介電層之表面突出或與介電層之表面平齊之金屬特徵暴露於此表面上；而安置在延伸至介電層之表面之介電層中之孔中或與其對準之內凹導電特徵亦暴露於此表面上。
諸如半導體晶片上之接觸件28可包含鋁或銅且具有暴露正面，該暴露正面具有亞微米尺寸。接觸件28之正面可覆蓋有金屬或其他導電材料，該金屬或其他導電材料保護接觸件28在後續處理期間不受損，諸如在如下所述疊加於晶片之正面之介電材料之雷射處理期間可能發生之損壞，同時提供接觸件可透過覆蓋接觸件之導電材料電連接至封裝之其他導電材料或元件。見2011年8月1日申請之美國申請案第13/195,187號，其以參考的方式併入本文中。
參考圖2，在製作微電子單元12之一階段中，一層囊封劑30可形成在遠離晶片16B之邊緣24B延伸之表面18A之未覆蓋部分22、晶片16A及16B之邊緣24及26及晶片16B之背面20B之未覆蓋部分上方。保護囊封組件使其不受外部環境影響之囊封劑可包含介電材料或樹脂。在一實施例中，囊封劑可藉由模製製程形成，該模製製程形成從晶片16A之背面20A延伸且與晶片16A之背面20A共面之囊封劑30之平坦頂部表面32。此外，囊封劑可形成從晶片16B之正面18B延伸且與晶片16B之正面18B共面之平坦背面34。載板 31可在囊封劑形成後諸如藉由砂磨、蝕刻或類似技術移除以獲得具有堆疊的晶片16之微電子單元12，該等堆疊的晶片16具有由囊封劑覆蓋之暴露表面。
在形成囊封劑30覆蓋晶片16A之接觸件28A之一實施例中，製作之另一階段可包含形成從背面34穿過囊封劑30朝向晶片16A之正面之表面部分22延伸之孔36。覆蓋晶片12A之正面18A之部分22上之接觸件28A之導電材料暴露於孔36內。
孔36可沿著垂直軸或大致垂直軸遠離晶片延伸。參考圖3A，孔36可為大致錐形或圓柱形，其具有背面34上之大致圓形頂端38及鄰近晶片16A之接觸件28A之大致圓形底端40。在另一實施例中，孔36可具有大約25微米之平均直徑或寬度。孔之頂端之直徑或寬度與底端之直徑或寬度之間之差值可為大約5至10微米。在一些實例中，孔之底端之寬度可小於頂端之寬度；在另一實例中，孔之底端寬度可與頂端寬度相同。
在另一實施例中，孔36可為大致平行於微電子單元12之晶片之正面延伸之槽之形式。
在一實施例中，孔36可藉由諸如使用雷射焼蝕、打孔或蝕刻囊封劑而形成在囊封劑中。
在另一實施例中，囊封劑30可預製為具有晶片16A、16B之邊緣及晶片16A之正面及晶片16B之背面之未覆蓋部分之形狀且亦包含經圖案化以匹配晶片16A之暴露元件接觸件28A之預形成孔。處於軟化狀態之囊封劑30隨後可附 著至例如壓進堆疊的晶片上方之位置使得孔與接觸件28A垂直對準。在一實施例中，在此情況中之囊封劑可在附著至堆疊的晶片時部分固化，例如「B階段」材料。
在製作之另一階段中，參考圖3A，微電子單元接觸件可形成為從背面34穿過孔36朝向接觸件28A延伸之金屬化通孔42。舉例而言，通孔42可從背面34延伸至覆蓋接觸件28A之凸塊或支柱(未展示)。通孔42可包含可蝕刻導電材料，其按需要為金屬，諸如銅、以銅為基礎之合金、鋁、鎳及金。
在一實施例中，通孔42可藉由沈積，舉例而言，電解或無電金屬電鍍、導電材料或導電基質材料之沈積或藉由使用模板將導電膏選擇性地印刷至孔中以形成導電通孔而形成。在另一實施例中，導電晶種層(未展示)可在導電通孔42形成前形成在孔36中。
在一替代實施例中，囊封劑30可藉由模製製程分別模製在晶片16A及16B之正面及背面之未覆蓋部分及晶片16之邊緣上方，其中模具之結構元件或另一元件(諸如銷)在模製製程期間與接觸件28A垂直對準且形成孔36。參考圖3B，在囊封劑形成後，導電材料可沈積至孔36中以在表面部分22上形成導電墊44，該導電墊44可充當電連接至晶片接觸件28A之微電子單元12之單元接觸件。
上述不同製作步驟按需要可在配置在諸如載板上以形成微電子單元12之複數個晶片堆疊上進行且提供單元12之個別一者可藉由在載板移除之前或之後適當地在囊封劑之切 割道上切斷單元之間之囊封劑而獲得。可按需要構造微電子單元12，而無需所完成之微電子單元中之封裝基板用於支撐至少一晶片。
參考圖4至圖8，為了形成微電子單元14，半導體晶片16C可藉由黏著劑層(未展示)而在其正面18C上附著至載板52之表面50。載板52及黏著劑可由如上所述用於形成微電子單元12之類似材料形成。
參考圖5，囊封劑54之層可形成在晶片16C之背面20C及邊緣24C及26C上方。囊封劑54可類似於上文針對微電子單元12所述包含材料及藉由模製而形成且隨後可移除載板52。各包含晶片16C且具有相對邊緣64及66之個別微電子單元14隨後可藉由切斷例如，諸如藉由沿著切割道56鋸切或刻劃囊封劑而形成。在替代實施例中，可在移除載板52前執行切斷以獲得個別封裝。
在一實施例中，囊封劑54可藉由模製製程形成，該模製製程形成在邊緣64與66之間延伸之囊封劑54之平坦頂部表面58及與晶片16C之正面18C共面且在晶片16C之邊緣26C與邊緣66之間及晶片16C之邊緣24C與邊緣64之間延伸之平坦背面60。
參考圖6，孔62可形成為穿過囊封劑54，從背面60延伸穿過其整個厚度至頂部表面58。如下文詳細描述，孔62處於沿著表面58及60之預定位置上以允許導電元件穿過其中且將微電子單元14之接觸件電連接至另一微電子單元之微電子單元接觸件，諸如堆疊在微電子單元14上以形成封裝 10之微電子單元12。孔62可為直徑係大約400微米至1 mm之圓柱形槽之形式。在一實施例中，孔62可包含邊緣26C與邊緣66之間之孔及邊緣24C與邊緣64之間之孔。在另一實施例中，孔62可組態為在微電子單元14中大致水平延伸之槽。孔62可使用類似於上述用於形成孔36之製程之製程形成。
參考圖解說明包含暴露於正面18C上之晶片16C之接觸件28C之單元14之一部分之放大圖之圖7及圖8，一層介電材料68可形成在晶片16C之正面18C上方、遠離正面18C延伸至孔62之囊封劑54之背面60上方以及從孔62延伸至邊緣64及66之背面60上方。孔70隨後可形成為朝向接觸件28C延伸穿過介電層68以暴露覆蓋接觸件28C之導電材料(未展示)。導電部分隨後可形成在正面18C上，該正面18C包含從介電層68之背面69延伸穿過孔70至覆蓋接觸件28C之導電材料之導電通孔72、沿著表面69遠離通孔72延伸之導電跡線74及在表面69上電連接跡線74且按需要從跡線74延伸之端子76。端子76位於微電子單元14之背面78上或暴露於微電子單元14之背面78上且透過跡線74及通孔70電連接至接觸件28C。
在其他實施例中，可在囊封總成上執行一系列沈積以建立導電結構，該導電結構包含金屬化通孔及一層、兩層或更多層導電跡線及介電材料層。
此外，孔80可形成為延伸穿過介電層68至單元14之囊封劑54之背面60。雖然圖中未展示，但是孔80可平行於及沿 著表面60之長度延伸至單元14之另一電元件，諸如電源供應器(未展示)之正極或負極接地端子。導電部分隨後可形成在單元14之表面78上，該表面78包含從介電層68之背面69延伸穿過孔80至囊封劑54之背面60之導電通孔82、沿著表面69遠離通孔82延伸之導電跡線84及在表面69上電連接跡線84且按需要從跡線84延伸之端子86。在一實施例中，通孔82之導電材料可沿著背面60延伸以連接至構成電源供應器(未展示)之正極端子及負極端子之外部連接器。
在單元14之囊封劑之背面60上形成跡線、通孔及端子之導電部分可包含用於形成如上所述之微電子單元12之單元接觸件之相同材料且可藉由光微影圖案化或類似製程形成。跡線可藉由任何適當金屬沈積技術形成，舉例而言，該金屬沈積技術可包含導電膏或導電基質材料之濺鍍、無電或電解電鍍或印刷或模印。
阻焊層(未展示)可疊加於介電層68之背面69之未覆蓋部分且經圖案化以覆蓋跡線74及84，藉此使端子76及86暴露於表面69上。
此外，在阻焊層形成後，可包含導電材料(諸如接合金屬、焊料、導電膏、導電基質材料或類似材料)之塊體88之接合單元可形成在導電部分之外表面之暴露部分上充當端子74及84。因此，塊體88之一些可透過端子76、導電跡線74及通孔72電互連至晶片16C之接觸件28C。此外，塊體88之一些可透過端子86、跡線84及通孔82與舉例而言包含在單元14中或與單元14相關聯的其他電子電路電互連。 塊體88可包含接合金屬，諸如焊料、金、錫或銦。在塊體形成後，可移除阻焊層。
類似於微電子單元12，可構造微電子單元14，而無需所完成之微電子單元中之封裝基板用於將至少一晶片支撐於其中。
因此，如上所述形成之單元12及14可構成可測試單元，該等可測試單元之各者可經歷測試以確認其中所含之晶片之所要電功能性及可操作性。舉例而言，單元12之晶片16A可藉由與單元接觸件互連而經歷功能測試，且晶片16B可藉由與暴露的接觸件28B互連而經歷功能測試。此外，微電子單元14之端子適於晶片16C之功能測試。因此，如下文所述，可在將單元組裝為堆疊配置前視需要用其他電子單元對各微電子單元12及14中之晶片進行功能測試以形成共同封裝，諸如封裝10。
參考圖9至圖11，微電子單元12按需要在其測試之後可附著至微電子單元14，亦按需要在其測試之後呈垂直堆疊配置以形成封裝10。單元12可藉由黏著劑92之層在其背面90(其由背面34及18B形成)上附著至單元14之囊封劑54之頂部表面58之部分。如上所述，黏著劑92可類似於用於將單元12之晶片彼此附著之黏著劑。單元12及14彼此附著，單元14之孔62與單元12之單元接觸件(諸如通孔42及暴露之晶片接觸件28B)垂直對準。
參考圖10，由堆疊的單元12及14形成之封裝10可具有形成為在一端上連接至跡線84之暴露部分及在另一端上連接 至微電子單元12之晶片之單元接觸件或晶片接觸件之接合線100。舉例而言，進一步參考作為具有示意圖解說明之導電元件之間之電連接之封裝10之底部平面圖之圖12，接合線100A可將電連接至端子86C及塊體88C之跡線84C與通孔42A連接，通孔42A與單元12之晶片16A之接觸件28A電連接。此外，接合線100B可將跡線84C(其電連接至端子86B及塊體88B)與微電子單元接觸件，諸如與單元12之晶片16A之不同接觸件28A電連接至之墊(未展示)連接。此外，如上文關於單元14之形成所述，晶片16C之接觸件28C可透過導電通孔72A(圖12中未展示)、跡線74A及端子76A(圖12中亦未展示)與塊體88A電連接。在一實施例中，相關聯之跡線、通孔及塊體88彼此電連接之端子86(其等定位在微電子單元14之孔62與相鄰邊緣64或66之間)可構成接合線100所電連接之電力及接地端子，而相關聯之跡線、通孔及塊體88彼此電連接之端子86(其等介於微電子單元14之晶片之孔62與相鄰邊緣24或26之間)經由電連接至其上之接合線100提供與微電子單元12之晶片之資料交換。
在一實施例中，接合線100可藉由加熱暴露於毛細管之一端上之線(該線通常為金、銅或銅合金)之末端而施加以軟化該末端使得其形成至單元接觸件之球形接合，諸如通孔42及跡線84(在被壓至其上時)，形成基極(未展示)。
或者，接合線可藉由楔形接合形成。楔形接合藉由加熱線鄰近其末端之一部分並用施加至其上之壓力在單元14之 背面上將其沿著單元接觸件及跡線拖曳而形成。鋁接合線可以此方式形成。此一製程進一步描述於美國專利第7,391,121號中，其揭示內容全文以引用的方式併入本文中。
參考圖11，囊封劑102可形成在鄰近孔62及孔62中之囊封劑54之背面60之未覆蓋表面部分上方以囊封接合線100。囊封劑102可包含環氧材料。
在另一實施例中，參考圖13，微電子封裝200可包含具有與單元14類似之構造之微電子單元214及具有與單元12類似之構造之微電子單元212，其中單元212垂直堆疊於單元214之頂部上。在封裝200中，單元212具有暴露於單元212之背面220之部分218上遠離單元214之相對邊緣224及226延伸之晶片接觸件216使得單元214不包含延伸穿過其中及接合線延伸穿過之孔。類似於上述封裝10中，接合線230圍繞邊緣226及224從覆蓋單元212之接觸件216之導電材料(未展示)延伸至跡線84且跡線84將端子86電連接至單元214內之半導體晶片16C之晶片接觸件28C。
在另一實施例中，參考圖14，微電子封裝300可包含如上所述垂直堆疊於微電子單元314上之微電子單元12。單元314具有與如上所述之微電子單元14類似之構造，囊封劑54之背面形成單元314之背面365且囊封劑材料從晶片16之正面18C(晶片接觸件28C安置在該正面18C上)延伸至單元314之背面365除外。此外，在本實施例中，孔362從背面365延伸穿過單元314之厚度至單元12之表面34，與疊加 單元12之晶片16B之接觸件28B垂直對準。接合線370從單元12之單元接觸件44延伸穿過孔362至單元314之背面365上之跡線84。此外，接合線372從接觸件28B圍繞單元314之邊緣324延伸至單元314之背面上之跡線84以將端子86與晶片接觸件28B電連接。此外，接合線374從電連接至接觸件28A之單元接觸件44圍繞單元314之邊緣326延伸以連接單元314之背面上之跡線84及因此將端子86與接觸件28A電連接。
如圖15所示，上述微電子封裝可用於構造多種電子系統。舉例而言，根據本揭示內容之另一實施例之系統400包含如上文結合其他電子組件408及410所述之微電子封裝406。在所描繪之實例中，組件408為半導體晶片，而組件410為顯示螢幕，但可使用任何其他組件。當然，雖然為方便闡釋在圖15中僅描繪兩個額外組件，但是系統可包含任意數量之此等組件。微電子封裝或總成406可為上述封裝或總成之任意者。在另一變體中，可使用任意數量之此等微電子封裝或總成。微電子封裝或總成406及組件408及410安裝在以虛線示意描繪之共同外殼411中且根據需要彼此電互連以形成所要電路。在所示之例示性系統中，系統包含電路面板412，諸如可撓印刷電路板且電路面板包含將組件彼此互連之許多導體414，在圖15中僅描繪其中一個。但是此僅係例示性的；可使用用於製作電連接之任意適當結構。外殼411描繪為例如蜂巢式電話或個人數位助理中可使用之類型之可攜式外殼且螢幕410暴露於外殼之 表面上。在結構406包含光敏元件(諸如成像晶片)的情況下，亦可提供透鏡416或其他光學裝置以將光安排路線至結構。再次，圖15中所示之簡化系統僅為例示性；其他系統，包含通常被視作固定結構之系統，諸如桌上型電腦、路由器及類似物可使用上述結構製作。
因此，本揭示內容之實施例提供將可測試微電子單元組裝在共同封裝中之方式，該共同封裝具有用於互連至外部組件，諸如電路面板，例如電路板或可撓電路面板之一組共同封裝端子。各微電子單元包含至少一半導體晶片且暴露於微電子單元之第一微電子單元之表面上之單元接觸件與第一單元之至少一晶片之晶片接觸件及位於堆疊第一單元及第二單元之第二微電子單元之面上之封裝端子電連接。可構造各微電子單元，而無需所完成之微電子單元中之封裝基板用於支撐至少一晶片。單元接觸件可沿著第一微電子單元之暴露表面在至少一方向上從第一單元之半導體晶片之晶片接觸件移位。封裝之微電子單元可具有類似於晶圓級晶片尺寸封裝(「WLCSP」)或扇出晶圓級封裝(「FO-WLP」)之特徵，其中諸如線可接合墊之單元接觸件藉由將導電材料沈積至其中具有至少一半導體晶片之囊封總成上而形成。舉例而言，微電子單元可為重組之晶圓或電路面板之部分。
單元接觸件適用於各第一微電子單元中之至少一半導體晶片之功能測試且端子適用於各第二微電子單元中之至少一半導體晶片之功能測試，使得第一微電子單元及第二微 電子單元之各者中之晶片可在將第一微電子單元之一者或多者連同第二微電子單元之一者或多者進一步組裝在共同封裝中之前進行功能測試。
雖然本文中參考特定實施例描述本發明，但是應瞭解此等實施例僅闡釋本發明之原理及應用。所以，應瞭解可對闡釋性實施例進行多種修改且可設計其他配置而不脫離如隨附申請專利範圍所定義之本發明之精神及範疇。
10‧‧‧微電子封裝
12‧‧‧微電子單元
14‧‧‧微電子單元
16A‧‧‧晶片
16B‧‧‧晶片
16C‧‧‧半導體晶片
18A‧‧‧正面
18B‧‧‧正面
18C‧‧‧正面
20A‧‧‧背面
20B‧‧‧背面
20C‧‧‧背面
22‧‧‧未覆蓋部分
24A‧‧‧邊緣
24B‧‧‧邊緣
24C‧‧‧邊緣
26A‧‧‧邊緣
26B‧‧‧邊緣
26C‧‧‧邊緣
28A‧‧‧接觸件
28B‧‧‧接觸件
28C‧‧‧接觸件
29‧‧‧表面
30‧‧‧囊封劑
31‧‧‧載板
32‧‧‧頂部表面
34‧‧‧背面
36‧‧‧孔
38‧‧‧頂端
40‧‧‧底端
42‧‧‧通孔
42A‧‧‧通孔
44‧‧‧導電墊
50‧‧‧表面
52‧‧‧載板
54‧‧‧囊封劑
56‧‧‧切割道
58‧‧‧頂部表面
60‧‧‧平坦背面
62‧‧‧孔
64‧‧‧邊緣
66‧‧‧邊緣
68‧‧‧介電材料
69‧‧‧背面
70‧‧‧孔
72‧‧‧通孔
74‧‧‧跡線
74A‧‧‧跡線
76‧‧‧端子
78‧‧‧背面
80‧‧‧孔
82‧‧‧通孔
84‧‧‧跡線
84C‧‧‧跡線
86‧‧‧端子
86B‧‧‧端子
86C‧‧‧端子
88‧‧‧塊體
88A‧‧‧塊體
88B‧‧‧塊體
88C‧‧‧塊體
90‧‧‧背面
92‧‧‧黏著劑
100‧‧‧接合線
100A‧‧‧接合線
100B‧‧‧接合線
102‧‧‧囊封劑
200‧‧‧微電子封裝
212‧‧‧微電子單元
214‧‧‧微電子單元
216‧‧‧晶片接觸件
218‧‧‧部分
220‧‧‧背面
224‧‧‧邊緣
226‧‧‧邊緣
230‧‧‧接合線
300‧‧‧微電子封裝
314‧‧‧微電子單元
324‧‧‧邊緣
326‧‧‧邊緣
362‧‧‧孔
365‧‧‧背面
370‧‧‧接合線
372‧‧‧接合線
374‧‧‧接合線
400‧‧‧系統
406‧‧‧微電子封裝
408‧‧‧電子組件
410‧‧‧電子組件
411‧‧‧外殼
412‧‧‧電路面板
414‧‧‧導體
416‧‧‧透鏡
圖1至圖2係圖解說明根據本揭示內容之一實施例之製作包含垂直堆疊的微電子元件之微電子單元之方法中之階段之圖解截面圖。
圖3A係根據本揭示內容之一實施例之包含垂直堆疊的微電子元件之微電子單元之部分之圖解截面圖。
圖3B係根據本揭示內容之另一實施例之包含垂直堆疊的微電子元件之微電子單元之部分之圖解截面圖。
圖4至圖8係圖解說明根據本揭示內容之一實施例之製作具有封裝端子之微電子單元之方法中之階段之圖解截面圖。
圖9至圖11係圖解說明根據本揭示內容之一實施例之製作具有使用圖1至圖3及圖4至圖8之方法形成之堆疊的微電子單元之微電子封裝之方法中之步驟之圖解截面圖。
圖12係圖11之封裝之仰視平面圖。
圖13係根據本揭示內容之另一實施例之微電子封裝之圖解截面圖。
圖14係根據本揭示內容之另一實施例之微電子封裝之圖 解截面圖。
圖15係根據本揭示內容之一實施例之系統之示意描繪。
10‧‧‧微電子封裝
12‧‧‧微電子單元
14‧‧‧微電子單元
60‧‧‧平坦背面
88B‧‧‧塊體
88C‧‧‧塊體
100A‧‧‧接合線
100B‧‧‧接合線
102‧‧‧囊封劑

Claims (32)

  1. 一種微電子封裝，其包括：一第一微電子單元，其包含：一半導體晶片，其具有第一晶片接觸件；一囊封劑，其接觸該半導體晶片之一邊緣；及第一單元接觸件，其等暴露於該囊封劑之一表面上且與該等第一晶片接觸件電連接；一第二微電子單元，其包含：一半導體晶片，其在其一表面上具有第二晶片接觸件；一囊封劑，其接觸該第二微電子單元之該半導體晶片之一邊緣且具有遠離該邊緣延伸之一表面，該第二微電子單元之該半導體晶片與該囊封劑之該等表面界定該第二微電子單元之一面；接合線，其等與該等第一單元接觸件電連接；及封裝端子，其等位於該第二微電子單元之該面上(i)透過該等接合線與該等第一單元接觸件電連接及(ii)透過形成為與該等第二晶片接觸件接觸之金屬化通孔及跡線與該等第二晶片接觸件電連接。
  2. 如請求項1之微電子封裝，其中該第一微電子單元經組態以主要提供記憶體儲存陣列功能。
  3. 如請求項2之微電子封裝，其中該第二微電子單元經組態以主要提供邏輯功能。
  4. 如請求項1之微電子封裝，其中該第一微電子單元包含：一第一半導體晶片，其具有暴露於該第一微電子單元之一面上之第一晶片接觸件；及一第二半導體晶片，其第一晶片接觸件透過延伸穿過該第一微電子單元之該 囊封劑之導電通孔與該等第一單元接觸件連接。
  5. 如請求項4之微電子封裝，其中該第二半導體晶片之該等第一晶片接觸件之至少一者暴露於該第一微電子單元之該囊封劑中之一穿透開口上。
  6. 如請求項4之微電子封裝，其中該第一半導體晶片及該第二半導體晶片經組態以主要提供記憶體儲存陣列功能。
  7. 如請求項6之微電子封裝，其中該第二半導體晶片部分疊加於該第一半導體晶片使得該第二半導體晶片之該等第一晶片接觸件安置為超過該第一半導體晶片之一邊緣。
  8. 如請求項6之微電子封裝，其中該第一半導體晶片及該第二半導體晶片之該等第一晶片接觸件分別安置於該第一半導體晶片及該第二半導體晶片之鄰近邊緣。
  9. 如請求項1之微電子封裝，其進一步包括接合至該等封裝端子之導電接合單元。
  10. 如請求項1之微電子封裝，其中該等接合線之至少一些圍繞該第二微電子單元之一邊緣延伸。
  11. 如請求項1之微電子封裝，其中該等接合線之至少一些延伸穿過該第二微電子單元之該囊封劑中之一穿透開口。
  12. 如請求項11之微電子封裝，其中該等封裝端子之至少一些安置於該第二微電子單元之該開口與一邊緣之間。
  13. 如請求項12之微電子封裝，其中該等端子之至少一些包 含電力端子或接地端子之至少一者。
  14. 如請求項11之微電子封裝，其中該等封裝端子之至少一些安置於該第二微電子單元之該半導體晶片之該開口與一邊緣之間。
  15. 如請求項1之微電子封裝，其中該第一微電子單元之該囊封劑疊加於其中相對於該等第一晶片接觸件所安置之一表面之該半導體晶片之一表面。
  16. 如請求項1之微電子封裝，其中該第二微電子單元之該囊封劑疊加於其中相對於該等第二晶片接觸件所安置之該表面之該半導體晶片之一表面。
  17. 如請求項1之微電子封裝，其中在具有該第一微電子單元及該第二微電子單元之該微電子封裝形成之前可對該第一微電子單元或該第二微電子單元之至少一者進行功能測試。
  18. 如請求項1之微電子封裝，其中在具有該第一微電子單元及該第二微電子單元之該微電子封裝形成之前可對該第一微電子單元或該第二微電子單元之各者進行功能測試。
  19. 一種製作一微電子封裝之方法，其包括：將一第一微電子單元堆疊至一第二微電子單元上，該第一微電子單元包含：一半導體晶片，其具有第一晶片接觸件；一囊封劑，其接觸該半導體晶片之一邊緣；及第一單元接觸件，其等暴露於該囊封劑之一表面上且與該等第一晶片接觸件電連接， 該第二微電子單元，其包含：一半導體晶片，其在其一表面上具有第二晶片接觸件；一囊封劑，其接觸該第二微電子單元之該半導體晶片之一邊緣且具有遠離此邊緣延伸之一表面，該第二微電子單元之該半導體晶片與該囊封劑之該等表面界定該第二微電子單元之一面；及形成將該等第一單元接觸件與該第二微電子單元之該面上之封裝端子電連接之接合線，該等封裝端子透過形成為與該等第二晶片接觸件接觸之金屬化通孔及跡線與該等第二晶片接觸件電連接。
  20. 如請求項19之方法，其中沈積該等通孔及該等跡線。
  21. 如請求項19之方法，其中該第一微電子單元經組態以主要提供記憶體儲存陣列功能。
  22. 如請求項19之方法，其中該第二微電子單元經組態以主要提供邏輯功能。
  23. 如請求項19之方法，其中該第一微電子單元包含：一第一半導體晶片，其具有暴露於該第一微電子單元之一面上之第一晶片接觸件；及一第二半導體晶片，其第一晶片接觸件透過延伸穿過該第一微電子單元之該囊封劑之導電通孔與該等第一單元接觸件連接。
  24. 如請求項23之方法，其中該第一半導體晶片及該第二半導體晶片經組態以主要提供記憶體儲存陣列功能。
  25. 如請求項23之方法，其中該第二半導體晶片部分疊加於該第一半導體晶片使得該第二半導體晶片之該等第一晶片接觸件安置為超過該第一半導體晶片之一邊緣。
  26. 如請求項19之方法，其中形成接合線之該步驟形成該等接合線之至少一些以圍繞該第二微電子單元之一邊緣延伸。
  27. 如請求項19之方法，其中形成接合線之該步驟形成延伸穿過該第二微電子單元之該囊封劑中之一穿透開口之該等接合線之至少一些。
  28. 如請求項27之方法，其中在圍繞該第二微電子單元之該半導體晶片模製該囊封劑期間形成該第二微電子單元之該囊封劑中之該穿透開口。
  29. 如請求項28之方法，其中具有與該穿透開口相同之組態之一元件在該模製期間形成該穿透開口。
  30. 如請求項19之方法，其進一步包括在該堆疊步驟之前對該第一微電子單元或該第二微電子單元之至少一者進行功能測試。
  31. 如請求項19之方法，其進一步包括在該堆疊步驟之前對該第一微電子單元或該第二微電子單元之各者進行功能測試。
  32. 如請求項19之方法，其中該第一微電子單元或該第二微電子單元之至少一者具有一重組晶圓或電路面板。
TW101138771A 2011-10-20 2012-10-19 具有堆疊的微電子單元之微電子封裝及其製造方法 TWI463635B (zh)

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