CN101320702B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN101320702B
CN101320702B CN2008101100054A CN200810110005A CN101320702B CN 101320702 B CN101320702 B CN 101320702B CN 2008101100054 A CN2008101100054 A CN 2008101100054A CN 200810110005 A CN200810110005 A CN 200810110005A CN 101320702 B CN101320702 B CN 101320702B
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hole
insulating film
mentioned
semiconductor
semiconductor substrate
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Chinese (zh)
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CN101320702A (zh
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川下道宏
吉村保广
田中直敬
内藤孝洋
赤沢隆
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NEC Corp
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Renesas Technology Corp
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    • H10W20/023—
    • H10P72/74—
    • H10W20/0234—
    • H10W20/0242—
    • H10W20/2125—
    • H10W90/00—
    • H10P72/7436—
    • H10W70/60—
    • H10W72/00—
    • H10W72/01225—
    • H10W72/072—
    • H10W72/07227—
    • H10W72/241—
    • H10W72/244—
    • H10W72/251—
    • H10W72/29—
    • H10W72/923—
    • H10W72/932—
    • H10W72/9415—
    • H10W72/942—
    • H10W90/297—
    • H10W90/722—
    • H10W90/724—

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CN2008101100054A 2007-06-06 2008-06-02 半导体器件及其制造方法 Expired - Fee Related CN101320702B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007-150289 2007-06-06
JP2007150289A JP4937842B2 (ja) 2007-06-06 2007-06-06 半導体装置およびその製造方法
JP2007150289 2007-06-06

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CN101320702A CN101320702A (zh) 2008-12-10
CN101320702B true CN101320702B (zh) 2010-07-21

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US (2) US7973415B2 (enExample)
JP (1) JP4937842B2 (enExample)
KR (1) KR101191492B1 (enExample)
CN (1) CN101320702B (enExample)
TW (1) TW200908152A (enExample)

Families Citing this family (79)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7791199B2 (en) 2006-11-22 2010-09-07 Tessera, Inc. Packaged semiconductor chips
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
WO2008108970A2 (en) 2007-03-05 2008-09-12 Tessera, Inc. Chips having rear contacts connected by through vias to front contacts
JP2009021433A (ja) * 2007-07-12 2009-01-29 Fujikura Ltd 配線基板及びその製造方法
CN103178032B (zh) * 2007-07-31 2017-06-20 英闻萨斯有限公司 使用穿透硅通道的半导体封装方法
US20090212381A1 (en) * 2008-02-26 2009-08-27 Tessera, Inc. Wafer level packages for rear-face illuminated solid state image sensors
US20100053407A1 (en) * 2008-02-26 2010-03-04 Tessera, Inc. Wafer level compliant packages for rear-face illuminated solid state image sensors
TWI365528B (en) * 2008-06-27 2012-06-01 Advanced Semiconductor Eng Semiconductor structure and method for manufacturing the same
KR100997788B1 (ko) * 2008-06-30 2010-12-02 주식회사 하이닉스반도체 반도체 패키지
US7872332B2 (en) 2008-09-11 2011-01-18 Micron Technology, Inc. Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods
JP2010080897A (ja) * 2008-09-29 2010-04-08 Panasonic Corp 半導体装置及びその製造方法
JP4803844B2 (ja) 2008-10-21 2011-10-26 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体パッケージ
JP5455538B2 (ja) * 2008-10-21 2014-03-26 キヤノン株式会社 半導体装置及びその製造方法
JP5434306B2 (ja) * 2008-10-31 2014-03-05 日本電気株式会社 半導体装置及び半導体装置の製造方法
DE102008058001B4 (de) * 2008-11-19 2024-08-29 Austriamicrosystems Ag Verfahren zur Herstellung eines Halbleiterbauelementes und Halbleiterbauelement
US8513119B2 (en) * 2008-12-10 2013-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bump structure having tapered sidewalls for stacked dies
US20100171197A1 (en) * 2009-01-05 2010-07-08 Hung-Pin Chang Isolation Structure for Stacked Dies
US8198172B2 (en) * 2009-02-25 2012-06-12 Micron Technology, Inc. Methods of forming integrated circuits using donor and acceptor substrates
JP5201048B2 (ja) * 2009-03-25 2013-06-05 富士通株式会社 半導体装置とその製造方法
EP2460180B1 (en) 2009-07-30 2020-02-19 QUALCOMM Incorporated System-in packages
US8791549B2 (en) 2009-09-22 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside interconnect structure connected to TSVs
KR101096223B1 (ko) * 2009-10-30 2011-12-22 주식회사 하이닉스반도체 단일측벽콘택에 연결된 매립비트라인을 갖는 반도체장치 제조 방법
US8399180B2 (en) * 2010-01-14 2013-03-19 International Business Machines Corporation Three dimensional integration with through silicon vias having multiple diameters
US8415238B2 (en) 2010-01-14 2013-04-09 International Business Machines Corporation Three dimensional integration and methods of through silicon via creation
US8304863B2 (en) * 2010-02-09 2012-11-06 International Business Machines Corporation Electromigration immune through-substrate vias
US8541886B2 (en) * 2010-03-09 2013-09-24 Stats Chippac Ltd. Integrated circuit packaging system with via and method of manufacture thereof
US8466059B2 (en) 2010-03-30 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-layer interconnect structure for stacked dies
US8324511B1 (en) 2010-04-06 2012-12-04 Amkor Technology, Inc. Through via nub reveal method and structure
JP5423572B2 (ja) 2010-05-07 2014-02-19 セイコーエプソン株式会社 配線基板、圧電発振器、ジャイロセンサー、配線基板の製造方法
US8202797B2 (en) 2010-06-22 2012-06-19 Stats Chippac Ltd. Integrated circuit system with recessed through silicon via pads and method of manufacture thereof
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8440554B1 (en) 2010-08-02 2013-05-14 Amkor Technology, Inc. Through via connected backside embedded circuit features structure and method
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
JP2012064891A (ja) * 2010-09-17 2012-03-29 Toshiba Corp 半導体装置及びその製造方法
US8487445B1 (en) 2010-10-05 2013-07-16 Amkor Technology, Inc. Semiconductor device having through electrodes protruding from dielectric layer
KR101059490B1 (ko) 2010-11-15 2011-08-25 테세라 리써치 엘엘씨 임베드된 트레이스에 의해 구성된 전도성 패드
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
US8390130B1 (en) 2011-01-06 2013-03-05 Amkor Technology, Inc. Through via recessed reveal structure and method
US20120193809A1 (en) * 2011-02-01 2012-08-02 Nanya Technology Corp. Integrated circuit device and method for preparing the same
JP5870493B2 (ja) * 2011-02-24 2016-03-01 セイコーエプソン株式会社 半導体装置、センサーおよび電子デバイス
JP2012231096A (ja) * 2011-04-27 2012-11-22 Elpida Memory Inc 半導体装置及びその製造方法
US8900994B2 (en) 2011-06-09 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for producing a protective structure
US8796822B2 (en) * 2011-10-07 2014-08-05 Freescale Semiconductor, Inc. Stacked semiconductor devices
US9076664B2 (en) 2011-10-07 2015-07-07 Freescale Semiconductor, Inc. Stacked semiconductor die with continuous conductive vias
US8710670B2 (en) 2011-12-14 2014-04-29 Stats Chippac Ltd. Integrated circuit packaging system with coupling features and method of manufacture thereof
JP5810921B2 (ja) * 2012-01-06 2015-11-11 凸版印刷株式会社 半導体装置の製造方法
CN103240481B (zh) * 2012-02-08 2016-07-06 西安永电电气有限责任公司 焊接工装件
KR102342629B1 (ko) 2012-04-18 2021-12-22 싸이노슈어, 엘엘씨 피코초 레이저 장치 및 그를 사용한 표적 조직의 치료 방법
CN103633013B (zh) * 2012-08-21 2016-06-29 中芯国际集成电路制造(上海)有限公司 硅通孔封装结构的形成方法
US9076715B2 (en) 2013-03-12 2015-07-07 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for connecting dies and methods of forming the same
US20150187701A1 (en) 2013-03-12 2015-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Devices and Methods of Manufacture Thereof
JP5826782B2 (ja) * 2013-03-19 2015-12-02 株式会社東芝 半導体装置の製造方法
US9082757B2 (en) * 2013-10-31 2015-07-14 Freescale Semiconductor, Inc. Stacked semiconductor devices
US9257641B2 (en) * 2013-11-08 2016-02-09 Industrial Technology Research Institute Via structure, memory array structure, three-dimensional resistance memory and method of forming the same
US9412719B2 (en) 2013-12-19 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC interconnect apparatus and method
US10056353B2 (en) 2013-12-19 2018-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC interconnect apparatus and method
US9425150B2 (en) 2014-02-13 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-via interconnect structure and method of manufacture
US20150348874A1 (en) 2014-05-29 2015-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC Interconnect Devices and Methods of Forming Same
US9543257B2 (en) 2014-05-29 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC interconnect devices and methods of forming same
US9455158B2 (en) * 2014-05-30 2016-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC interconnect devices and methods of forming same
US9449914B2 (en) 2014-07-17 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated circuits with redistribution lines
US9842825B2 (en) * 2014-09-05 2017-12-12 Taiwan Semiconductor Manufacturing Company, Ltd. Substrateless integrated circuit packages and methods of forming same
US10002653B2 (en) 2014-10-28 2018-06-19 Nxp Usa, Inc. Die stack address bus having a programmable width
US10297666B2 (en) * 2015-04-14 2019-05-21 Mitsubishi Electric Corporation Semiconductor device with a well region
JP6648544B2 (ja) * 2016-02-08 2020-02-14 三菱電機株式会社 半導体装置
JP6443362B2 (ja) * 2016-03-03 2018-12-26 株式会社デンソー 半導体装置
CN108257934B (zh) * 2016-12-29 2021-02-19 联华电子股份有限公司 焊垫开口及熔丝焊接口的制作方法与焊垫开口结构
JP6888493B2 (ja) * 2017-09-14 2021-06-16 三菱電機株式会社 半導体装置の製造方法
CN107946239A (zh) * 2017-12-06 2018-04-20 德淮半导体有限公司 硅通孔互连结构及其形成方法
KR102576062B1 (ko) 2018-11-07 2023-09-07 삼성전자주식회사 관통 실리콘 비아를 포함하는 반도체 소자 및 그 제조 방법
CN111128872B (zh) * 2019-12-30 2022-11-25 上海集成电路研发中心有限公司 一种接触孔及其制作方法
US11393791B2 (en) * 2020-01-28 2022-07-19 Micron Technology, Inc. Three-dimensional stacking semiconductor assemblies with near zero bond line thickness
TWI740716B (zh) * 2020-11-16 2021-09-21 旭德科技股份有限公司 基板結構

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3724110B2 (ja) * 1997-04-24 2005-12-07 三菱電機株式会社 半導体装置の製造方法
JP3481444B2 (ja) 1998-01-14 2003-12-22 シャープ株式会社 半導体装置及びその製造方法
JP3918350B2 (ja) 1999-03-05 2007-05-23 セイコーエプソン株式会社 半導体装置の製造方法
JP3731453B2 (ja) * 2000-07-07 2006-01-05 セイコーエプソン株式会社 半導体装置の製造方法
JP3910493B2 (ja) 2002-06-14 2007-04-25 新光電気工業株式会社 半導体装置及びその製造方法
JP2004296894A (ja) * 2003-03-27 2004-10-21 Seiko Epson Corp 半導体装置の製造方法
JP2005093486A (ja) * 2003-09-12 2005-04-07 Seiko Epson Corp 半導体装置の製造方法及び半導体装置
JP4441328B2 (ja) * 2004-05-25 2010-03-31 株式会社ルネサステクノロジ 半導体装置及びその製造方法
KR100570514B1 (ko) * 2004-06-18 2006-04-13 삼성전자주식회사 웨이퍼 레벨 칩 스택 패키지 제조 방법
JP4373866B2 (ja) 2004-07-16 2009-11-25 三洋電機株式会社 半導体装置の製造方法
JP4376715B2 (ja) * 2004-07-16 2009-12-02 三洋電機株式会社 半導体装置の製造方法
JP4365750B2 (ja) * 2004-08-20 2009-11-18 ローム株式会社 半導体チップの製造方法、および半導体装置の製造方法
JP2006114545A (ja) 2004-10-12 2006-04-27 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP4547247B2 (ja) 2004-12-17 2010-09-22 ルネサスエレクトロニクス株式会社 半導体装置
JP4409455B2 (ja) 2005-01-31 2010-02-03 株式会社ルネサステクノロジ 半導体装置の製造方法
JP2006222138A (ja) 2005-02-08 2006-08-24 Matsushita Electric Works Ltd 貫通電極の形成方法
JP4551255B2 (ja) 2005-03-31 2010-09-22 ルネサスエレクトロニクス株式会社 半導体装置
JP4694305B2 (ja) * 2005-08-16 2011-06-08 ルネサスエレクトロニクス株式会社 半導体ウエハの製造方法
JP4380718B2 (ja) * 2007-03-15 2009-12-09 ソニー株式会社 半導体装置の製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP特开2005-93486A 2005.04.07

Also Published As

Publication number Publication date
JP2008305897A (ja) 2008-12-18
KR101191492B1 (ko) 2012-10-15
US8324736B2 (en) 2012-12-04
TWI357111B (enExample) 2012-01-21
KR20080107288A (ko) 2008-12-10
US20090014843A1 (en) 2009-01-15
US7973415B2 (en) 2011-07-05
CN101320702A (zh) 2008-12-10
TW200908152A (en) 2009-02-16
US20110233773A1 (en) 2011-09-29
JP4937842B2 (ja) 2012-05-23

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