JP6648544B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6648544B2 JP6648544B2 JP2016021641A JP2016021641A JP6648544B2 JP 6648544 B2 JP6648544 B2 JP 6648544B2 JP 2016021641 A JP2016021641 A JP 2016021641A JP 2016021641 A JP2016021641 A JP 2016021641A JP 6648544 B2 JP6648544 B2 JP 6648544B2
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- 239000004065 semiconductor Substances 0.000 title claims description 101
- 239000002184 metal Substances 0.000 claims description 93
- 239000000758 substrate Substances 0.000 claims description 70
- 230000000149 penetrating effect Effects 0.000 claims description 9
- 239000012466 permeate Substances 0.000 claims 1
- 238000000034 method Methods 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000012267 brine Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- HPALAKNZSZLMCH-UHFFFAOYSA-M sodium;chloride;hydrate Chemical compound O.[Na+].[Cl-] HPALAKNZSZLMCH-UHFFFAOYSA-M 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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Description
図1は、本発明の実施の形態1に係る半導体装置を示す断面図である。図2は、本発明の実施の形態1に係る半導体装置を示す下面図である。
図5は、本発明の実施の形態2に係る半導体装置を示す断面図である。図6は、本発明の実施の形態2に係る半導体装置を示す下面図である。本実施の形態では、実施の形態1の金属膜4の代わりに、第1及び第2の金属膜6,7が半導体基板1の裏面、ビアホール2の側壁2a及び電極3の下面に順に積層されている。第1の金属膜6は第2の金属膜7より薄い。裏面側の金属膜のうち、第2の金属膜7が導電性を担う主要な層であり、裏面側の金属膜の厚さの過半を占める。第2の金属膜7を電気めっきで形成する場合の給電層として第1の金属膜6を無電解めっきにより形成する。これに限らず、付着力を確保するためのバリア層として第1の金属膜6を形成してもよい。形成方法もスパッタ法等の他の方法も適用可能である。
図7及び図8は、本発明の実施の形態3に係る半導体装置を示す断面図である。図8は図7とは別の方向から見た断面である。実施の形態1の開口5の代わりに、ビアホール2の側壁2aにおいて金属膜4に開口9が設けられている。開口9においてビアホール2の側壁2aが露出している。
図9は、本発明の実施の形態4に係る半導体装置を示す断面図である。本実施の形態では、実施の形態3の金属膜4の代わりに、第1及び第2の金属膜6,7が半導体基板1の裏面、ビアホール2の側壁2a及び電極3の下面に順に積層されている。第1の金属膜6は第2の金属膜7より薄い。ビアホール2の側壁2aにおいて第2の金属膜7に開口10が設けられている。開口10において第1の金属膜6が露出している。これにより、実施の形態2,3と同様の効果を得ることができる。
図10は、本発明の実施の形態5に係る半導体装置を示す平面図である。図11は図10のI−IIに沿った断面図である。実施の形態1の開口5の代わりに、ビアホール2上において電極3に開口11が設けられている。開口11において金属膜4が露出している。
図12は、本発明の実施の形態6に係る半導体装置を示す断面図である。実施の形態5の電極3の代わりに、第1及び第2の電極12,13がビアホール2を塞ぐように半導体基板1の表面に順に積層されている。第1の電極12は第2の電極13より薄い。ビアホール2上において第2の電極13に開口14が設けられている。開口14において第1の電極12が露出している。これにより、実施の形態2,5と同様の効果を得ることができる。
Claims (6)
- 裏面から表面まで貫通するビアホールが設けられた半導体基板と、
前記ビアホールを塞ぐように前記半導体基板の前記表面に設けられた電極と、
前記半導体基板の前記裏面、前記ビアホールの側壁及び前記電極の下面に設けられた金属膜とを備え、
前記半導体基板の前記裏面において前記金属膜に開口が設けられ、
前記開口は前記ビアホールの外周の一部のみに接し、
前記開口において前記ビアホールの前記側壁と前記金属膜の界面が露出していることを特徴とする半導体装置。 - 裏面から表面まで貫通するビアホールが設けられた半導体基板と、
前記ビアホールを塞ぐように前記半導体基板の前記表面に設けられた電極と、
前記半導体基板の前記裏面、前記ビアホールの側壁及び前記電極の下面に順に積層された第1及び第2の金属膜とを備え、
前記第1の金属膜は前記第2の金属膜より薄くガスを透過する厚さであり、
前記半導体基板の前記裏面において前記第2の金属膜に開口が設けられ、
前記開口は前記ビアホールの外周の一部のみに接し、
前記開口において前記ビアホールの前記側壁上の前記第1の金属膜と前記第2の金属膜の界面が露出していることを特徴とする半導体装置。 - 裏面から表面まで貫通するビアホールが設けられた半導体基板と、
前記ビアホールを塞ぐように前記半導体基板の前記表面に設けられた電極と、
前記半導体基板の前記裏面、前記ビアホールの側壁及び前記電極の下面に設けられた金属膜とを備え、
前記ビアホールの前記側壁において前記金属膜に開口が設けられ、
前記開口において前記ビアホールの前記側壁が露出していることを特徴とする半導体装置。 - 裏面から表面まで貫通するビアホールが設けられた半導体基板と、
前記ビアホールを塞ぐように前記半導体基板の前記表面に設けられた電極と、
前記半導体基板の前記裏面、前記ビアホールの側壁及び前記電極の下面に順に積層された第1及び第2の金属膜とを備え、
前記第1の金属膜は前記第2の金属膜より薄くガスを透過する厚さであり、
前記ビアホールの前記側壁において前記第2の金属膜に開口が設けられ、
前記開口において前記第1の金属膜が露出していることを特徴とする半導体装置。 - 裏面から表面まで貫通するビアホールが設けられた半導体基板と、
前記ビアホールを塞ぐように前記半導体基板の前記表面に設けられた電極と、
前記半導体基板の前記裏面、前記ビアホールの側壁及び前記電極の下面に設けられた金属膜とを備え、
前記ビアホール上において開口が前記電極に設けられ前記金属膜には設けられず、
前記開口において前記金属膜が露出していることを特徴とする半導体装置。 - 裏面から表面まで貫通するビアホールが設けられた半導体基板と、
前記ビアホールを塞ぐように前記半導体基板の前記表面に順に積層された第1及び第2の電極と、
前記半導体基板の前記裏面、前記ビアホールの側壁及び前記第1の電極の下面に設けられた金属膜とを備え、
前記第1の電極は前記第2の電極より薄くガスを透過する厚さであり、
前記ビアホール上において前記第2の電極に開口が設けられ、
前記開口において前記第1の電極が露出していることを特徴とする半導体装置。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016021641A JP6648544B2 (ja) | 2016-02-08 | 2016-02-08 | 半導体装置 |
TW105136224A TWI624908B (zh) | 2016-02-08 | 2016-11-08 | 半導體裝置 |
US15/345,560 US10020246B2 (en) | 2016-02-08 | 2016-11-08 | Semiconductor device |
DE102017200415.0A DE102017200415B4 (de) | 2016-02-08 | 2017-01-12 | Halbleitervorrichtung |
KR1020170009471A KR101898373B1 (ko) | 2016-02-08 | 2017-01-20 | 반도체 장치 |
CN201710069042.4A CN107045978B (zh) | 2016-02-08 | 2017-02-08 | 半导体装置 |
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JP2016021641A JP6648544B2 (ja) | 2016-02-08 | 2016-02-08 | 半導体装置 |
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JP6648544B2 true JP6648544B2 (ja) | 2020-02-14 |
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JP (1) | JP6648544B2 (ja) |
KR (1) | KR101898373B1 (ja) |
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CN107527823A (zh) * | 2017-08-24 | 2017-12-29 | 通富微电子股份有限公司 | 一种封装基板的制备方法及封装基板 |
CN107564879A (zh) * | 2017-08-24 | 2018-01-09 | 通富微电子股份有限公司 | 一种扇出型封装器件 |
CN107611043A (zh) * | 2017-08-24 | 2018-01-19 | 通富微电子股份有限公司 | 一种扇出型封装方法 |
CN107611042B (zh) * | 2017-08-24 | 2021-09-21 | 通富微电子股份有限公司 | 一种扇出型封装方法 |
CN107611112A (zh) * | 2017-08-24 | 2018-01-19 | 通富微电子股份有限公司 | 一种扇出型封装器件 |
CN107481940A (zh) * | 2017-08-24 | 2017-12-15 | 通富微电子股份有限公司 | 一种封装基板的制备方法及封装基板 |
CN107564880A (zh) * | 2017-08-24 | 2018-01-09 | 通富微电子股份有限公司 | 一种扇出型封装器件 |
CN107516638A (zh) * | 2017-08-24 | 2017-12-26 | 通富微电子股份有限公司 | 一种扇出型封装方法 |
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JPS61263284A (ja) * | 1985-05-17 | 1986-11-21 | Nec Corp | 半導体装置 |
JP3443219B2 (ja) * | 1995-11-14 | 2003-09-02 | 株式会社日立製作所 | 半導体集積回路装置およびその製造方法 |
JP3724110B2 (ja) | 1997-04-24 | 2005-12-07 | 三菱電機株式会社 | 半導体装置の製造方法 |
CN1926930B (zh) * | 2004-03-03 | 2011-06-15 | 新光电气工业株式会社 | 电路板制造方法与电路板 |
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US20170229380A1 (en) | 2017-08-10 |
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TWI624908B (zh) | 2018-05-21 |
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