TWI624908B - 半導體裝置 - Google Patents
半導體裝置 Download PDFInfo
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- TWI624908B TWI624908B TW105136224A TW105136224A TWI624908B TW I624908 B TWI624908 B TW I624908B TW 105136224 A TW105136224 A TW 105136224A TW 105136224 A TW105136224 A TW 105136224A TW I624908 B TWI624908 B TW I624908B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 107
- 239000002184 metal Substances 0.000 claims abstract description 99
- 229910052751 metal Inorganic materials 0.000 claims abstract description 99
- 239000000758 substrate Substances 0.000 claims abstract description 73
- 230000000149 penetrating effect Effects 0.000 claims abstract description 9
- 239000011229 interlayer Substances 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000007772 electroless plating Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
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- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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Abstract
介層洞形成後即使加熱也可以得到確保基板表面側與背面側導通的半導體裝置。
半導體基板1中,設置從背面貫通到表面的介層洞2。在半導體基板1的表面上設置電極3,堵住介層洞2。金屬膜4設置在半導體基板1的背面、介層洞2的側壁2a及電極3的下面。半導體基板1的背面在金屬膜4中設置開口5。開口5只連接介層洞2的外周的一部分。開口5中露出介層洞2的側壁2a與金屬膜4的界面A。
Description
本發明係關於設置貫通半導體基板的介層洞的半導體裝置。
取得形成半導體元件的基板表面與其相反側的背面之間的導通的情況下,在半導體基板中設置介層洞,表面側的電極與背面側的金屬膜間經由介層洞互相連接。
製造如此的半導體裝置的情況下,首先,半導體基板的表面上形成電極。其次,研削半導體基板的背面側直到既定的厚度。其次,形成背面的介層洞之處以外,以光阻等遮光,蝕刻半導體基板直到從背面側露出電極。除去.洗淨光罩後,背面、介層洞的側壁及電極的下面形成金屬膜。因為介層洞內露出電極的背面,表面側的電極與背面側的金屬膜接觸。
[專利文件1]專利公開平成10年第303198號公報
由於半導體裝置的高積體化,介層洞也縮小平面
方向的尺寸。所以,形成介層洞之際為了不往水平方向擴大,有必要再提高乾蝕刻的異向性。於是,不往橫方向蝕刻,蝕刻時更強化在介層洞側壁上形成的膜。因此,即使蝕刻後的除去.洗淨,也有除不盡的殘渣殘留在介層洞側壁上。介層洞形成後加熱半導體裝置之際,由於從背面側的金屬膜覆蓋的殘渣產生氣體,半導體基板與金屬膜之間的界面受到壓力。此壓力傳過界面散佈密合強度弱的電極與金屬膜的界面。結果,兩者的連接脫落,有無法取得導通的問題。
本發明係用以解決上述的問題而形成,其目的是介層洞形成後即使加熱也可以得到確保基板表面側與背面側導通的半導體裝置。
根據本發明的半導體裝置,包括:半導體基板,設置從背面貫通到表面的介層洞;電極,設置在上述半導體基板的上述表面上,堵住上述介層洞;以及金屬膜,設置在上述半導體基板的上述背面、上述介層洞的側壁及上述電極的下面;其特徵在於:上述半導體基板的上述背面在上述金屬膜中設置開口,上述開口只連接上述介層洞的外周的一部分,上述開口中露出上述介層洞的上述側壁與上述金屬膜的界面。
本發明中,從殘渣產生的氣體傳過半導體基板與金屬膜之間的界面,到達設置在金屬膜中的開口。開口連接介層洞的外周,開口中露出介層洞的側壁與金屬膜的界面。因此,傳過界面的氣體排出到半導體裝置之外。結果,因為可以
防止電極與金屬膜的連接脫落,介層洞形成後即使加熱也可以得到確保基板表面側與背面側導通。
1‧‧‧半導體基板
2‧‧‧介層洞
2a‧‧‧側壁
3‧‧‧電極
4‧‧‧金屬膜
5‧‧‧開口
6‧‧‧第1金屬膜
7‧‧‧第2金屬膜
8‧‧‧開口
9‧‧‧開口
10‧‧‧開口
11‧‧‧開口
12‧‧‧第1電極
13‧‧‧第2電極
14‧‧‧開口
A‧‧‧界面
B‧‧‧界面
[第1圖]係顯示根據本發明第一實施例的半導體裝置的剖面圖;[第2圖]係顯示根據本發明第一實施例的半導體裝置的下面圖;[第3圖]係顯示根據比較例的半導體裝置的剖面圖;[第4圖]係顯示根據比較例的半導體裝置的剖面圖;[第5圖]係顯示根據本發明第二實施例的半導體裝置的剖面圖;[第6圖]係顯示根據本發明第二實施例的半導體裝置的下面圖;[第7圖]係顯示根據本發明第三實施例的半導體裝置的剖面圖;[第8圖]係顯示根據本發明第三實施例的半導體裝置的剖面圖;[第9圖]係顯示根據本發明第四實施例的半導體裝置的剖面圖;[第10圖]係顯示根據本發明第五實施例的半導體裝置的平面圖;[第11圖]係沿著第10圖的I~II的剖面圖;以及[第12圖]係顯示根據本發明第六實施例的半導體裝置的
剖面圖。
關於根據本發明的實施例的半導體裝置,參照圖面說明。相同或對應的構成要素附上相同的符號,可能省略重複的說明。
第1圖係顯示根據本發明第一實施例的半導體裝置的剖面圖。第2圖係顯示根據本發明第一實施例的半導體裝置的下面圖。
半導體基板1的表面上形成電晶體等的半導體元件(未圖示)。設置從半導體基板1的背面貫通到表面的介層洞2。在此,以介層洞2內露出的半導體基板1的內壁為介層洞2的側壁2a。又,對半導體基板1的背面從垂直方向所見的平視圖中介層洞2的平面形狀是圓形,但橢形等的形狀也可以。
在半導體基板1的表面上設置電極3,堵住介層洞2。金屬膜4設置在半導體基板1的背面、介層洞2的側壁2a及電極3的下面。金屬膜4與電極3的下面直接接觸,半導體基板1的表面側與背面側導通。介層洞2的側壁2a與金屬膜4直接接觸構成界面A。對半導體基板1的背面從垂直方向所見的平視圖中,介層洞2的外周全周設置介層洞2的側壁2a與金屬膜4的界面A。
半導體基板1的背面在金屬膜4中設置開口5。對半導體基板1的背面從垂直方向所見的平視圖中,開口5只連接介層洞2的外周的一部分。開口5中露出介層洞2的側壁2a
與金屬膜4的界面A。又,開口5連接介層洞2的外周全部的話,半導體基板1的背面的金屬膜4與介層洞2的側壁2a的金屬膜4分離,半導體基板1的表面側與背面側變得不導通。
接著,說明本實施例的半導體裝置的製造方法。首先,半導體基板1的表面上形成電極3。其次,研削半導體基板1的背面側至既定的厚度。其次,形成背面的介層洞2之處以光阻等遮光,蝕刻半導體基板1直到電極3從背面側露出。除去.洗淨光罩後,半導體基板1的背面側全面,即基板背面、介層洞2的側壁2a及電極3的下面形成金屬膜4。其次,除去切割線的金屬膜4之際,除了形成開口5之處與切割線以光阻覆蓋背面。此狀態下,以蝕刻金屬膜4不蝕刻半導體基板1的液體處理,形成開口5。
接著,將本實施例的效果與比較例比較說明。第3、4圖,係顯示根據比較例的半導體裝置的剖面圖。比較例,不在金屬膜4中設置開口5。介層洞2形成後,加熱半導體裝置之際,由於從背面側的金屬膜4覆蓋的殘渣產生的氣體,半導體基板1與金屬膜4之間的界面A受到壓力。此壓力傳過界面A散佈密合強度弱的電極3與背面側的金屬膜4的界面A。結果,兩者的連接脫落,有無法取得導通的問題。
相對於此,本發明的實施例,從殘渣產生的氣體傳過半導體基板1與金屬膜4之間的界面A,到達金屬膜4中設置的開口5。開口5連接介層洞2的外周,開口5中露出介層洞2的側壁2a與金屬膜4之間的界面A。因此,傳過界面A的氣體排出半導體裝置外。結果,因為可以防止電極3與金屬
膜4的連接脫落,介層洞2形成後,即使加熱也可以確保基板表面側與背面側的導通。
第5圖係顯示根據本發明第二實施例的半導體裝置的剖面圖,第6圖係顯示根據本發明第二實施例的半導體裝置的下面圖。本實施例中,取代第一實施例的金屬膜4,第1及第2金屬膜6、7依序層壓在半導體基板1的背面、介層洞2的側壁2a及電極3的下面。第1金屬膜6比第2金屬膜7薄。背面側的金屬膜中,第2金屬膜7係負擔導電性的主要層,佔背面側的金屬膜厚度的過半。第2金屬膜7作為電鍍形成時的供電層,以無電解電鍍形成第1金屬膜6。不限定於此,作為用以確保附著力的阻障層,形成第1金屬膜6也可以。形成方法也可以應用濺鍍法等其他的方法。
半導體基板1的背面在第2金屬膜7中設置開口8。開口8只連接介層洞2的外周的一部分。本實施例的開口8,也與第一實施例相同,除了形成開口8之處與切割線以光阻覆蓋背面的狀態下,蝕刻金屬膜4形成。
開口8中露出介層洞2在側壁2a上的第1金屬膜6與第2金屬膜7的界面B。又,與此界面B大致相同的位置上也配置介層洞2的側壁2a與第1金屬膜6的界面A,存在於開口8內留下的第1金屬膜6的下側。
本實施例中,從殘渣產生的氣體傳過半導體基板1與第1金屬膜6之間的界面A,到達第2金屬膜7中設置的開口8。開口8內以第1金屬膜6覆蓋,但因為第1金屬膜6薄,
氣體透過第1金屬膜6排出半導體裝置之外。結果,介層洞2形成後即使加熱也可以確保基板表面側與背面側的導通。
又,由於留下薄的第1金屬膜6,因為不必2次蝕刻主要的第2金屬膜7與薄的第1金屬膜6,可以簡化步驟。又,以無電解電鍍形成金屬膜時,以無電解電鍍形成後,因為必須加熱處理,容易受氣體的影響。所以,如本實施例,在第2金屬膜7中設置開口8的效果很大。
第7及8圖係顯示根據本發明第三實施例的半導體裝置的剖面圖。第8圖係從不同於第7圖的另外的方向所見的剖面。取代第一實施例的開口5,介層洞2的側壁2a在金屬膜4中設置開口9。開口9中露出介層洞2的側壁2a。
本實施例中,介層洞2的側壁2a形成錐狀,使可以照相製版。在半導體基板1的背面側全面形成金屬膜4後,除了形成開口9之處以光阻覆蓋背面。在此狀態下,以蝕刻金屬膜4不蝕刻半導體基板1的液體處理,形成開口9。
藉此,與第一實施例相同,從殘渣產生的氣體傳過界面A,從開口9排出半導體裝置之外。結果,介層洞2形成後,即使加熱也可以確保基板表面側與背面側的導通。又,雖然開口9的形成方法變複雜,但藉由介層洞2內設置開口9,比起第一實施例氣體更容易排出。
第9圖係顯示根據本發明第四實施例的半導體裝置的剖面圖。本實施例中,取代第三實施例的金屬膜4,第1及第2金
屬膜6、7依序層壓在半導體基板1的背面、介層洞2的側壁2a及電極3的下面。第1金屬膜6比第2金屬膜7薄。介層洞2的側壁2a在第2金屬膜7中設置開口10。開口10中露出第1金屬膜6。藉此,可以得到與第二、三實施例相同的效果。
第10圖係顯示根據本發明第五實施例的半導體裝置的平面圖。第11圖係沿著第10圖的I~II的剖面圖。取代第一實施例的開口5,介層洞2上在電極3中設置開口11。開口11中露出金屬膜4。
本實施例中,形成介層洞2及金屬膜4後,除了形成開口11之處,以光阻覆蓋基板表面,背面側的金屬膜4作為阻絕層,蝕刻表面側的電極3形成開口11。
因此,與第一實施例相同,從殘渣產生的氣體傳過界面A,從開口11排出半導體裝置之外。結果,介層洞2形成後即使加熱也可以確保基板表面側與背面側的導通。又,雖然開口11的形成方法變複雜,但藉由介層洞2上設置開口11,比起第一實施例氣體更容易排出。
第12圖係顯示根據本發明第六實施例的半導體裝置的剖面圖。取代第五實施例的電極3,第1及第2電極12、13堵住介層洞2,依序層壓在半導體基板1的表面上。第1電極12比第2電極13薄。介層洞2上在第2電極13中設置開口14。開口14中露出第1電極12。藉此,可以得到與第二、五實施例同樣的效果。
Claims (6)
- 一種半導體裝置,包括:半導體基板,設置從背面貫通到表面的介層洞;電極,設置在上述半導體基板的上述表面上,堵住上述介層洞;以及金屬膜,設置在上述半導體基板的上述背面、上述介層洞的側壁及上述電極的下面;其特徵在於:在上述半導體基板的上述背面的上述金屬膜中設置開口,上述開口只連接上述介層洞的外周的一部分,上述開口中露出上述半導體基板的上述介層洞的上述側壁與上述金屬膜的界面。
- 一種半導體裝置,包括:半導體基板,設置從背面貫通到表面的介層洞;電極,設置在上述半導體基板的上述表面上,堵住上述介層洞;以及第1金屬膜及第2金屬膜,依序層壓在上述半導體基板的上述背面、上述介層洞的側壁及上述電極的下面;其特徵在於:上述第1金屬膜比上述第2金屬膜薄;在上述半導體基板的上述背面的上述第2金屬膜中設置開口,上述開口只連接上述介層洞的外周的一部分,上述開口中露出上述介層洞在上述側壁上的上述第1金屬膜與上述第2金屬膜的界面。
- 一種半導體裝置,包括:半導體基板,設置從背面貫通到表面的介層洞;電極,設置在上述半導體基板的上述表面上,堵住上述介層洞;以及金屬膜,設置在上述半導體基板的上述背面、上述介層洞的側壁及上述電極的下面;其特徵在於:在上述介層洞的上述側壁的上述金屬膜中設置開口,上述開口中露出上述半導體基板的上述介層洞的上述側壁。
- 一種半導體裝置,包括:半導體基板,設置從背面貫通到表面的介層洞;電極,設置在上述半導體基板的上述表面上,堵住上述介層洞;以及第1金屬膜及第2金屬膜,依序層壓在上述半導體基板的上述背面、上述介層洞的側壁及上述電極的下面;其特徵在於:上述第1金屬膜比上述第2金屬膜薄;在上述介層洞的上述側壁的上述第2金屬膜中設置開口,上述開口只佔據上述介層洞之橫截面上的邊界的一部分,上述開口中露出上述第1金屬膜。
- 一種半導體裝置,包括:半導體基板,設置從背面貫通到表面的介層洞;電極,設置在上述半導體基板的上述表面上,堵住上述介層洞;以及金屬膜,設置在上述半導體基板的上述背面、上述介層洞的側壁及上述電極的下面;其特徵在於:在上述介層洞上的上述電極中設置開口,上述開口中露出上述金屬膜的上表面。
- 一種半導體裝置,包括:半導體基板,設置從背面貫通到表面的介層洞;第1電極及第2電極,依序層壓在上述半導體基板的上述表面上,堵住上述介層洞;以及金屬膜,設置在上述半導體基板的上述背面、上述介層洞的側壁及上述第1電極的下面;其特徵在於:上述第1電極比上述第2電極薄;在上述介層洞上的上述第2電極中設置開口,上述開口中露出上述第1電極的上表面。
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