TWI527104B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI527104B
TWI527104B TW100108306A TW100108306A TWI527104B TW I527104 B TWI527104 B TW I527104B TW 100108306 A TW100108306 A TW 100108306A TW 100108306 A TW100108306 A TW 100108306A TW I527104 B TWI527104 B TW I527104B
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semiconductor device
separation trench
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insulating film
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理崎智光
中西章滋
島崎洸一
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精工電子有限公司
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Description

半導體裝置及其製造方法
本發明係有關適合用以防止由於切割而導致之膜剝離且於蝕刻期間抑制異常放電的半導體裝置。
將半導體晶圓分割成半導體晶片之切割技術為製造半導體晶片所不可或缺的。然而，在切割之後，由於該半導體晶片之切割或處理的撞擊，有時候會發生膜剝離。圖3A及3B為剖面視圖，說明習知半導體裝置中所固有之膜剝離的問題。圖3A說明在切割之前的剖面視圖，且圖3B說明在切割之後的剖面視圖。在具有沈積於半導體基板001上之層間絕緣膜002的結構中，沿著複數個IC區域004間之劃線區域003的切割造成即自半導體晶片與區域006相接觸之每一個端部表面貫穿過的損壞，而該區域006係藉由切割來予以切開與移除。然後，層疊之層間絕緣膜002與該半導體基板001剝離開，如圖3B所示，結果是膜剝離部份005甚至可出現在IC區域004中。
作為用以防止因切割所造成之膜剝離的方法，提供有沈積在半導體基板上之諸膜的實體分離(譬如見日本專利特許公開申請案第H01-309351號)。圖4A及4B為採用該前述方法而採取對抗膜剝離之措施的半導體裝置之剖面視圖。圖4A說明在切割之前的剖面視圖，且圖4B說明在切割之後的剖面視圖。分離溝槽007被設置在於劃線區域003與IC區域004間之邊界附近的層間絕緣膜002中，以便實體地分開個別區域間之層間絕緣膜002。當如圖4B中所說明地施行切割時，在半導體晶片之與該被切開及移除之區域006相接觸的端部表面的附近之層間絕緣膜002被損壞，而與該半導體基板001剝離開而成為小的片段(piece)008，而無任何損壞傳遞經過沒有該等層間絕緣膜002的部份，其造成該IC區域004中之層間絕緣膜002沒有剝離。
然而，本案申請人已經由研究而發現以下問題會發生：如果該前述之習知技術被應用於具有金屬插塞之半導體裝置。圖5A至5B為剖面視圖，說明當該習知技術及該插塞技術被組合使用時所發生之困難。圖5A說明一剖面視圖，其中，該分離溝槽007被設置在半導體基板001上之層間絕緣膜002中，且插塞金屬膜010之後被沈積在層間絕緣膜002及該半導體基板001的露出部份上。具有小開口之接觸孔009被完全地充填以該插塞金屬膜010，而具有大開口的分離溝槽007則未被充填以該金屬膜，但該插塞金屬膜010係沿著該分離溝槽007的底部部分與側面壁而被沈積。圖5B說明在沈積的插塞金屬膜010被回蝕刻之後的剖面視圖，其說明插塞金屬膜之被形成為該分離溝槽007之側面壁的側壁011。圖5C說明在金屬接線012被形成且連接至該接觸孔009內的插塞金屬膜及鈍化膜013而後被沈積在半導體晶圓之上之後的剖面視圖。圖5D說明當以覆蓋有墊片抗蝕劑014之IC區域004來施行用於墊片開口之蝕刻時的剖面視圖。已發現到當鈍化膜013的一部份係藉由蝕刻來予以移除而該底層暴露出時，在插塞金屬膜之側壁011上產生異常放電015，而導致晶圓表面燃燒(wafer surface burning)之困難。已經認知上述困難需要被進一步處理。
本發明已鑒於該前述問題而被作成。
為了解決該前述問題，本發明採用以下措施。
首先，提供有一半導體裝置，其具有劃線區域及IC區域，包括：形成在半導體基板上之第一絕緣膜，該第一絕緣膜於該劃線區域中包括至少一個分離溝槽；側壁，其係由插塞金屬膜所製成，且被形成為該至少一個分離溝槽之側面壁；及第二絕緣膜，其覆蓋至少該等側壁。
此外，於該半導體裝置中，該第二絕緣膜為鈍化膜。
另外，於該半導體裝置中，在該分離溝槽中由該等插塞金屬膜所製成之相向側壁的底部部分彼此相接觸。
然後，提供有用於半導體裝置之製造方法，包括：在半導體基板上形成第一絕緣膜；在該第一絕緣膜中同時形成接觸孔及分離溝槽；在該第一絕緣膜及該半導體基板的露出部份上沈積插塞金屬膜，藉以完全地充填至少在該接觸孔中之該插塞金屬膜；回蝕刻該插塞金屬膜，以便在該分離溝槽之側面壁上形成側壁；將第二絕緣膜沈積在該等側壁上；圖案化蝕刻用之抗蝕劑膜，以便在該分離溝槽上方覆蓋至少該第二絕緣膜；及對作為底層之該第二絕緣膜施行乾式蝕刻，而以該蝕刻用之抗蝕劑膜使用作為遮罩。
此外，在用於半導體裝置之製造方法中，該第二絕緣膜為鈍化膜。
另外，在用於半導體裝置之製造方法中，該蝕刻用之抗蝕劑膜為光敏性聚醯亞胺。
於半導體晶圓中，採用該等前述之措施將使製造在乾式蝕刻期間由該插塞金屬膜所製成之側壁上沒有異常放電的半導體裝置成為可能，其中，提供該等分離溝槽，用作為對抗在切割之後所造成的層間絕緣膜之剝離的措施。
圖1為說明本發明之第一實施例的半導體裝置之剖面視圖。根據本發明之半導體裝置包括劃線區域003及IC區域004，該兩者在該相同的半導體基板001上具有層間絕緣膜002。在該IC區域004中，接觸孔009係開通於該層間絕緣膜002中，並被完全地充填以插塞金屬膜。在該層間絕緣膜002上，金屬接線012被形成而被連接至該插塞金屬膜。然後，鈍化膜013被設置，以便覆蓋該金屬接線012及該層間絕緣膜002，除了墊片開口部份(未圖示出)以外。
另一方面，在劃線區域003中，分離溝槽007係形成在該半導體基板001上，於該層間絕緣膜002中，且插塞金屬膜之側壁011係形成在該分離溝槽007之側面壁上。該鈍化膜013完全覆蓋該等插塞金屬膜之側壁011。在切割之後，圖1的劃線區域003之左端構成半導體晶片之端部表面，且該端部表面之左邊為藉由切割而被切開及移除之區域(見圖4B之符號006)。此結構防止由於因切割而從該半導體晶片的端部表面朝向該內部IC區域004之損壞造成的膜剝離，且亦防止在用於墊片開口之蝕刻期間的異常放電。
雖然藉由參考圖4B而給予該等小的片段008被散開之說明，但是根據本發明，圖1的左端上之層間絕緣膜002的小片段008係與該插塞金屬膜之側壁001及該鈍化膜013相接觸，其明顯地防止該層間絕緣膜002被散開而成為小的片段。
圖2為概要地說明當用以形成圖1所說明之鈍化膜013的乾式蝕刻被完成時之形狀的視圖。抗蝕劑膜014覆蓋在該分離溝槽007上方的該鈍化膜013，藉以防止該鈍化膜013被蝕刻。
於該前述之實施例中，該分離溝槽被舉例說明為具有該插塞金屬膜之膜厚度的兩倍以上之開口寬度。然而，另一選擇係，如同於圖6所說明的本發明之第二實施例中，該分離溝槽可具有少於該插塞金屬膜之膜厚度的兩倍之開口寬度。於此情況中，該分離溝槽係充分充填以該插塞金屬膜，且在該分離溝槽007之底部部分，形成在該分離溝槽之側面壁的兩者上之該等相向側壁011的每一者之膜厚度為該分離溝槽007之開口寬度的一半或更多。於該結果之半導體裝置中，該等相向側壁007之底部部分係互相接觸，以便更牢靠地固持該等小的片段。
其次，參考圖7A至7D來敘述用於根據本發明之半導體裝置的製造方法。
首先，如圖7A所說明，該接觸孔009係形成於該半導體基板001上之層間絕緣膜002中，且同時在其中設置有該分離溝槽007。然後，插塞金屬膜010係沈積在該層間絕緣膜002與該半導體基板001之露出部份上。在此時，具有小開口之接觸孔009係完全地充填以該插塞金屬膜010，而具有大開口的分離溝槽007則並未充填以該插塞金屬膜010，但該插塞金屬膜010係沿著該分離溝槽007之底部部分與側面壁而被沈積。
其次，如圖7B所說明，沈積之插塞金屬膜010被回蝕刻，以使該插塞金屬膜的側壁011係形成在該分離溝槽007之每一個側面壁上，且其中之該插塞金屬膜被充填至該上部之接觸孔009被形成。
然後，如圖7C所說明，該金屬接線012被形成而被連接至在該接觸孔009內側之插塞金屬膜，且該鈍化膜013之後被沈積在該半導體晶圓上。
此外，用於墊片開口之抗蝕劑014係如圖7D所說明般地被圖案化。換句話說，於該IC區域004中，該抗蝕劑膜014被設置，以便覆蓋該鈍化膜013，除了墊片開口部份(未圖示出)以外，而於該劃線區域003中，用於墊片蝕刻014之抗蝕劑膜被圖案化，以便在該分離溝槽007上方至少覆蓋該鈍化膜013。用於墊片蝕刻014之抗蝕劑膜被使用作為遮罩，以蝕刻該鈍化膜013而作為該底層。在該蝕刻中，墊片係開通於該IC區域004中，且於該劃線區域003中，設置在即將藉由切割而被切開及移除的區域中之鈍化膜013被移除，同時保持該鈍化膜013覆蓋該層間絕緣膜002之小片段008及該分離溝槽007。
藉由採用如上面所述之製造方法，該等插塞金屬膜之側壁011在用於墊片開口之蝕刻期間不會暴露於蝕刻電漿，藉以防止異常之放電。
該等前述之實施例已舉例說明用於圖案化該鈍化膜之抗蝕劑的使用。然而，另一選擇係，於該製造方法中，光敏性聚醯亞胺可代替該抗蝕劑而被使用，且該光敏性聚醯亞胺可被圖案化成預定的形狀，且之後被使用作為遮罩，以蝕刻該在下方之鈍化膜。
此外，該等前述之實施例已舉例說明該金屬接線為單層之情況，但本發明亦係適用於多層接線。
如上所述，本發明不被限制於該等前述之實施例，並可被修改及具體化，而未偏離其要旨。
001．．．基板
002．．．絕緣膜
003．．．劃線區域
004．．．積體電路區域
005．．．膜剝離部份
006．．．區域
007．．．溝槽
008．．．片段
009．．．接觸孔
010．．．插塞金屬膜
011．．．側壁
012．．．金屬接線
013．．．鈍化膜
014．．．墊片抗蝕劑
015．．．放電
於該等附圖中：
圖1係說明本發明之第一實施例的半導體裝置之剖面視圖；
圖2係剖面視圖，說明根據本發明之半導體裝置的製造方法，並說明蝕刻被完成之狀態；
圖3A係剖面視圖，說明習知半導體裝置中所固有之膜剝離的問題，並說明在切割之前的狀態；
圖3B係剖面視圖，說明習知半導體裝置中所固有之膜剝離的問題，並說明在切割之後的狀態；
圖4A係用以解決該膜剝離之問題的半導體裝置之剖面視圖，說明在切割之前的狀態；
圖4B係用以解決該膜剝離之問題的半導體裝置之剖面視圖，說明在切割之後的狀態；
圖5A係剖面視圖，說明當圖4A及4B之習知技術及插塞技術被組合使用時所發生之問題，並說明在沈積插塞金屬膜之後的狀態；
圖5B係剖面視圖，說明當圖4A及4B之習知技術及該插塞技術被組合使用時所發生之該問題，並說明在回蝕刻該插塞金屬膜之後的狀態；
圖5C係剖面視圖，說明當圖4A及4B之習知技術及該插塞技術被組合使用時所發生之該問題，並說明在沈積該鈍化膜之後的狀態；
圖5D係剖面視圖，說明當圖4A及4B之習知技術及該插塞技術被組合使用時所發生之該問題，並說明用以打開墊片的鈍化膜之乾式蝕刻的過程；
圖6係說明本發明之第二實施例的半導體裝置之剖面視圖；
圖7A係剖面視圖，說明用於根據本發明之第一實施例的半導體裝置之製造方法，並說明在沈積插塞金屬膜之後的狀態；
圖7B係剖面視圖，說明用於根據本發明之第一實施例的半導體裝置之製造方法，並說明在回蝕刻該插塞金屬膜之後的狀態；
圖7C係剖面視圖，說明用於根據本發明之第一實施例的半導體裝置之製造方法，並說明在沈積該鈍化膜之後的狀態；及
圖7D剖面視圖，說明用於根據本發明之第一實施例的半導體裝置之製造方法，並說明用以打開墊片的鈍化膜之乾式蝕刻被完成。
001．．．基板
002．．．絕緣膜
003．．．劃線區域
004．．．積體電路區域
007．．．溝槽
008．．．片段
009．．．接觸孔
011．．．側壁
012．．．金屬接線
013．．．鈍化膜

Claims (11)

  1. 一種半導體裝置，具有劃線區域及積體電路(IC)區域，包括：半導體基板；第一絕緣膜，配置在該半導體基板上而橫越該劃線區域及該IC區域；分離溝槽，設置於該劃線區域中之該第一絕緣膜中，該劃線區域具有連續於該IC區域並配置在該分離溝槽之一側的第一端以及配置在該分離溝槽之另一側的第二端，該劃線區域之該第二端形成該半導體裝置之一端面，該端面係配置在該分離溝槽之外並且係藉由切割及移除連續於該半導體裝置之該端面之該劃線區域的一部份所形成；側壁，由插塞金屬膜所製成，且形成在該分離溝槽之側面壁上，使得在該分離溝槽之側面壁上的該插塞金屬膜未延伸出該分離溝槽且不存在於該第一絕緣膜之上表面；及第二絕緣膜，其覆蓋該IC區域及由此朝該劃線區域鄰接地延伸使得該等側壁被該第二絕緣膜覆蓋且被配置在該第二絕緣膜之下。
  2. 如申請專利範圍第1項之半導體裝置，其中，該分離溝槽具有開口寬度不小於兩倍的該插塞金屬膜之厚度。
  3. 如申請專利範圍第1項之半導體裝置，其中，該分離溝槽具有開口寬度小於兩倍的該插塞金屬膜之厚度。
  4. 如申請專利範圍第1項之半導體裝置，其中，該第 二絕緣膜為鈍化膜。
  5. 一種半導體裝置，具有劃線區域及積體電路(IC)區域，包括：半導體基板；第一絕緣膜，配置在該半導體基板上而橫越該劃線區域及該IC區域；分離溝槽，設置於該劃線區域中之該第一絕緣膜中，該劃線區域具有連續於該IC區域並配置在該分離溝槽之一側的第一端以及配置在該分離溝槽之另一側的第二端，該劃線區域之該第二端形成該半導體裝置之一端面，該端面係配置在該分離溝槽之外並且係藉由切割及移除連續於該半導體裝置之該端面之該劃線區域的一部份所形成；側壁，由插塞金屬膜所製成，且形成在該分離溝槽之側面壁上，該側壁的底部部分係彼此接觸；及第二絕緣膜，其覆蓋該IC區域及由此朝該劃線區域鄰接地延伸使得該等側壁被該第二絕緣膜覆蓋且被配置在該第二絕緣膜之下。
  6. 如申請專利範圍第5項之半導體裝置，其中，該分離溝槽具有開口寬度不小於兩倍的該插塞金屬膜之厚度。
  7. 如申請專利範圍第5項之半導體裝置，其中，該分離溝槽具有開口寬度小於兩倍的該插塞金屬膜之厚度。
  8. 如申請專利範圍第5項之半導體裝置，其中，該第二絕緣膜為鈍化膜。
  9. 一種半導體裝置之製造方法，包括： 在半導體基板上形成第一絕緣膜；在該第一絕緣膜中同時形成接觸孔及分離溝槽，該分離溝槽被配置在IC區域及該半導體裝置之一端面之間；在該第一絕緣膜及該半導體基板的露出部份上沈積插塞金屬膜，藉以完全地充填至少在該接觸孔中之該插塞金屬膜；回蝕刻該插塞金屬膜，以便在該分離溝槽之側面壁上形成側壁；將第二絕緣膜沈積在該等側壁上；圖案化蝕刻用之抗蝕劑膜，以便在該分離溝槽上方覆蓋至少該第二絕緣膜；及對作為底層之該第二絕緣膜施行乾式蝕刻，且使用該蝕刻用之抗蝕劑膜作為遮罩。
  10. 如申請專利範圍第9項之半導體裝置之製造方法，其中，該第二絕緣膜包括鈍化膜。
  11. 如申請專利範圍第9或10項之半導體裝置之製造方法，其中，該蝕刻用之抗蝕劑膜包括光敏性聚醯亞胺。
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