JP2011192846A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2011192846A JP2011192846A JP2010058449A JP2010058449A JP2011192846A JP 2011192846 A JP2011192846 A JP 2011192846A JP 2010058449 A JP2010058449 A JP 2010058449A JP 2010058449 A JP2010058449 A JP 2010058449A JP 2011192846 A JP2011192846 A JP 2011192846A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000002184 metal Substances 0.000 claims abstract description 48
- 238000002161 passivation Methods 0.000 claims abstract description 21
- 238000002955 isolation Methods 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims description 19
- 238000000926 separation method Methods 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 6
- 239000004642 Polyimide Substances 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 229920001721 polyimide Polymers 0.000 claims description 4
- 239000011229 interlayer Substances 0.000 abstract description 21
- 230000002159 abnormal effect Effects 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
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- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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Abstract
【解決手段】 半導体装置はスクライブ領域003とIC領域004からなり、スクライブ領域003の層間絶縁膜002には少なくとも一つの分離溝007が設けられ、分離溝007の両側の側壁にはプラグ金属膜からなるサイドウォール011が形成され、少なくともサイドウォールを覆うパッシベーション膜を設ける構成とした半導体装置とする。
【選択図】 図1
Description
本発明は、上記課題に鑑み成されたものである。
まず、半導体基板上に第1の絶縁膜を形成した半導体装置であって、半導体装置はスクライブ領域とIC領域からなり、スクライブ領域の第1の絶縁膜は少なくとも一つの分離溝を有し、分離溝の側壁に形成したプラグ金属膜からなるサイドウォールと、少なくともサイドウォールを覆う第2の絶縁膜とを有することを特徴とする半導体装置とした。
まず、図5(a)に示すように、半導体基板001上の層間絶縁膜002にコンタクトホール009を形成すると同時に分離溝007を設け、層間絶縁膜002および露出した半導体基板001上にプラグ金属膜010を堆積する。このとき、開口の小さいコンタクトホールの中はプラグ金属膜010で完全充填されているが、開口の大きい分離溝007は金属膜で満たされることなく分離溝の底部および側壁に沿ってプラグ金属膜010が堆積される。
002 層間絶縁膜
003 スクライブ領域
004 IC領域
005 膜剥れ部分
006 ダイシングにて切断除去された領域
007 分離溝
008 層間絶縁膜の小片
009 半導体チップ内のコンタクトホール
010 プラグ用金属膜
011 プラグ金属膜のサイドウォール
012 金属配線
013 パッシベーション膜
014 パッドエッチング用レジスト
015 異常放電
Claims (6)
- スクライブ領域とIC領域とからなる半導体装置であって、
半導体基板と、
前記スクライブ領域と前記IC領域とに亘って前記半導体基板上に配置された第1の絶縁膜と、
前記スクライブ領域の前記第1の絶縁膜に設けられた分離溝と、
前記分離溝の側壁に形成されたプラグ金属膜からなるサイドウォールと、
前記サイドウォールを覆う第2の絶縁膜と、
を有する半導体装置。 - 前記第2の絶縁膜は、パッシベーション膜であることを有することを特徴とする請求項1記載の半導体装置。
- 前記プラグ金属膜からなるサイドウォールは、前記分離溝内の対向する前記サイドウォールの底部が互いに接触していることを特徴とする請求項1または請求項2記載の半導体装置。
- 半導体基板上に第1の絶縁膜を形成する工程と、
前記第1の絶縁膜にコンタクトホールを形成すると同時に分離溝を形成する工程と、
前記第1の絶縁膜および露出した半導体基板上にプラグ金属膜を堆積し、少なくとも前記コンタクトホールの中にプラグ金属膜を完全充填する工程と、
前記プラグ金属膜をエッチバックして前記分離溝の側壁にサイドウォールを形成する工程と、
前記サイドウォール上に第2の絶縁膜を堆積する工程と、
少なくとも前記分離溝の上方にある前記第2の絶縁膜を覆うようにエッチング用レジスト膜をパターニングする工程と、
前記エッチング用レジスト膜をマスクとして下地の第2の絶縁膜をドライエッチングする工程と、
からなることを特徴とする半導体装置の製造方法。 - 前記第2の絶縁膜は、パッシベーション膜であることを有することを特徴とする請求項4記載の半導体装置の製造方法。
- 前記パッドエッチング用レジストが感光性ポリイミドであることを特徴とする請求項4または請求項5記載の半導体装置の製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010058449A JP5638818B2 (ja) | 2010-03-15 | 2010-03-15 | 半導体装置およびその製造方法 |
US12/932,560 US9299629B2 (en) | 2010-03-15 | 2011-02-28 | Semiconductor device and manufacturing method therefor |
TW100108306A TWI527104B (zh) | 2010-03-15 | 2011-03-11 | 半導體裝置及其製造方法 |
KR1020110022493A KR101765928B1 (ko) | 2010-03-15 | 2011-03-14 | 반도체 소자 및 그 제조 방법 |
CN201110071731.1A CN102194773B (zh) | 2010-03-15 | 2011-03-15 | 半导体装置及其制造方法 |
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JP2010058449A JP5638818B2 (ja) | 2010-03-15 | 2010-03-15 | 半導体装置およびその製造方法 |
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Publication Number | Publication Date |
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JP2011192846A true JP2011192846A (ja) | 2011-09-29 |
JP2011192846A5 JP2011192846A5 (ja) | 2013-02-28 |
JP5638818B2 JP5638818B2 (ja) | 2014-12-10 |
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Country | Link |
---|---|
US (1) | US9299629B2 (ja) |
JP (1) | JP5638818B2 (ja) |
KR (1) | KR101765928B1 (ja) |
CN (1) | CN102194773B (ja) |
TW (1) | TWI527104B (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017028056A (ja) * | 2015-07-21 | 2017-02-02 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
KR20190012307A (ko) * | 2017-07-26 | 2019-02-11 | 삼성전자주식회사 | 반도체 장치 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7240149B2 (ja) * | 2018-08-29 | 2023-03-15 | キオクシア株式会社 | 半導体装置 |
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JPH05315076A (ja) * | 1992-05-14 | 1993-11-26 | Toshiba Corp | 端面発光型el素子のピクセル形成方法 |
JPH0621218A (ja) * | 1992-07-03 | 1994-01-28 | Seiko Epson Corp | 半導体装置とその製造方法 |
JPH06244239A (ja) * | 1993-02-19 | 1994-09-02 | Nippondenso Co Ltd | 半導体装置 |
JP2006148007A (ja) * | 2004-11-24 | 2006-06-08 | Sharp Corp | 半導体装置の製造方法とその製造方法によって製造された半導体装置 |
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US5136354A (en) * | 1989-04-13 | 1992-08-04 | Seiko Epson Corporation | Semiconductor device wafer with interlayer insulating film covering the scribe lines |
JPH0750700B2 (ja) * | 1989-06-27 | 1995-05-31 | 三菱電機株式会社 | 半導体チップの製造方法 |
JP2894165B2 (ja) * | 1993-07-24 | 1999-05-24 | ヤマハ株式会社 | 半導体装置 |
US7087452B2 (en) * | 2003-04-22 | 2006-08-08 | Intel Corporation | Edge arrangements for integrated circuit chips |
US7566634B2 (en) * | 2004-09-24 | 2009-07-28 | Interuniversitair Microelektronica Centrum (Imec) | Method for chip singulation |
US7615469B2 (en) * | 2007-05-25 | 2009-11-10 | Semiconductor Components Industries, L.L.C. | Edge seal for a semiconductor device and method therefor |
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2010
- 2010-03-15 JP JP2010058449A patent/JP5638818B2/ja active Active
-
2011
- 2011-02-28 US US12/932,560 patent/US9299629B2/en active Active
- 2011-03-11 TW TW100108306A patent/TWI527104B/zh active
- 2011-03-14 KR KR1020110022493A patent/KR101765928B1/ko active IP Right Grant
- 2011-03-15 CN CN201110071731.1A patent/CN102194773B/zh active Active
Patent Citations (4)
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JPH05315076A (ja) * | 1992-05-14 | 1993-11-26 | Toshiba Corp | 端面発光型el素子のピクセル形成方法 |
JPH0621218A (ja) * | 1992-07-03 | 1994-01-28 | Seiko Epson Corp | 半導体装置とその製造方法 |
JPH06244239A (ja) * | 1993-02-19 | 1994-09-02 | Nippondenso Co Ltd | 半導体装置 |
JP2006148007A (ja) * | 2004-11-24 | 2006-06-08 | Sharp Corp | 半導体装置の製造方法とその製造方法によって製造された半導体装置 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017028056A (ja) * | 2015-07-21 | 2017-02-02 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
KR20190012307A (ko) * | 2017-07-26 | 2019-02-11 | 삼성전자주식회사 | 반도체 장치 |
JP2019029654A (ja) * | 2017-07-26 | 2019-02-21 | 三星電子株式会社Samsung Electronics Co.,Ltd. | 半導体装置 |
JP7017992B2 (ja) | 2017-07-26 | 2022-02-09 | 三星電子株式会社 | 半導体装置 |
KR102428328B1 (ko) * | 2017-07-26 | 2022-08-03 | 삼성전자주식회사 | 반도체 장치 |
Also Published As
Publication number | Publication date |
---|---|
JP5638818B2 (ja) | 2014-12-10 |
CN102194773B (zh) | 2015-08-19 |
TWI527104B (zh) | 2016-03-21 |
US9299629B2 (en) | 2016-03-29 |
KR101765928B1 (ko) | 2017-08-07 |
US20110221043A1 (en) | 2011-09-15 |
KR20110103881A (ko) | 2011-09-21 |
TW201203338A (en) | 2012-01-16 |
CN102194773A (zh) | 2011-09-21 |
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