CN102194773B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN102194773B
CN102194773B CN201110071731.1A CN201110071731A CN102194773B CN 102194773 B CN102194773 B CN 102194773B CN 201110071731 A CN201110071731 A CN 201110071731A CN 102194773 B CN102194773 B CN 102194773B
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semiconductor device
dielectric film
separating tank
metal film
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理崎智光
中西章滋
岛崎洸一
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Ablic Inc
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Abstract

本发明提供一种适合防止伴随着切割的膜剥离及防止异常放电的半导体装置。半导体装置的结构为，半导体装置包括划线区域(003)和IC区域(004)，在划线区域(003)的层间绝缘膜(002)设有至少一个分离槽(007)，在分离槽(007)的两侧的侧壁形成由堵塞物金属膜构成的边壁(011)，设有至少覆盖边壁的钝化膜。本发明还提供该半导体装置的制造方法。

Description

半导体装置及其制造方法
技术领域
本发明涉及适合防止伴随着切割的膜剥离及防止蚀刻时的异常放电的半导体装置。
背景技术
在作成半导体芯片时，将半导体晶片分割使其成为半导体芯片的切割技术是必不可少的。但是，由于该切割的冲击、切割后的半导体芯片的处理，有的情况下会引起膜剥离。图3A和图3B是表示以往的半导体装置的膜剥离问题的剖视图。图3A表示切割前，图3B表示切割后的截面形状。在半导体衬底001上沉积有层间绝缘膜002的结构中，若将多个IC区域004之间的划线区域003进行切割，则损伤会从与由切割被切断去除的领城006相接的半导体芯片的端面进入，如图3B所示，层叠的层间绝缘膜002从半导体衬底001剥离，有的情况下在IC区域004也会产生膜剥离部分005。
作为防止这样的切割引起的膜剥离的方法，有将沉积在半导体衬底上的膜物理地分离这样的方法。(例如参照专利文献1)。图4A和图4B是使用该方法对膜剥离进行处理的半导体装置的剖视图。图4A表示切割前，图4B表示切割后的截面形状。在划线区域003与IC区域004的边界附近的层间绝缘膜002设有分离槽007，将各区域间的层间绝缘膜物理地分离。若如图4B所示进行切割，则由于其损伤而与被切断去除的区域006相接的半导体芯片的端面附近的层间绝缘膜会成为小片008，从半导体衬底001剥离飞散，但在没有层间绝缘膜的部分中，损伤不会传播，在IC区域004上的层间绝缘膜002不会产生剥离。
专利文献1：日本特开平1-309351号公报
发明内容
然而，申请人通过调查发现，若对具有金属堵塞物(plug)的半导体装置适用上述现有技术则有以下这样的问题。图5A～图5D是表示在并用现有技术和堵塞物技术的情况下产生的不良情况的剖视图。图5A是在半导体衬底001上的层间绝缘膜002设有分离槽007，将堵塞物金属膜010沉积在层间绝缘膜002及露出的半导体衬底001上之后的剖视图。开口较小的接触孔中被堵塞物金属膜010完全填充，但开口较大的分离槽007没有被金属膜充满，沿着分离槽的底部及侧壁沉积有堵塞物金属膜010。图5B是表示将沉积的堵塞物金属膜010进行深蚀刻后的剖视图，在分离槽007的侧壁形成有堵塞物金属膜的边壁011。图5C是形成与接触孔009内的堵塞物金属膜连接的金属布线012后，在半导体晶片上沉积钝化膜013时的剖视图。在IC区域004覆盖焊盘蚀刻用抗蚀剂014，进行焊盘开口蚀刻时的剖视图如图5D所示。可知若钝化膜由蚀刻去除并露出基底，则在堵塞物金属膜的边壁011上会产生异常放电015，有的情况下会产生晶片表面焦糊这样的不良情况。认识到这是需要进一步处理的问题。
本发明鉴于上述问题而完成。
为解决上述问题的本发明使用以下这样方案。
首先，半导体装置的特征在于，包括划线区域和IC区域，具有形成于半导体衬底上的第一绝缘膜，划线区域的第一绝缘膜至少具有一个分离槽，具有：由形成于分离槽的侧壁的堵塞物金属膜构成的边壁、以及至少覆盖边壁的第二绝缘膜。
而且，半导体装置的特征在于，第二绝缘膜是钝化膜。
另外，半导体装置的特征在于，由堵塞物金属膜构成的边壁的、分离槽内的对置的边壁的底部互相接触。
另外，一种半导体装置的制造方法，其特征在于，包括：在半导体衬底上形成第一绝缘膜的工序；在第一绝缘膜形成接触孔的同时形成分离槽的工序；在第一绝缘膜及露出的半导体衬底上沉积堵塞物金属膜，至少在接触孔中完全填充堵塞物金属膜的工序；对堵塞物金属膜进行深蚀刻，在分离槽的侧壁形成边壁的工序；在边壁上沉积第二绝缘膜的工序；对蚀刻用抗蚀剂膜进行构图，以至少覆盖位于分离槽的上方的第二绝缘膜的工序；以及将蚀刻用抗蚀剂膜作为掩模，对基底的第二绝缘膜进行干蚀刻的工序。
另外，半导体装置的制造方法的特征在于，第二绝缘膜是钝化膜。
而且，半导体装置的制造方法的特征在于，焊盘蚀刻用抗蚀剂是感光性聚酰亚胺。
发明的效果
通过使用上述方案，能够制造在设有对应切割后的层间绝缘膜剥用的分离槽的半导体晶片中，干蚀刻时在堵塞物金属膜的边壁不会引起异常放电的半导体装置。
附图说明
图1是表示本发明的第一实施方式的半导体装置的剖视图。
图2是表示本发明的半导体装置的制造方法的剖视图，表示蚀刻结束时。
图3A是表示以往的半导体装置的膜剥离问题的剖视图，是切割前的图。
图3B是表示以往的半导体装置的膜剥离问题的剖视图，是切割后的图。
图4A是用于解决膜剥离问题的半导体装置的剖视图，是切割前的图。
图4B是用于解决膜剥离问题的半导体装置的剖视图，是切割后的图。
图5A是表示在并用图4的现有技术和堵塞物技术的情况下产生的问题的剖视图，是堵塞物金属膜沉积后的图。
图5B是表示在并用图4的现有技术和堵塞物技术的情况下产生的问题的剖视图，是堵塞物金属膜深蚀刻后的图。
图5C是表示在并用图4的现有技术和堵塞物技术的情况下产生的问题的剖视图，是钝化膜沉积后的图。
图5D是表示在并用图4的现有技术和堵塞物技术的情况下产生的问题的剖视图，是表示用于对焊盘进行开口的钝化膜的干蚀刻的中途的图。
图6是表示本发明的第二实施方式的半导体装置的剖视图。
图7A是表示本发明的第一实施例所涉及的半导体装置的制造方法的剖视图，是堵塞物金属膜沉积后的图。
图7B是表示本发明的第一实施例所涉及的半导体装置的制造方法的剖视图，是堵塞物金属膜深蚀刻后的图。
图7C是表示本发明的第一实施例所涉及的半导体装置的制造方法的剖视图，是钝化膜沉积后的图。
图7D是表示本发明的第一实施例所涉及的半导体装置的制造方法的剖视图，是表示用于对焊盘进行开口的钝化膜的干蚀刻结束时的图。
附图标记说明
001半导体衬底；002层间绝缘膜；003划线区域；004IC区域；005膜剥离部分；006被切割而切断去除的区域；007分离槽；008层间绝缘膜的小片；009半导体芯片内的接触孔；010堵塞物用金属膜；011堵塞物金属膜的边壁；012金属布线；013钝化膜；014焊盘蚀刻用抗蚀剂；015异常放电。
具体实施方式
图1是表示本发明的第一实施方式的半导体装置的剖视图。本发明的半导体装置包括划线区域003和IC区域004，两个区域在同一半导体衬底001上具有层间绝缘膜002，在IC区域004，在层间绝缘膜002开口有接触孔009，在其中完全填充堵塞物金属膜，在层间绝缘膜002上与堵塞物金属膜连接形成有金属布线012。然后，设有钝化膜013，以覆盖除了焊盘开口部(未图示)的金属布线012及层间绝缘膜002。
另一方面，在划线区域003，在半导体衬底001上的层间绝缘膜002形成分离槽007，在分离槽007的侧壁形成有堵塞物金属膜的边壁011。覆盖有钝化膜013，使其完全覆盖堵塞物金属膜的边壁011。在切割后，图中的划线区域003的左端是半导体芯片的端面，其左侧成为被切割而切断去除的区域(参照图4B的标记006)。通过采用这样的结构，可以防止由于切割时的损伤从半导体芯片的端面向内部的IC区域产生膜剥离，并且可以防止在焊盘开口用的蚀刻中异常放电。
另外，在图4B说明了小片008会飞散，但根据本发明，由于图1内的左端的层间绝缘膜的小片008与堵塞物金属膜的边壁011或钝化膜013接触，因此显著抑制成为小片而飞散。
图2是示意用于形成图1所示的钝化膜013的干蚀刻结束时的形状的图。抗蚀剂膜14覆盖位于分离槽007的上方的钝化膜013，使其不被蚀刻。
在上述实施例中，图示了使分离槽的开口宽度相对于堵塞物金属膜的膜厚为2倍以上的大小，但如图6所示的第二实施方式所示，通过使分离槽的开口宽度不到堵塞物金属膜的膜厚的2倍，在分离槽内充分填充堵塞物金属膜，形成于分离槽内的两侧的侧壁，对置的边壁的分离槽底部的膜厚为分离槽开口宽度的一半(1/2)以上。其结果是，对置的边壁的底部接触，成为可以对小片进一步牢固保持的半导体装置。
接下来，使用图7A～图7D，说明本发明的半导体装置的制造方法。
首先，如图7A所示，在半导体衬底001上的层间绝缘膜002形成接触孔009，同时设有分离槽007，在层间绝缘膜002及露出的半导体衬底001上沉积堵塞物金属膜010。此时，开口较小的接触孔中被堵塞物金属膜010完全填充，但开口较大的分离槽007没有被金属膜充满，沿着分离槽的底部及侧壁沉积有堵塞物金属膜010。
接下来，如图7B所示，若对沉积的堵塞物金属膜010进行深蚀刻，则在分离槽007的两侧的侧壁形成堵塞物金属膜的边壁011，而且形成直到上部都被堵塞物金属膜填充的接触孔。
而且，如图7C所示，在形成与接触孔009内的堵塞物金属膜连接的金属布线012后，在半导体晶片上沉积钝化膜。
并且，如图7D所示，对焊盘开口用的抗蚀剂014进行构图。即，设有抗蚀剂膜014，以在IC区域覆盖除了焊盘开口部(未图示)的钝化膜013，在划线区域003，对焊盘蚀刻用抗蚀剂膜014进行构图，以至少覆盖位于分离槽007的上方的钝化膜013。若将焊盘蚀刻用抗蚀剂膜014作为掩模，对基底的钝化膜013进行蚀刻，则在IC区域中焊盘会开口，在划线区域003中残留覆盖层间绝缘膜的小片008和分离槽007的钝化膜，进行蚀刻以去除由切割而被切断去除的区域的钝化膜013。
通过使用以上这样的制造方法，在焊盘开口蚀刻中堵塞物金属膜的边壁011不会暴露在蚀刻等离子体内，可以防止异常放电。
在上述实施例中，示出了使用抗蚀剂作为钝化膜的构图的例子，但也可以采用用感光性聚酰亚胺代替抗蚀剂，将感光性聚酰亚胺构图为既定的形状后，将其作为掩模，对基底的钝化膜进行蚀刻这样的制造方法。
另外，在上述例中，说明了金属布线为1层的情况，但也可以适用于多层布线。
如上所述，本发明不限于上述实施方式，可以在不脱离其要点的范围内变形实施。

Claims (6)

1.一种半导体装置的制造方法，其特征在于，包括：
在半导体衬底上形成第一绝缘膜的工序；
在所述第一绝缘膜形成接触孔的同时形成分离槽的工序；
在划线区域内形成以所述分离槽为一端而以切割端面为另一端的、连续设置的所述第一绝缘膜的小片的工序；
在所述第一绝缘膜及露出的半导体衬底上沉积堵塞物金属膜，至少在所述接触孔中沉积堵塞物金属膜的工序；
对所述堵塞物金属膜进行深蚀刻，在所述分离槽的侧壁形成边壁的工序；
以覆盖所述边壁上及所述第一绝缘膜的小片的至少所述一端方式沉积第二绝缘膜的工序；
对蚀刻用抗蚀剂膜进行构图，以至少覆盖位于所述分离槽的上方的所述第二绝缘膜的工序；以及
将所述蚀刻用抗蚀剂膜作为掩模，对基底的第二绝缘膜进行干蚀刻的工序。
2.根据权利要求1所述的半导体装置的制造方法，其特征在于，
所述第二绝缘膜是钝化膜。
3.根据权利要求1或2所述的半导体装置的制造方法，其特征在于，
所述蚀刻用抗蚀剂膜是感光性聚酰亚胺。
4.一种半导体装置，通过权利要求１所述的半导体装置的制造方法制造，包括划线区域和IC区域，该半导体装置具有：
半导体衬底；
遍及所述划线区域和所述IC区域而配置在所述半导体衬底上的第一绝缘膜；
设在所述划线区域的所述第一绝缘膜的分离槽；
在所述划线区域内，以所述分离槽为一端而以切割端面为另一端的、连续设置的所述第一绝缘膜的小片；
由形成于所述分离槽的侧壁的堵塞物金属膜构成的边壁；以及
覆盖所述边壁及所述第一绝缘膜的小片的至少所述一端的第二绝缘膜。
5.根据权利要求4所述的半导体装置，其特征在于，
所述第二绝缘膜是钝化膜。
6.根据权利要求4或5所述的半导体装置，其特征在于，
由所述堵塞物金属膜构成的边壁的、所述分离槽内的对置的所述边壁的底部互相接触。
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