TW201733004A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

Info

Publication number
TW201733004A
TW201733004A TW105136224A TW105136224A TW201733004A TW 201733004 A TW201733004 A TW 201733004A TW 105136224 A TW105136224 A TW 105136224A TW 105136224 A TW105136224 A TW 105136224A TW 201733004 A TW201733004 A TW 201733004A
Authority
TW
Taiwan
Prior art keywords
via hole
metal film
semiconductor substrate
opening
electrode
Prior art date
Application number
TW105136224A
Other languages
English (en)
Other versions
TWI624908B (zh
Inventor
堀浩一郎
西澤弘一郎
Original Assignee
三菱電機股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機股份有限公司 filed Critical 三菱電機股份有限公司
Publication of TW201733004A publication Critical patent/TW201733004A/zh
Application granted granted Critical
Publication of TWI624908B publication Critical patent/TWI624908B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816Aspects relating to the layout of the pattern or to the size of vias or trenches
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051Deposition of metallic or metal-silicide layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

介層洞形成後即使加熱也可以得到確保基板表面側與背面側導通的半導體裝置。半導體基板1中,設置從背面貫通到表面的介層洞2。在半導體基板1的表面上設置電極3,堵住介層洞2。金屬膜4設置在半導體基板1的背面、介層洞2的側壁2a及電極3的下面。半導體基板1的背面在金屬膜4中設置開口5。開口5只連接介層洞2的外周的一部分。開口5中露出介層洞2的側壁2a與金屬膜4的界面A。

Description

半導體裝置
本發明係關於設置貫通半導體基板的介層洞的半導體裝置。
取得形成半導體元件的基板表面與其相反側的背面之間的導通的情況下,在半導體基板中設置介層洞,表面側的電極與背面側的金屬膜間經由介層洞互相連接。
製造如此的半導體裝置的情況下,首先,半導體基板的表面上形成電極。其次,研削半導體基板的背面側直到既定的厚度。其次,形成背面的介層洞之處以外,以光阻等遮光,蝕刻半導體基板直到從背面側露出電極。除去.洗淨光罩後,背面、介層洞的側壁及電極的下面形成金屬膜。因為介層洞內露出電極的背面,表面側的電極與背面側的金屬膜接觸。
[先行技術文件] [專利文件]
[專利文件1]專利公開平成10年第303198號公報
由於半導體裝置的高積體化,介層洞也縮小平面 方向的尺寸。所以,形成介層洞之際為了不往水平方向擴大,有必要再提高乾蝕刻的異向性。於是,不往橫方向蝕刻,蝕刻時更強化在介層洞側壁上形成的膜。因此,即使蝕刻後的除去.洗淨,也有除不盡的殘渣殘留在介層洞側壁上。介層洞形成後加熱半導體裝置之際,由於從背面側的金屬膜覆蓋的殘渣產生氣體,半導體基板與金屬膜之間的界面受到壓力。此壓力傳過界面散佈密合強度弱的電極與金屬膜的界面。結果,兩者的連接脫落,有無法取得導通的問題。
本發明係用以解決上述的問題而形成,其目的是介層洞形成後即使加熱也可以得到確保基板表面側與背面側導通的半導體裝置。
根據本發明的半導體裝置,包括:半導體基板,設置從背面貫通到表面的介層洞;電極,設置在上述半導體基板的上述表面上,堵住上述介層洞;以及金屬膜,設置在上述半導體基板的上述背面、上述介層洞的側壁及上述電極的下面;其特徵在於:上述半導體基板的上述背面在上述金屬膜中設置開口,上述開口只連接上述介層洞的外周的一部分,上述開口中露出上述介層洞的上述側壁與上述金屬膜的界面。
本發明中,從殘渣產生的氣體傳過半導體基板與金屬膜之間的界面,到達設置在金屬膜中的開口。開口連接介層洞的外周,開口中露出介層洞的側壁與金屬膜的界面。因此,傳過界面的氣體排出到半導體裝置之外。結果,因為可以 防止電極與金屬膜的連接脫落,介層洞形成後即使加熱也可以得到確保基板表面側與背面側導通。
1‧‧‧半導體基板
2‧‧‧介層洞
2a‧‧‧側壁
3‧‧‧電極
4‧‧‧金屬膜
5‧‧‧開口
6‧‧‧第1金屬膜
7‧‧‧第2金屬膜
8‧‧‧開口
9‧‧‧開口
10‧‧‧開口
11‧‧‧開口
12‧‧‧第1電極
13‧‧‧第2電極
14‧‧‧開口
A‧‧‧界面
B‧‧‧界面
[第1圖]係顯示根據本發明第一實施例的半導體裝置的剖面圖;[第2圖]係顯示根據本發明第一實施例的半導體裝置的下面圖;[第3圖]係顯示根據比較例的半導體裝置的剖面圖;[第4圖]係顯示根據比較例的半導體裝置的剖面圖;[第5圖]係顯示根據本發明第二實施例的半導體裝置的剖面圖;[第6圖]係顯示根據本發明第二實施例的半導體裝置的下面圖;[第7圖]係顯示根據本發明第三實施例的半導體裝置的剖面圖;[第8圖]係顯示根據本發明第三實施例的半導體裝置的剖面圖;[第9圖]係顯示根據本發明第四實施例的半導體裝置的剖面圖;[第10圖]係顯示根據本發明第五實施例的半導體裝置的平面圖;[第11圖]係沿著第10圖的I~II的剖面圖;以及[第12圖]係顯示根據本發明第六實施例的半導體裝置的 剖面圖。
關於根據本發明的實施例的半導體裝置,參照圖面說明。相同或對應的構成要素附上相同的符號,可能省略重複的說明。
[第一實施例]
第1圖係顯示根據本發明第一實施例的半導體裝置的剖面圖。第2圖係顯示根據本發明第一實施例的半導體裝置的下面圖。
半導體基板1的表面上形成電晶體等的半導體元件(未圖示)。設置從半導體基板1的背面貫通到表面的介層洞2。在此,以介層洞2內露出的半導體基板1的內壁為介層洞2的側壁2a。又,對半導體基板1的背面從垂直方向所見的平視圖中介層洞2的平面形狀是圓形,但橢形等的形狀也可以。
在半導體基板1的表面上設置電極3,堵住介層洞2。金屬膜4設置在半導體基板1的背面、介層洞2的側壁2a及電極3的下面。金屬膜4與電極3的下面直接接觸,半導體基板1的表面側與背面側導通。介層洞2的側壁2a與金屬膜4直接接觸構成界面A。對半導體基板1的背面從垂直方向所見的平視圖中,介層洞2的外周全周設置介層洞2的側壁2a與金屬膜4的界面A。
半導體基板1的背面在金屬膜4中設置開口5。對半導體基板1的背面從垂直方向所見的平視圖中,開口5只連接介層洞2的外周的一部分。開口5中露出介層洞2的側壁2a 與金屬膜4的界面A。又,開口5連接介層洞2的外周全部的話,半導體基板1的背面的金屬膜4與介層洞2的側壁2a的金屬膜4分離,半導體基板1的表面側與背面側變得不導通。
接著,說明本實施例的半導體裝置的製造方法。首先,半導體基板1的表面上形成電極3。其次,研削半導體基板1的背面側至既定的厚度。其次,形成背面的介層洞2之處以光阻等遮光,蝕刻半導體基板1直到電極3從背面側露出。除去.洗淨光罩後,半導體基板1的背面側全面,即基板背面、介層洞2的側壁2a及電極3的下面形成金屬膜4。其次,除去切割線的金屬膜4之際,除了形成開口5之處與切割線以光阻覆蓋背面。此狀態下,以蝕刻金屬膜4不蝕刻半導體基板1的液體處理,形成開口5。
接著,將本實施例的效果與比較例比較說明。第3、4圖,係顯示根據比較例的半導體裝置的剖面圖。比較例,不在金屬膜4中設置開口5。介層洞2形成後,加熱半導體裝置之際,由於從背面側的金屬膜4覆蓋的殘渣產生的氣體,半導體基板1與金屬膜4之間的界面A受到壓力。此壓力傳過界面A散佈密合強度弱的電極3與背面側的金屬膜4的界面A。結果,兩者的連接脫落,有無法取得導通的問題。
相對於此,本發明的實施例,從殘渣產生的氣體傳過半導體基板1與金屬膜4之間的界面A,到達金屬膜4中設置的開口5。開口5連接介層洞2的外周,開口5中露出介層洞2的側壁2a與金屬膜4之間的界面A。因此,傳過界面A的氣體排出半導體裝置外。結果,因為可以防止電極3與金屬 膜4的連接脫落,介層洞2形成後,即使加熱也可以確保基板表面側與背面側的導通。
[第二實施例]
第5圖係顯示根據本發明第二實施例的半導體裝置的剖面圖,第6圖係顯示根據本發明第二實施例的半導體裝置的下面圖。本實施例中,取代第一實施例的金屬膜4,第1及第2金屬膜6、7依序層壓在半導體基板1的背面、介層洞2的側壁2a及電極3的下面。第1金屬膜6比第2金屬膜7薄。背面側的金屬膜中,第2金屬膜7係負擔導電性的主要層,佔背面側的金屬膜厚度的過半。第2金屬膜7作為電鍍形成時的供電層,以無電解電鍍形成第1金屬膜6。不限定於此,作為用以確保附著力的阻障層,形成第1金屬膜6也可以。形成方法也可以應用濺鍍法等其他的方法。
半導體基板1的背面在第2金屬膜7中設置開口8。開口8只連接介層洞2的外周的一部分。本實施例的開口8,也與第一實施例相同,除了形成開口8之處與切割線以光阻覆蓋背面的狀態下,蝕刻金屬膜4形成。
開口8中露出介層洞2在側壁2a上的第1金屬膜6與第2金屬膜7的界面B。又,與此界面B大致相同的位置上也配置介層洞2的側壁2a與第1金屬膜6的界面A,存在於開口8內留下的第1金屬膜6的下側。
本實施例中,從殘渣產生的氣體傳過半導體基板1與第1金屬膜6之間的界面A,到達第2金屬膜7中設置的開口8。開口8內以第1金屬膜6覆蓋,但因為第1金屬膜6薄, 氣體透過第1金屬膜6排出半導體裝置之外。結果,介層洞2形成後即使加熱也可以確保基板表面側與背面側的導通。
又,由於留下薄的第1金屬膜6,因為不必2次蝕刻主要的第2金屬膜7與薄的第1金屬膜6,可以簡化步驟。又,以無電解電鍍形成金屬膜時,以無電解電鍍形成後,因為必須加熱處理,容易受氣體的影響。所以,如本實施例,在第2金屬膜7中設置開口8的效果很大。
[第三實施例]
第7及8圖係顯示根據本發明第三實施例的半導體裝置的剖面圖。第8圖係從不同於第7圖的另外的方向所見的剖面。取代第一實施例的開口5,介層洞2的側壁2a在金屬膜4中設置開口9。開口9中露出介層洞2的側壁2a。
本實施例中,介層洞2的側壁2a形成錐狀,使可以照相製版。在半導體基板1的背面側全面形成金屬膜4後,除了形成開口9之處以光阻覆蓋背面。在此狀態下,以蝕刻金屬膜4不蝕刻半導體基板1的液體處理,形成開口9。
藉此,與第一實施例相同,從殘渣產生的氣體傳過界面A,從開口9排出半導體裝置之外。結果,介層洞2形成後,即使加熱也可以確保基板表面側與背面側的導通。又,雖然開口9的形成方法變複雜,但藉由介層洞2內設置開口9,比起第一實施例氣體更容易排出。
[第四實施例]
第9圖係顯示根據本發明第四實施例的半導體裝置的剖面圖。本實施例中,取代第三實施例的金屬膜4,第1及第2金 屬膜6、7依序層壓在半導體基板1的背面、介層洞2的側壁2a及電極3的下面。第1金屬膜6比第2金屬膜7薄。介層洞2的側壁2a在第2金屬膜7中設置開口10。開口10中露出第1金屬膜6。藉此,可以得到與第二、三實施例相同的效果。
[第五實施例]
第10圖係顯示根據本發明第五實施例的半導體裝置的平面圖。第11圖係沿著第10圖的I~II的剖面圖。取代第一實施例的開口5,介層洞2上在電極3中設置開口11。開口11中露出金屬膜4。
本實施例中,形成介層洞2及金屬膜4後,除了形成開口11之處,以光阻覆蓋基板表面,背面側的金屬膜4作為阻絕層,蝕刻表面側的電極3形成開口11。
因此,與第一實施例相同,從殘渣產生的氣體傳過界面A,從開口11排出半導體裝置之外。結果,介層洞2形成後即使加熱也可以確保基板表面側與背面側的導通。又,雖然開口11的形成方法變複雜,但藉由介層洞2上設置開口11,比起第一實施例氣體更容易排出。
[第六實施例]
第12圖係顯示根據本發明第六實施例的半導體裝置的剖面圖。取代第五實施例的電極3,第1及第2電極12、13堵住介層洞2,依序層壓在半導體基板1的表面上。第1電極12比第2電極13薄。介層洞2上在第2電極13中設置開口14。開口14中露出第1電極12。藉此,可以得到與第二、五實施例同樣的效果。
1‧‧‧半導體基板
2‧‧‧介層洞
2a‧‧‧側壁
3‧‧‧電極
4‧‧‧金屬膜
5‧‧‧開口
A‧‧‧界面

Claims (6)

  1. 一種半導體裝置,包括:半導體基板,設置從背面貫通到表面的介層洞;電極,設置在上述半導體基板的上述表面上,堵住上述介層洞;以及金屬膜,設置在上述半導體基板的上述背面、上述介層洞的側壁及上述電極的下面;其特徵在於:上述半導體基板的上述背面在上述金屬膜中設置開口,上述開口只連接上述介層洞的外周的一部分,上述開口中露出上述介層洞的上述側壁與上述金屬膜的界面。
  2. 一種半導體裝置,包括:半導體基板,設置從背面貫通到表面的介層洞;電極,設置在上述半導體基板的上述表面上,堵住上述介層洞;以及第1及第2金屬膜,依序層壓在上述半導體基板的上述背面、上述介層洞的側壁及上述電極的下面;其特徵在於:上述第1金屬膜比上述第2金屬膜薄;上述半導體基板的上述背面在上述第2金屬膜中設置開口,上述開口只連接上述介層洞的外周的一部分,上述開口中露出上述介層洞在上述側壁上的上述第1金屬膜與上述第2金屬膜的界面。
  3. 一種半導體裝置,包括:半導體基板,設置從背面貫通到表面的介層洞;電極,設置在上述半導體基板的上述表面上,堵住上述介層洞;以及金屬膜,設置在上述半導體基板的上述背面、上述介層洞的側壁及上述電極的下面;其特徵在於:上述介層洞的上述側壁在上述金屬膜中設置開口,上述開口中露出上述介層洞的上述側壁。
  4. 一種半導體裝置,包括:半導體基板,設置從背面貫通到表面的介層洞;電極,設置在上述半導體基板的上述表面上,堵住上述介層洞;以及第1及第2金屬膜,依序層壓在上述半導體基板的上述背面、上述介層洞的側壁及上述電極的下面;其特徵在於:上述第1金屬膜比上述第2金屬膜薄;上述介層洞的上述壁側在上述第2金屬膜中設置開口,上述開口中露出上述第1金屬膜。
  5. 一種半導體裝置,包括:半導體基板,設置從背面貫通到表面的介層洞;電極,設置在上述半導體基板的上述表面上,堵住上述介層洞;以及金屬膜,設置在上述半導體基板的上述背面、上述介層洞 的側壁及上述電極的下面;其特徵在於:上述介層洞上在上述電極中設置開口,上述開口中露出上述金屬膜。
  6. 一種半導體裝置,包括:半導體基板,設置從背面貫通到表面的介層洞;第1及第2電極,依序層壓在上述半導體基板的上述表面上,堵住上述介層洞;以及金屬膜,設置在上述半導體基板的上述背面、上述介層洞的側壁及上述第1電極的下面;其特徵在於:上述第1電極比上述第2電極薄;上述介層洞上在上述第2電極中設置開口,上述開口中露出上述第1電極。
TW105136224A 2016-02-08 2016-11-08 半導體裝置 TWI624908B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016021641A JP6648544B2 (ja) 2016-02-08 2016-02-08 半導体装置
JP2016-021641 2016-02-08

Publications (2)

Publication Number Publication Date
TW201733004A true TW201733004A (zh) 2017-09-16
TWI624908B TWI624908B (zh) 2018-05-21

Family

ID=59382095

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105136224A TWI624908B (zh) 2016-02-08 2016-11-08 半導體裝置

Country Status (6)

Country Link
US (1) US10020246B2 (zh)
JP (1) JP6648544B2 (zh)
KR (1) KR101898373B1 (zh)
CN (1) CN107045978B (zh)
DE (1) DE102017200415B4 (zh)
TW (1) TWI624908B (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107527823A (zh) * 2017-08-24 2017-12-29 通富微电子股份有限公司 一种封装基板的制备方法及封装基板
CN107611043A (zh) * 2017-08-24 2018-01-19 通富微电子股份有限公司 一种扇出型封装方法
CN107611112A (zh) * 2017-08-24 2018-01-19 通富微电子股份有限公司 一种扇出型封装器件
CN107564880A (zh) * 2017-08-24 2018-01-09 通富微电子股份有限公司 一种扇出型封装器件
CN107481940A (zh) * 2017-08-24 2017-12-15 通富微电子股份有限公司 一种封装基板的制备方法及封装基板
CN107611042B (zh) * 2017-08-24 2021-09-21 通富微电子股份有限公司 一种扇出型封装方法
CN107516638A (zh) * 2017-08-24 2017-12-26 通富微电子股份有限公司 一种扇出型封装方法
CN107564879A (zh) * 2017-08-24 2018-01-09 通富微电子股份有限公司 一种扇出型封装器件

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61263284A (ja) * 1985-05-17 1986-11-21 Nec Corp 半導体装置
JP3443219B2 (ja) * 1995-11-14 2003-09-02 株式会社日立製作所 半導体集積回路装置およびその製造方法
JP3724110B2 (ja) 1997-04-24 2005-12-07 三菱電機株式会社 半導体装置の製造方法
DE112005000522T5 (de) * 2004-03-03 2007-01-18 Shinko Electric Industries Co., Ltd. Platinen-Herstellungsverfahren und Platine
CN1926930B (zh) * 2004-03-03 2011-06-15 新光电气工业株式会社 电路板制造方法与电路板
JP4884104B2 (ja) * 2006-06-29 2012-02-29 富士通セミコンダクター株式会社 キャパシタを含む半導体装置及びその製造方法
JP5119623B2 (ja) * 2006-08-03 2013-01-16 大日本印刷株式会社 インターポーザ基板の製造方法
JP4937842B2 (ja) * 2007-06-06 2012-05-23 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2009220493A (ja) * 2008-03-18 2009-10-01 Nec Electronics Corp 金属ペースト印刷方法およびメタルマスク
JP5471268B2 (ja) * 2008-12-26 2014-04-16 大日本印刷株式会社 貫通電極基板及びその製造方法
JP2010258213A (ja) 2009-04-24 2010-11-11 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法
JP5532394B2 (ja) * 2009-10-15 2014-06-25 セイコーエプソン株式会社 半導体装置及び回路基板並びに電子機器
JP5663886B2 (ja) 2010-02-08 2015-02-04 三菱電機株式会社 半導体装置の製造方法
US8415805B2 (en) 2010-12-17 2013-04-09 Skyworks Solutions, Inc. Etched wafers and methods of forming the same
JP5357241B2 (ja) * 2011-08-10 2013-12-04 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
JP2016021641A (ja) 2014-07-14 2016-02-04 富士ゼロックス株式会社 情報処理装置およびプログラム

Also Published As

Publication number Publication date
CN107045978A (zh) 2017-08-15
JP2017143093A (ja) 2017-08-17
KR20170094073A (ko) 2017-08-17
CN107045978B (zh) 2020-08-21
US10020246B2 (en) 2018-07-10
DE102017200415A1 (de) 2017-08-10
JP6648544B2 (ja) 2020-02-14
KR101898373B1 (ko) 2018-09-12
US20170229380A1 (en) 2017-08-10
TWI624908B (zh) 2018-05-21
DE102017200415B4 (de) 2022-04-21

Similar Documents

Publication Publication Date Title
TW201733004A (zh) 半導體裝置
US10504839B2 (en) Semiconductor device and manufacturing method of the same
TWI684242B (zh) 半導體裝置之製造方法及半導體裝置
US20160351473A1 (en) Semiconductor device and method for producing semiconductor device
US8772944B2 (en) Semiconductor device and method for manufacturing semiconductor device
TWI582918B (zh) 晶片封裝體及其製造方法
CN104576657B (zh) 一种阵列基板及其制造方法
JP2018088487A (ja) 半導体装置及びその製造方法
JP2018032757A (ja) 半導体装置及びその製造方法
TWI578420B (zh) 半導體結構及其製作方法
US10529587B2 (en) Semiconductor device and method of manufacturing semiconductor device
JP6843570B2 (ja) 半導体装置の製造方法
TWI754891B (zh) 半導體裝置
US20150194396A1 (en) Bond pad having a trench and method for forming
US9185807B2 (en) Integrated circuit structures having off-axis in-hole capacitor
TWI514488B (zh) 矽穿孔底部形成凸塊之製程與結構
JP2014229667A (ja) 半導体装置および半導体装置の製造方法
TW201316466A (zh) 半導體裝置及其製造方法
WO2016145758A1 (zh) 显示基板及其制备方法
JP2018142674A (ja) 電子部品の製造方法
JP2016111060A (ja) 半導体装置および半導体装置の製造方法
US20190027358A1 (en) Method for manufacturing semiconductor device
JP2007300139A (ja) 半導体装置
JP2010080772A (ja) 半導体装置