CN101114592B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN101114592B
CN101114592B CN2007101383129A CN200710138312A CN101114592B CN 101114592 B CN101114592 B CN 101114592B CN 2007101383129 A CN2007101383129 A CN 2007101383129A CN 200710138312 A CN200710138312 A CN 200710138312A CN 101114592 B CN101114592 B CN 101114592B
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China
Prior art keywords
semiconductor substrate
planarization
layer
semiconductor
peristome
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CN2007101383129A
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CN101114592A (zh
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关克行
铃木彰
龟山工次郎
及川贵弘
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On Semiconductor Niigata Co Ltd
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Sanyo Electric Co Ltd
Sanyo Semiconductor Co Ltd
Sanyo Semiconductor Manufacturing Co Ltd
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Abstract

本发明提供一种生产效率高且可靠性和合格品率高的半导体装置及其制造方法。进行半导体衬底(1)的背面磨削(背研磨)，把半导体装置减薄。然后在该阶段不进行把由背面磨削产生的损伤层(7)除去而有选择地在半导体衬底的背面形成抗蚀剂层(8)。然后，以抗蚀剂层(8)作为掩模蚀刻半导体衬底(1)，形成通路孔(9)。然后保持将半导体衬底(1)配置在该蚀刻工序所利用的蚀刻装置内的状态，把形成通路孔(9)和除去抗蚀剂层(8)连续进行。这样，把蚀刻工序和其后的灰化工序以一个处理装置连续进行。然后，把半导体衬底(1)背面的损伤层(7)除去和把通路孔(9)内壁面平坦化的工序也以与上述灰化工序同一装置连续进行。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置的制造方法，特别是涉及蚀刻工序和把在该蚀刻工序中使用的掩模层除去的工序。
背景技术
目前，在制造半导体装置时，具有把抗蚀剂层作为掩模而把基底的绝缘膜或金属层、或半导体衬底等加工成规定图形的蚀刻(etching)工序，和把在该蚀刻工序中使用的抗蚀剂层除去的灰化(ashing)工序。
说明现有半导体装置制造方法的一例。如图13(a)所示，使用背面磨削装置(磨床)对半导体衬底100的背面进行背面磨削(背研磨)，把半导体衬底100处理成规定的厚度(例如100μm～150μm)。
然后如图13(b)所示，使用规定的蚀刻装置(湿蚀刻装置或干蚀刻装置)对半导体衬底100的背面进行蚀刻，把由背面磨削产生的背面凸凹等机械损伤层(约30μm左右)除去。由此，半导体衬底100的背面更加平坦。
然后如图13(c)所示，通过光刻法在半导体衬底100的背面上有选择地形成抗蚀剂层101。并把该抗蚀剂层101作为掩模来干蚀刻半导体衬底100。该蚀刻工序如图14(a)所示是在干蚀刻装置110的真空室111内进行。
图14(a)中，半导体衬底100通过保持部件112而被机械固定在载物台113上。图14(b)是从上方看载物台113的俯视图。保持部件112被配置在半导体衬底100外周数毫米的部分处。被保持部件112覆盖的部分由于不能进行合适的蚀刻加工，所以不能成为产品芯片而最终被除去。RF电源114与载物台113连接。RF电源114是用于供给把真空室111内的等离子引入的电力的高频电源。
通过把抗蚀剂层101作为掩模进行蚀刻而在半导体衬底100上形成如图13(d)所示的开口部102。开口部102有时是使用所谓的博世处理(ボツシュプロセス)来形成。所谓博世处理是通过周期性反复进行下面两工序而把半导体衬底垂直地且深地蚀刻的处理，两工序即：使用SF6气体把半导体衬底的表面各向异性地进行蚀刻的等离子蚀刻工序，和使用C4F8气体把碳高分子作为保护膜而向通过等离子蚀刻工序所形成的槽的内壁进行沉积的等离子沉积工序。
然后，把半导体衬底100从真空室111取出来，把半导体衬底100运送到未图示的灰化装置(例如等离子灰化装置)的室内。该灰化装置也基本上与上述的干蚀刻装置100同样，设置有真空室、载物台、保持部件和RF电源等。例如通过利用氧等离子的等离子灰化而把抗蚀剂层101除去。由于被保持部件覆盖的部分不接触等离子而不能适当进行灰化，所以要把保持部件的位置错开而再次进行灰化。
在由于悬伸现象(才一バ——ハング現象)或博世处理等而开口部102的内壁不平坦时，则再次把半导体衬底100从灰化装置向蚀刻装置移动，对开口部102的内壁进行用于平坦化的蚀刻。这是由于若内壁面不平坦，则不能在以后的开口部102内均匀成膜的缘故。在形成开口部102时采取博世处理的情况下，已知有时开口部102的内壁面成为图13(d)所示的波纹状粗糙形状(切削残余形状103)。因此，在使用了博世处理的情况下特别需要进行该平坦化工序。
通过平坦化工序，开口部102的内壁面则如图13(e)所示那样变平坦，能在以后的开口部102内进行均匀成膜。
这样，现有半导体装置制造方法中的蚀刻工序和灰化工序是分别使用各自不同的专用装置进行。
本发明有关的技术例如记载在以下的专利文献中。
专利文献1：(日本)特开2006-12889号公报
如上所述，现有的蚀刻工序和灰化工序是分别使用各自的专用装置进行。因此，在蚀刻工序后有灰化工序的情况下和在灰化工序后有蚀刻工序的情况下，每次都需要运送半导体衬底100，有生产效率明显低下的问题。且在运送时有半导体衬底100产生机械缺陷的可能性。
在蚀刻装置与灰化装置之间运送半导体衬底100时，有保持部件112的拆卸作业和安装作业，因此，难于把保持部件112再次配置到完全相同的位置。如上所述，由于被保持部件112覆盖的部分不能进行适当的蚀刻加工，所以通常不能成为产品芯片。因此，在使用保持部件把半导体衬底固定在载物台上的情况下，在反复进行蚀刻工序和灰化工序的情况下保持部件的位置产生微小的错动，也存在最终产品的可靠性和合格品率恶化的问题。
发明内容
本发明的目的在于提供一种提高生产效率且可靠性和合格品率高的半导体装置及其制造方法。
本发明是鉴于上述课题而开发的，其主要特点如下。即本发明半导体装置的制造方法包括：在半导体衬底的表面上有选择地形成掩模层的工序、把所述掩模层作为掩模在蚀刻装置中对所述半导体衬底进行干蚀刻而在所述半导体衬底上形成开口部的工序、保持将所述半导体衬底配置在所述蚀刻装置内的状态，使用所述蚀刻装置把所述掩模层除去的工序。
本发明半导体装置的制造方法具有：在形成所述掩模层的工序前，通过把所述半导体衬底的一个面进行磨削而把所述半导体衬底减薄的工序、用于把所述半导体衬底的所述一个面进行平坦化的第一平坦化工序，保持把所述半导体衬底配置在所述蚀刻装置中的状态，连续进行除去所述掩模层的工序和所述第一平坦化工序。
本发明半导体装置的制造方法具有把所述开口部的内壁进行平坦化的第二平坦化工序，保持把所述半导体衬底配置在所述蚀刻装置中的状态，连续进行除去所述掩模层的工序和所述第二平坦化工序。
本发明的半导体装置包括：具有从其背面到表面贯通的通路孔的半导体衬底、在所述半导体衬底的表面上为了覆盖所述通路孔而配置的焊盘电极、形成在所述通路孔中而与所述焊盘电极电连接的贯通电极，所述通路孔是在所述半导体衬底的背面侧弯曲且从所述半导体衬底的背面侧到表面侧其开口径变狭窄的正向锥形状，进行了用于使所述通路孔的内壁面平坦化的蚀刻处理。
本发明的半导体装置的制造方法把蚀刻工序和在该蚀刻工序中使用的掩模层除去的工序在一个处理装置中进行。因此，没有现有的在蚀刻装置和灰化装置之间半导体衬底的运送，生产效率提高。而且能减少由半导体衬底运送而引起的不良情况，因此能制造可靠性和合格品率高的半导体装置。
附图说明
图1是说明本发明实施例的半导体装置及其制造方法的剖面图；
图2是说明本发明实施例的半导体装置及其制造方法的剖面图；
图3是说明本发明实施例的半导体装置的制造方法中所使用的蚀刻装置的剖面图；
图4是说明本发明实施例的半导体装置及其制造方法的剖面图；
图5A～5B是说明本发明实施例的半导体装置及其制造方法的剖面图；
图6是说明本发明实施例的半导体装置及其制造方法的剖面图；
图7是说明本发明实施例的半导体装置及其制造方法的剖面图；
图8是说明本发明实施例的半导体装置及其制造方法的剖面图；
图9是说明本发明实施例的半导体装置及其制造方法的剖面图；
图10是说明本发明实施例的半导体装置及其制造方法的剖面图；
图11是说明本发明实施例的半导体装置及其制造方法的剖面图；
图12是说明本发明实施例的半导体装置及其制造方法的剖面图；
图13A～13E是说明现有半导体装置制造方法的剖面图；
图14A～14B是说明现有半导体装置的制造方法中所使用的蚀刻装置的剖面图和俯视图。
附图标记说明
1半导体衬底2第一绝缘膜3焊盘电极
4钝化膜5粘接层6支承体7损伤层
8抗蚀剂层9通路孔10切削残余形状
11第二绝缘膜12抗蚀剂层13势垒层
14籽晶层15贯通电极16配线层17抗蚀剂层
18保护层19导电端子30绝缘膜50蚀刻装置
51真空室52载物台53保持部件54氦层
55RF电源56下部电极57配管58ICP线圈
100半导体衬底101抗蚀剂层102开口部
101切削残余形状110蚀刻装置111真空室
112保持部件113载物台114RF电源
具体实施方式
下面一边参照附图一边说明本发明的实施例。图1至图10是说明本发明实施例的半导体装置制造方法的剖面图。以下说明的制造工序是使用晶片状半导体衬底进行，是以规定的切割线为边界矩阵状形成多个半导体装置，但为了方便，说明形成一个半导体装置的工序。
首先，如图1所示，准备在其表面形成有未图示的电子器件(例如CCD或红外线传感器等受光元件或发光元件，或其他半导体元件)的半导体衬底1。半导体衬底1例如其口径是8英寸(200mm)的尺寸、厚度是300μm～700μm左右。在半导体衬底1的表面形成例如膜厚度2μm的第一绝缘膜2(例如是通过热氧化法或CVD法形成的氧化硅膜或BPSG膜)。
然后，通过喷溅法或镀敷法以及其他的成膜方法形成铝(A1)、铝合金或铜(Cu)等金属层，然后以未图示的抗蚀剂层作为掩模对该金属层进行蚀刻布图。这样，在第一绝缘膜2上形成例如1μm膜厚度的焊盘电极3。焊盘电极3通过未图示的配线与半导体衬底1上的电子器件及其周边元件进行电连接。
然后，例如通过CVD法在半导体衬底1的表面形成覆盖在焊盘电极3一部分上的钝化膜4(例如氮化硅膜)。然后在包含焊盘电极3的半导体衬底1表面上通过环氧树脂、抗蚀剂和丙烯等粘接层5粘贴支承体6。支承体6可以是膜状的保护带，也可以是玻璃、石英、陶瓷、塑料和金属等刚性的基板，也可以是由树脂构成。支承体6是刚性基板，牢固地支撑着薄型化的半导体衬底1，这在进行不通过人手的运送自动化上是优选的。支承体6在支承半导体衬底1的同时，具有保护其元件表面的功能。
然后，使用背面磨削装置(磨床)对半导体衬底1的背面进行背研磨，把半导体衬底1磨削成规定的厚度(例如100μm～150μm)。通过该背研磨，半导体衬底1的背面并不完全平坦，而是产生凹凸等机械损伤层7。图2以比现实情况夸张的方式描绘了损伤层7。该磨削工序也可以是蚀刻处理，也可以是磨削与蚀刻处理并用。若不需要把半导体衬底1薄膜化则不需要进行该工序。
然后如图2所示，利用光刻技术在半导体衬底1的背面上有选择地形成抗蚀剂层8。抗蚀剂层8在半导体衬底1的背面中与焊盘电极3对应的位置处具有开口部。本实施例把抗蚀剂层作为掩模层使用，但也可以把氧化硅膜或氮化硅膜等绝缘膜作为掩模层使用。目前在背研磨后进行损伤层7的除去，但本实施例中与后述的灰化工序或通路孔内壁的平坦化工序连续进行。因此，与目前相比半导体衬底1的运送作业变少，提高了生产效率。且还有利用损伤层7的凹凸形状来提高抗蚀剂层8对半导体衬底1的贴紧性的优点。
然后，把该抗蚀剂层8作为掩模，利用博世处理对半导体衬底1的规定区域进行蚀刻。具体说就是如图3所示，把半导体衬底1载置在蚀刻装置50的真空室51内设置的载物台52上，用保持部件53进行机械固定。保持部件53配置在半导体衬底1外周数毫米的部分处。
也能通过公知的静电吸附方式把半导体衬底1保持在载物台52上，但当支承体6是玻璃等有绝缘性时则不能得到足够的吸附力。因此，本实施例使用保持部件53把半导体衬底1进行机械固定。在能得到足够的静电吸附力的情况下、或没有后述氦层54泄漏的问题时，则也可以不使用保持部件53而用静电吸附方式把半导体衬底固定在载物台上。只要静电吸附方式是可能的，则与使用保持部件53的情况相比，能够与基板外周无间隙地进行蚀刻工序或灰化工序等，且对基板的机械损伤少，因此有合格品率好的优点。所谓静电吸附方式是在载物台上设置感应层，向载物台与半导体衬底之间施加电压，利用两者之间产生的力来吸附半导体衬底的方式。
然后，从载物台52侧通过未图示的配管使氦(He)气流入，在支承体6与载物台52之间形成氦层54。该氦层54是用于冷却基板的层。通过该氦层54使载物台52的温度反映到半导体衬底1侧，使面内温度均匀，使对于半导体衬底1整个面的蚀刻加工精度均匀。
保持部件53固定半导体衬底1，而且通过从上方按压而具有防止氦层54从载物台向外部过度泄漏的功能。通过RF电源55把交流电压向下部电极56供给。真空室51设置有用于导入成为蚀刻气体或灰化气体的气体的配管57、该气体的排气管(未图示)和真空泵(未图示)等。还设置有用于向等离子源供给电力的ICP线圈58。
蚀刻装置50例如使用ICP(Inductively Coupled Plasma：感应耦合等离子)型的蚀刻装置。IPC型的蚀刻装置是通过向ICP线圈供给高频电力的感应结合放电方式而使所供给的反应气体在真空室内被等离子化，使用该高密度等离子来进行对象物蚀刻的装置。
使用蚀刻装置50，以压力：10～50mTorr、SF6气体流量：300～400scc/min、O2气体流量：30～40scc/min、ICP功率：1500～2000W、下部电极：20～30W的条件进行等离子蚀刻工序，以压力：20～30mTorr、C4F8气体流量：150～200scc/min、ICP功率：1200～1700W的条件进行等离子沉积工序，以切换时间：10sec/5sec的周期进行。
如图4所示，通过该博世处理在半导体衬底1上形成贯通厚度方向的通路孔9(开口部)，同时通路孔9的内壁面成为切削残余形状10。通路孔9的开口直径例如是30～50μm左右，其深度例如是100μm～150μm左右，切削残余形状10的槽的高差例如是6000埃左右。当SF6气体向横方向的侧蚀刻量多时，则切削残余形状10的高差就大。
由于越靠近通路孔9的底部侧(图4的下侧)蚀刻率越小，所以实际上通路孔9的底部侧比上部侧(图4的上侧)的切削残余形状10的高差浅，是接近平坦的状态。同图中通路孔9是直线形状，但若使用博世处理，则有成为正向锥形状(随着朝向深度方向开口的直径变狭窄的形状)的倾向。
也有通过不使用博世处理的蚀刻来形成通路孔9的情况。虽然未图示，但也可以使通路孔9不贯通半导体衬底1，也可以其底部在半导体衬底1的中间。
然后在与形成上述通路孔9的蚀刻中所使用的蚀刻装置50同一装置中，把真空室51内的气体种类改变成灰化用气体，压力、装置电力等各条件也改变，如图5(a)或图5(b)所示那样把抗蚀剂层8进行等离子除去(灰化)。即，该灰化工序是把半导体衬底1配置在真空室51内不动而与上述蚀刻工序连续进行。灰化工序例如以压力：10～50mTorr、O2气体流量：150～200scc/min、ICP功率：2000～3000W、下部电极：20～30W的条件进行。在不是使用抗蚀剂层8，而是把氧化硅膜或氮化硅膜等绝缘膜作为掩模层使用时，把装置内的压力、气体等条件最优化成除去绝缘膜的条件来除去掩模层。
然后把真空室51内的气体种类从灰化用气体改变成蚀刻气体，压力、装置电力等各条件也改变。通过干蚀刻法把半导体衬底1背面的平坦化(除去损伤层7)和通路孔9内壁的平坦化(除去切削残余形状10)同时进行。
干蚀刻后的通路孔9可以是图5(a)所示那样的直线形状，但通过改变干蚀刻的条件，则也可以如图5(b)所示那样，成为通路孔9的上部(半导体衬底1的背面侧)圆滑地弯曲的正向锥形状。通路孔9的形状是正向锥形状的情况与是直线形状的情况相比，具有在通路孔9内能进行膜厚度均匀性高的成膜的优点。
这样，半导体衬底1背面的平坦化和通路孔9内壁的平坦化能把半导体衬底1配置在蚀刻装置50的真空室51内不动而连续进行形成通路孔9和除去抗蚀剂层8。该损伤层7的除去和通路孔9内壁的平坦化例如以压力：20～80mTorr、SF6气体流量：500～600scc/min、O2气体流量：0～60scc/min、ICP功率：1500～2500W、下部电极：50～100W的条件进行。基于提高切削残余形状10改善效果的观点，即，基于使通路孔9的内壁更加平坦化的观点，最好是在低压、高功率、SF4气体浓的条件下进行。
然后根据需要进行湿式处理，把抗蚀剂层8完全除去。这是由于被保持部件53覆盖的部位残留有抗蚀剂层8而也有可能给下一工序带来不好影响。
然后把通路孔9内露出的第一绝缘膜2蚀刻除去，使第一绝缘膜2露出来。
然后如图6所示，在包含有通路孔9内壁的半导体衬底1背面的整个面上形成第二绝缘膜11(例如通过CVD法形成氧化硅膜或氮化硅膜)。该第二绝缘膜11把半导体衬底1与导电性部件(后述的势垒层13、籽晶层14、贯通电极15、配线层16)进行绝缘。
然后如图7所示，在半导体衬底1的背面有选择地形成抗蚀剂层12，以该抗蚀剂层12作为掩模把通路孔9底部的第二绝缘膜11蚀刻除去。通过该蚀刻使焊盘电极3的一部分露出来。然后通过灰化工序把抗蚀剂层12除去。
至于该第二绝缘膜11的蚀刻工序和抗蚀剂层12的除去工序也是在同一蚀刻装置中连续进行。
第二绝缘膜11在半导体衬底1的背面最厚，也可以利用随着朝向通路孔9内的侧壁和底部而形成得薄的倾向而没有掩模(抗蚀剂层12)地来进行该蚀刻。通过没有掩模的蚀刻还能谋求制造处理的合理化。也可以把所述第一绝缘膜2和第二绝缘膜11在同一蚀刻工序中除去。
然后如图8所示，在通路孔9内和半导体衬底1的背面上形成势垒层13。势垒层13通过溅射法、PVD法、CVD法和其他的成膜方法形成。势垒层13例如由钛(Ti)层、钛渗氮(TiN)层、钽(Ta)层、钽渗氮(TaN)层、钛钨(TiW)层、钨渗氮(WN)层、锆渗氮(ZrN)层等构成。
势垒层13具有防止后面在通路孔9内形成的贯通电极15的金属材料的扩散、防止该金属材料与导电体(本实施例的焊盘电极3)的相互反应和提高半导体衬底1与后述的贯通电极15的贴紧性等作用。只要是有这些作用，则其材质没有特别的限定，也可以是单层或是层合。层合结构由已经说明过的材质等组合构成，例如是钛层/钛渗氮层。
然后，如该图所示那样在势垒层13上形成籽晶层14。籽晶层14是用于镀敷形成后述的贯通电极15和配线层16的作为基底电极的导电层，例如由铜(Cu)、钌(Ru)、钯(Pb)等金属构成。籽晶层14通过溅射法、PVD法、CVD法和其他的成膜方法形成。籽晶层14的膜厚度例如是50nm左右。由于通路孔9的内壁面被平坦化，所以势垒层13和籽晶层14的覆盖性良好。
然后，如该图所示那样在包扩通路孔9内部的籽晶层14上、通过例如把籽晶层14作为镀敷电极的电镀法形成由铜(Cu)构成的贯通电极15和与之连续并连接的配线层16。贯通电极15是在通路孔12内形成的导电层。贯通电极15和配线层16通过势垒层13和籽晶层14而与在通路孔9的底部露出的焊盘电极3电连接。由于通路孔9的内壁面被平坦化，所以能形成良好的贯通电极15和配线层16。
贯通电极15也可以不把通路孔9内部完全填充，也可以如图11所示那样不完全填充。根据该结构，能节约形成贯通电极15和配线层16所需要的导电材料，而且与完全填充的情况相比能以短时间形成贯通电极15和配线层16，因此有提高生产率的优点。
然后如图9所示，在半导体衬底1背面的配线层16上有选择地形成用于形成配线图形的抗蚀剂层17。然后以抗蚀剂层17作为掩模把不需要部分的配线层16和籽晶层14蚀刻除去。通过该蚀刻配线层16被布图成规定的配线图形。接着以配线层16作为掩模把在半导体衬底1背面形成的势垒层13有选择地蚀刻除去。
以该抗蚀剂层17作为掩模的各层(配线层16、籽晶层、势垒层13)的蚀刻工序和抗蚀剂层17的除去工序，也是在同一蚀刻装置中连续进行，这从提高生产效率的观点出发是优选的。
势垒层13、籽晶层14、贯通电极15、配线层16的形成并不限于上述工序。
然后如图10所示，在半导体衬底1的背面上形成例如由焊料抗蚀剂的有机材料或氮化硅膜等的无机材料构成的保护层18。保护层18中把预定形成导电端子的区域开口，在从该开口露出的配线层16上形成由镍(Ni)和金(Au)构成的电极连接层(未图示)。然后在该电极连接层上网板印刷焊锡，通过使该焊锡在热处理中回流而形成球状的导电端子19。
导电端子19的形成方法也可以是使用分配器把由焊锡等构成的球状端子等进行涂布的所谓分配法(涂布法)或电镀法等形成。作为其他实施例也有不形成导电端子19的情况。这时，电极连接层或配线层16成为从保护层18的开口露出的状态。该电极连接层或配线层16与其他装置的电极连接。
支承体6可以粘贴在半导体衬底1上不动，或也可以从半导体衬底1剥离而再利用。
通过以上的工序，从半导体衬底1的表面形成的导电体(焊盘电极3)直到在其背面形成的导电体(配线层16、导电端子19)的配线通过通路孔9完成芯片尺寸组件型的半导体装置。把该半导体装置向电子机器组装时，通过把导电端子19安装在电路基板上的配线图形上来与外部电路进行电连接。
这样，由于本实施例在同一蚀刻装置内保持配置半导体衬底的状态而把蚀刻工序和在该蚀刻工序中使用的掩模层除去的工序连续进行，因此，半导体衬底的移动比现有技术少。因此，制造工序的时间缩短，生产效率提高，而且能提高半导体装置的可靠性和合格品率。且由于不需要准备蚀刻工序和掩模层除去工序各自专用的装置，所以制造成本也降低。
由于本实施例把除去背研磨产生的损伤层与掩模层的除去工序和通路孔内壁面的平坦化工序在同一处理装置内连续进行，所以与现有技术相比制造工艺被合理化。
由于进行半导体衬底背面和通路孔内壁面的平坦化，所以能在半导体衬底的背面和通路孔内进行膜厚度均匀性高的成膜。例如在溅射工序中能谋求溅射粒子对通路孔9内壁附着量的均匀化。在CVD法的情况下也能使反应气体均匀到达内壁面而防止覆盖不足。没有由切削残余形状等凹凸而引起的覆盖不充分的担心，不需要进行过度的成膜。因此生产性提高，还能把通路孔内形成的膜厚度减薄。
切削残余形状不会反映到以后的成膜中，能形成可靠性高的镀层。由于能使在通路孔9内壁上形成的各种膜全部良好地形成，所以半导体装置的可靠性和合格品率提高。
以上实施例说明了具有球状导电端子19的BGA(Ball Grid Array：球栅阵列)型半导体装置，但本发明即使适用在没有球状导电端子的LGA(Land  Grid Array：面栅阵列)型或其他的CSP型、倒装片型的半导体装置上也可以。
当然本发明并不限于上述实施例，而是在不脱离其要旨的范围可有变更。
例如上述实施例在半导体衬底1的表面侧(元件面侧)粘贴了支承体，但也可以如图12所示那样在其他面侧(非元件面侧)粘贴支承体6来制造所希望的半导体装置。该半导体装置在半导体衬底1的表面侧(元件面侧)形成焊盘电极3、配线层16、导电端子19等。把该半导体装置向电子设备组装时，通过把导电端子19与电路基板上的配线图形进行安装而与外部电路电连接。把支承体6剥离除去后，把半导体衬底1背面上的与贯通电极15对应位置处的绝缘膜30(例如通过CVD法形成的氧化硅膜)开口，使其他半导体装置的导电端子与该开口连接，还能谋求半导体装置的层合。图12中对于与已经说明过的结构相同的结构使用相同的附图标记，而省略其说明。这样，即使把支承体粘贴在半导体衬底的任何面上也可以。

Claims (7)

1.一种半导体装置的制造方法，其特征在于，具有：通过把半导体衬底的一个面进行磨削而把所述半导体衬底减薄的工序、
在所述半导体衬底的表面上有选择地形成掩模层的工序、
把所述掩模层作为掩模在蚀刻装置中对所述半导体衬底进行干蚀刻而在所述半导体衬底上形成开口部的工序、
把所述掩模层除去的工序、
用于把所述半导体衬底的一个面进行平坦化的第一平坦化工序，
在保持将所述半导体衬底配置在所述蚀刻装置中的状态下，连续进行除去所述掩模层的工序和所述第一平坦化工序。
2.如权利要求1所述的半导体装置的制造方法，其特征在于，具有把所述开口部的内壁平坦化的第二平坦化工序，在保持将所述半导体衬底配置在所述蚀刻装置中的状态下，连续进行除去所述掩模层的工序和所述第二平坦化工序。
3.如权利要求1所述的半导体装置的制造方法，其特征在于，形成所述开口部的工序包括：
用于在所述半导体衬底上形成槽的等离子蚀刻工序、
向所述槽的内壁沉积保护膜的等离子沉积工序、
把所述等离子蚀刻工序和所述等离子沉积工序交替反复进行的工序。
4.如权利要求1所述的半导体装置的制造方法，其特征在于，所述蚀刻装置是感应耦合等离子型蚀刻装置。
5.如权利要求1所述的半导体装置的制造方法，其特征在于，具有：
在所述半导体衬底开口部的内壁上形成绝缘膜的工序、
在所述绝缘膜上形成贯通电极的工序。
6.一种半导体装置的制造方法，其特征在于，具有在所述半导体衬底的表面上有选择地形成掩模层的工序、
把所述掩模层作为掩模在蚀刻装置中对所述半导体衬底进行干蚀刻而在所述半导体衬底上形成开口部的工序、
把所述掩模层除去的工序、
把所述开口部的内壁进行平坦化的第二平坦化工序，
在保持将所述半导体衬底配置在所述蚀刻装置中的状态下，连续进行除去所述掩模层的工序和所述第二平坦化工序。
7.如权利要求2或6所述的半导体装置的制造方法，其特征在于，把所述开口部的内壁平坦化的第二平坦化工序，包括所述半导体衬底的背面侧弯曲且从所述半导体衬底的背面侧到表面侧其开口部变狭窄而形成的工序。
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